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Power 6/32 Unix version 1.21
#include "evt_defs.h"
#define MAX_POS 0x7fffffff;
/*
*********************************************************************
* FPP PIPELINED EVENTS TEST #6
*
* This test will execute the following code: "LDD MULD ADDL2 MULD 0"
* with an integer overflow fault on the ADDL2. We will make sure that:
* 1. The fault is detected,
* 2. the 1st multiply operation completes, and
* 3. the 2nd multiply instruction is not executed.
*
* NOTE: this instruction uses the same data as pipe2
*********************************************************************
*/
pipe6()
{
asm("moval (r13),_pre_event_fp"); /* save the frame pointer */
asm("moval (r14),_pre_event_sp"); /* save the stack pointer */
precision = DBL;
test_event = ARITH_CODE; /* expect an arithmetic fault */
exp_code = INT_OVFL_CODE; /* -specificly int overflow */
exp_event = FALSE; /* ... but not yet */
asm("movab _pipe6_ret,_event_return"); /* set post event return addr */
dbl_value_2.m = dbl_value_2.l = 0; /* clear the 2nd MULD operand */
for( index = 0; index < max_pipe2_index; index++ )
{
sgl_value_1 = 0x789abcde; /* get the integer ovfl data */
sgl_value_2 = MAX_POS; /* max integer (7fffffff) */
dbl_ld_acc = pipe2_data[index].op_1; /* get the data */
dbl_value_1 = pipe2_data[index].op_2;
dbl_expected = pipe2_data[index].exp;
asm(".globl _pipe6_lp1");
asm("_pipe6_lp1:");
asm("bispsw $0x60"); /* enable ovfl,undfl */
asm("ldd _dbl_ld_acc"); /* load the Acc. */
exp_event = test_event; /* expect event soon */
asm("muld _dbl_value_1"); /* start the multiply*/
asm("addl2 _sgl_value_1,_sgl_value_2"); /* trigger the fault */
asm("muld _dbl_value_2"); /* shouldn't get here*/
/*
* If we got to here then there was no event
*/
if( force_loop )
asm("brw _pipe6_lp1");; /* loop on the error */
exp_event = FALSE; /* reset event expected flag */
asm("movl _pre_event_fp,fp"); /* restore the frame pointer */
asm("movl _pre_event_sp,sp"); /* restore the stack pointer */
asm("bicpsw $0x60"); /* disable ovfl & undfl evts */
no_pipe6_evt();; /* report the error */
/*
* Come here after the event
*/
asm(".globl _pipe6_ret");
asm("_pipe6_ret:");
asm("movl _pre_event_fp,fp"); /* restore the frame pointer */
asm("movl _pre_event_sp,sp"); /* restore the stack pointer */
if( force_loop )
asm("brw _pipe6_lp1");; /* loop on the error */
asm("bicpsw $0x60"); /* disable ovfl & undfl evts */
if( (post_evt_acc.m != dbl_expected.m) ||
(post_evt_acc.l != dbl_expected.l) )
{
if( (!post_evt_acc.m) && (!post_evt_acc.l) )
pipe6_queue_er(); /* queue not cleared error */
else
bad_pipe6_result(); /* incorrect result error */
}
}
}
/****************************************************************************
* Report an "EVENT NOT DETECTED" error
*
* Cycle: xx. EVT test xx. subtest xx. No Integer Overflow fault. index = xx
* inst = LDD op1, MULD op2, ADDL2 op3,op4, MULD op5 (Int. Overflow on ADDL2)
* op1 = xxxxxxxx xxxxxxxx, op3 = xxxxxxxx
* op2 = xxxxxxxx xxxxxxxx, initial op4 = xxxxxxxx, final op4 = xxxxxxxx
****************************************************************************/
no_pipe6_evt()
{
errcnt++; /* bump the error count */
if ( prt_error )
{
print_pipe6_err( " No Integer Overflow fault." );
writes("op1 = ");
write32h( dbl_ld_acc.m );
writes(" ");
write32h( dbl_ld_acc.l );
writes(", op3 = ");
write32h( sgl_value_1 );
writes("\nop2 = ");
write32h( dbl_value_1.m );
writes(" ");
write32h( dbl_value_1.l );
writes(", initial op4 = ");
sgl_dummy1 = MAX_POS;
write32h( sgl_dummy1 );
writes(", final op4 = ");
write32h( sgl_value_2 );
writec('\n');
}
if ( halt_flg ) /* halt on error? */
pipe6_halt( 1 ); /* halt with a code of 1 */
if ( loop_on_err )
{
force_loop = TRUE; /* set the force loop flag */
asm("jmp _pipe6_lp1"); /* and loop */
};
}
/****************************************************************************
* Report an "BAD ACCUMULATOR AFTER THE EVENT" error
*
* Cycle: xx. EVT test xx. subtest xx. . Bad final Accumulator. index = xx
* inst = LDD op1, MULD op2, ADDL2 op3,op4, MULD op5 (Int. Overflow on ADDL2)
* The 2nd MULD should not be executed.
* op1 = xxxxxxxx xxxxxxxx, final Acc. = xxxxxxxx xxxxxxxx
* op2 = xxxxxxxx xxxxxxxx, expected = xxxxxxxx xxxxxxxx
* op5 = xxxxxxxx xxxxxxxx
****************************************************************************/
bad_pipe6_result()
{
errcnt++; /* bump the error count */
if ( prt_error )
{
print_pipe6_err( ". Bad final Accumulator." );
writes("The 2nd MULD should not be executed\n");
writes("op1 = ");
write32h( dbl_ld_acc.m );
writes(" ");
write32h( dbl_ld_acc.l );
writes(", final Acc. = ");
write32h( post_evt_acc.m );
writec(' ');
write32h( post_evt_acc.l );
writes("\nop2 = ");
write32h( dbl_value_1.m );
writes(" ");
write32h( dbl_value_1.l );
writes(", expected = ");
write32h( dbl_expected.m );
writes(" ");
write32h( dbl_expected.l );
writes("\nop5 = ");
write32h( dbl_value_2.m );
writes(" ");
write32h( dbl_value_2.l );
writec('\n');
}
if ( halt_flg ) /* halt on error? */
pipe6_halt( 2 ); /* halt with a code of 2 */
if ( loop_on_err )
{
force_loop = TRUE; /* set the force loop flag */
asm("jmp _pipe6_lp1"); /* and loop */
};
}
/****************************************************************************
* Report an "FPP Queue not cleared" error
*
* Cycle: xx. EVT test xx. subtest xx. . FPP queue not cleared. index = xx
* inst = LDD op1, MULD op2, ADDL2 op3,op4, MULD op5 (Int. Overflow on ADDL2)
* The 2nd MULD should not have been executed but apparently was.
* op1 = xxxxxxxx xxxxxxxx, final Acc. = xxxxxxxx xxxxxxxx
* op2 = xxxxxxxx xxxxxxxx, expected = xxxxxxxx xxxxxxxx
* op5 = xxxxxxxx xxxxxxxx
****************************************************************************/
pipe6_queue_er()
{
errcnt++; /* bump the error count */
if ( prt_error )
{
print_pipe6_err( ". FPP queue not cleared." );
writes(
"The 2nd MULD should not have been executed but apparently was.\n");
writes("op1 = ");
write32h( dbl_ld_acc.m );
writes(" ");
write32h( dbl_ld_acc.l );
writes(", final Acc. = ");
write32h( post_evt_acc.m );
writec(' ');
write32h( post_evt_acc.l );
writes("\nop2 = ");
write32h( dbl_value_1.m );
writes(" ");
write32h( dbl_value_1.l );
writes(", expected = ");
write32h( dbl_expected.m );
writes(" ");
write32h( dbl_expected.l );
writes("\nop5 = ");
write32h( dbl_value_2.m );
writes(" ");
write32h( dbl_value_2.l );
writec('\n');
}
if ( halt_flg ) /* halt on error? */
pipe6_halt( 3 ); /* halt with a code of 3 */
if ( loop_on_err )
{
force_loop = TRUE; /* set the force loop flag */
asm("jmp _pipe6_lp1"); /* and loop */
};
}
/****************************************************************************
* Report an error message of the form
*
* Cycle: xx. EVT test xx. subtest xx. <your message here> index = xx
* inst = LDD op1, MULD op2, ADDL2 op3,op4, MULD op5 (Int. Overflow on ADDL2)
****************************************************************************/
print_pipe6_err( msg )
char *msg; /* pointer to error message */
{
if( errcnt == 1 ) /* 1st error? */
writes(" \n"); /* start a new print line */
writes("Cycle: ");
writed( cycle );
writes(" EVT test ");
writed( test_no );
writes(". subtest ");
writed( subtest );
writes( msg ); /* print the error message */
writes(" index = ");
writed( index );
writes("\ninst = LDD op1, MULD op2, ADDL2 op3,op4, MULD op5");
writes(" (Integer Overflow on ADDL2)\n");
}
/****************************************************************************
* Error Halt Routine
****************************************************************************/
pipe6_halt( code )
int code; /* halt code to use */
{
err_code = code;
sgl_value_3 = MAX_POS; /* initial op4 data */
sgl_value_4 = dbl_ld_acc.m;
sgl_value_5 = dbl_ld_acc.l;
sgl_value_6 = dbl_value_1.m;
sgl_value_7 = dbl_value_1.l;
asm("movl _test_no,r0"); /* r0 = test number */
asm("movl _subtest,r1"); /* r1 = subtest number */
asm("movl _err_code,r2"); /* r2 = error code */
asm("movl _cycle,r3"); /* r3 = cycle count */
asm("movl _sgl_value_4,r4"); /* r4 = MSW of operand 1 */
asm("movl _sgl_value_5,r5"); /* r5 = LSW of operand 1 */
asm("movl _sgl_value_6,r6"); /* r6 = MSW of operand 2 */
asm("movl _sgl_value_7,r7"); /* r7 = LSW of operand 2 */
if( code == 1 ) {
asm("movl _sgl_value_1,r8"); /* r8 = operand 3 */
asm("movl _sgl_value_3,r9"); /* r9 = operand 2, initial */
asm("movl _sgl_value_2,r10"); /* r10 = operand 2, final */
asm("movl _index,r11"); /* r11 = data index */
asm("halt"); /* HALT ... */
} else {
sgl_value_1 = post_evt_acc.m;
sgl_value_2 = post_evt_acc.l;
sgl_value_3 = dbl_expected.m;
sgl_value_4 = dbl_expected.l;
sgl_value_5 = dbl_value_2.m;
sgl_value_6 = dbl_value_2.l;
asm("movl _sgl_value_1,r8"); /* r8 = MSW of final acc. */
asm("movl _sgl_value_2,r9"); /* r9 = LSW of final acc. */
asm("movl _sgl_value_3,r10"); /* r10 = MSW of expected */
asm("movl _sgl_value_4,r11"); /* r11 = LSW of expected */
asm("movl _sgl_value_5,r12"); /* r12 = MSW of 2nd MULD op */
asm("movl _sgl_value_6,r13"); /* r13 = LSW of 2nd MULD op */
asm("movl _index,r14"); /* r14 = data index */
}
asm("halt"); /* HALT ... */
}
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