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1.1 root 1: 1 00000000 LL0:
2: 2 00000000 .data
3: 3 00000218 * .text
4: 4 00000000 .align 1
5: 5 00000000 .globl _resop_test
6: 6 00000000 _resop_test:
7: 7 0000E02C 0000 .word L381
8: 8 0000E02E #
9: 9 0000E02E # #include "evt_defs.h"
10: 10 0000E02E #
11: 11 0000E02E # /*
12: 12 0000E02E # ********************************************************************
13: 13 0000E02E # *
14: 14 0000E02E # * MONITOR FOR THE FPP RESERVED OPERAND EVENT TEST
15: 15 0000E02E # *
16: 16 0000E02E # * 22-Mar-85 : written
17: 17 0000E02E # * 16-Jul-85 : changed to match "resop_tbl" changes
18: 18 0000E02E # * 24-Jul-85 : don't run LOGF with the "no-fpp" firmware
19: 19 0000E02E # *
20: 20 0000E02E # ********************************************************************
21: 21 0000E02E # */
22: 22 0000E02E # resop_test()
23: 23 0000E02E # {
24: 24 0000E02E 13 00c4 jbr L383
25: 25 0000E031 L384:
26: 26 0000E031 # event_msg = "Reserved Operand";
27: 27 0000E031 .data 1
28: 28 00000218 * L385:
29: 29 00000218 * 5265736572766564204F70657 .ascii "Reserved Operand\0"
30: 2616E6400
31: 30 00000229 * .text
32: 31 0000E031 0d 8f00000218 effffffff0 movl $L385,_event_msg
33: 32 0000E03C # test_event = RESOP_CODE;
34: 33 0000E03C 0d 2d efffffffe9 movl $45,_test_event
35: 34 0000E043 # disable_mask = 0; /* don't disable any events */
36: 35 0000E043 4b efffffffe3 clrw _disable_mask
37: 36 0000E049 # evt_disabled = FALSE; /* expected event is enabled */
38: 37 0000E049 4d efffffffdd clrl _evt_disabled
39: 38 0000E04F # if( evt_inst ) { /* was the op-code specified? */
40: 39 0000E04F 5d efffffffd7 tstl _evt_inst
41: 40 0000E055 31 62 jeql L386
42: 41 0000E057 # inst_index = get_resop_index( evt_inst );
43: 42 0000E057 dd efffffffcf pushl _evt_inst
44: 43 0000E05D fe 08 ef00000182 callf $8,_get_resop_index
45: 44 0000E064 0d 50 efffffffc1 movl r0,_inst_index
46: 45 0000E06B # if( inst_index < 0 ) {
47: 46 0000E06B 5d efffffffbb tstl _inst_index
48: 47 0000E071 81 3d jgeq L388
49: 48 0000E073 # if( (prt_hdrs) && (cycle == 1) ) { /* no reserved ops */
50: 49 0000E073 5d efffffffb3 tstl _prt_hdrs
51: 50 0000E079 31 33 jeql L389
52: 51 0000E07B 1d efffffffab 01 cmpl _cycle,$1
53: 52 0000E082 21 2a jneq L389
54: 53 0000E084 # writes(
55: 54 0000E084 # "There are no floating RESERVED OPERANDS with op-code" );
56: 55 0000E084 .data 1
57: 56 00000229 * L391:
58: 57 00000229 * 546865726520617265206E6F2 .ascii "There are no floating RESERVED OPERANDS with op-code\0"
59: 0666C6F6174696E6720524553
60: 4552564544204F504552414E4
61: 4532077697468206F702D636F
62: 646500
63: 58 0000025e * .text
64: 59 0000E084 dd 8f00000229 pushl $L391
65: 60 0000E08A fe 08 efffffff9b callf $8,_writes
66: 61 0000E091 # writeh( evt_inst ); /* print the ersatz op-code */
67: 62 0000E091 dd efffffff95 pushl _evt_inst
68: 63 0000E097 fe 08 efffffff8e callf $8,_writeh
69: 64 0000E09E # writec('\n');
70: 65 0000E09E dd 0a pushl $10
71: 66 0000E0A0 fe 08 efffffff85 callf $8,_writec
72: 67 0000E0A7 # error = TRUE; /* needed for line feed control */
73: 68 0000E0A7 0d 01 efffffff7e movl $1,_error
74: 69 0000E0AE # }
75: 70 0000E0AE # } else
76: 71 0000E0AE L389:
77: 72 0000E0AE 11 07 jbr L394
78: 73 0000E0B0 L388:
79: 74 0000E0B0 # test_resop_inst(); /* test the instruction */
80: 75 0000E0B0 fe 04 ef00000041 callf $4,_test_resop_inst
81: 76 0000E0B7 L394:
82: 77 0000E0B7 # } else /* test all applicable op-codes */
83: 78 0000E0B7 11 3b jbr L396
84: 79 0000E0B9 L386:
85: 80 0000E0B9 # for(inst_index=0; inst_index < size_resop_tbl; inst_index++)
86: 81 0000E0B9 4d efffffff6d clrl _inst_index
87: 82 0000E0BF L399:
88: 83 0000E0BF 1d efffffff67 efffffff62 cmpl _inst_index,_size_resop_tbl
89: 84 0000E0CA 81 28 jgeq L398
90: 85 0000E0CC # if( (!no_fpp_wcs) ||
91: 86 0000E0CC # (resop_tbl[inst_index].inst_code != LOGF_OP_CODE) )
92: 87 0000E0CC 5d efffffff5a tstl _no_fpp_wcs
93: 88 0000E0D2 31 11 jeql L9999
94: 89 0000E0D4 5c 18 efffffff51 50 mull3 $24,_inst_index,r0
95: 90 0000E0DC 1d e000000000 35 cmpl _resop_tbl(r0),$53
96: 91 0000E0E3 31 07 jeql L400
97: 92 0000E0E5 L9999:
98: 93 0000E0E5 # test_resop_inst();
99: 94 0000E0E5 fe 04 ef0000000c callf $4,_test_resop_inst
100: 95 0000E0EC # }
101: 96 0000E0EC L400:
102: 97 0000E0EC L397:
103: 98 0000E0EC 6d efffffff3a incl _inst_index
104: 99 0000E0F2 11 cb jbr L399
105: 100 0000E0F4 L398:
106: 101 0000E0F4 L396:
107: 102 0000E0F4 40 ret#2
108: 103 0000E0F5 .set L381,0x0
109: 104 0000E0F5 L383:
110: 105 0000E0F5 13 ff39 jbr L384
111: 106 0000E0F8 .data
112: 107 00000218 * .text
113: 108 0000E0F8 .align 1
114: 109 0000E0F8 .globl _test_resop_inst
115: 110 0000E0F8 _test_resop_inst:
116: 111 0000E0F8 0000 .word L401
117: 112 0000E0FA #
118: 113 0000E0FA #
119: 114 0000E0FA #
120: 115 0000E0FA # /*
121: 116 0000E0FA # ***************************************************************************
122: 117 0000E0FA # *
123: 118 0000E0FA # * Run the Reserved Operand Fault on one instruction
124: 119 0000E0FA # *
125: 120 0000E0FA # ***************************************************************************
126: 121 0000E0FA # */
127: 122 0000E0FA # test_resop_inst()
128: 123 0000E0FA # {
129: 124 0000E0FA 13 00e5 jbr L403
130: 125 0000E0FD L404:
131: 126 0000E0FD # valid_test = TRUE; /* a test is being run */
132: 127 0000E0FD 0d 01 efffffff28 movl $1,_valid_test
133: 128 0000E104 # op_code = resop_tbl[ inst_index ].inst_code;
134: 129 0000E104 5c 18 efffffff21 50 mull3 $24,_inst_index,r0
135: 130 0000E10C 0d e000000000 efffffff15 movl _resop_tbl(r0),_op_code
136: 131 0000E117 # op_name = resop_tbl[ inst_index ].name;
137: 132 0000E117 5c 18 efffffff0e 50 mull3 $24,_inst_index,r0
138: 133 0000E11F 0d e000000004 efffffff02 movl _resop_tbl+4(r0),_op_name
139: 134 0000E12A # precision = resop_tbl[ inst_index ].precision;
140: 135 0000E12A 5c 18 effffffefb 50 mull3 $24,_inst_index,r0
141: 136 0000E132 0d e00000000c effffffeef movl _resop_tbl+12(r0),_precision
142: 137 0000E13D # no_ops = resop_tbl[ inst_index ].no_operands;
143: 138 0000E13D 5c 18 effffffee8 50 mull3 $24,_inst_index,r0
144: 139 0000E145 0d e000000008 effffffedc movl _resop_tbl+8(r0),_no_ops
145: 140 0000E150 # data_ptr = resop_tbl[ inst_index ].evt_data;
146: 141 0000E150 5c 18 effffffed5 50 mull3 $24,_inst_index,r0
147: 142 0000E158 0d e000000010 effffffec9 movl _resop_tbl+16(r0),_data_ptr
148: 143 0000E163 # max_index = *resop_tbl[ inst_index ].evt_data_cnt;
149: 144 0000E163 5c 18 effffffec2 50 mull3 $24,_inst_index,r0
150: 145 0000E16B 0d f000000014 effffffeb6 movl *_resop_tbl+20(r0),_max_index
151: 146 0000E176 # if( precision == SGL ) {
152: 147 0000E176 1d effffffeb0 01 cmpl _precision,$1
153: 148 0000E17D 21 10 jneq L405
154: 149 0000E17F # sgl_op = TRUE;
155: 150 0000E17F 0d 01 effffffea6 movl $1,_sgl_op
156: 151 0000E186 # acc_ld_size = SGL; /* use a sgl precision Acc. */
157: 152 0000E186 0d 01 effffffe9f movl $1,_acc_ld_size
158: 153 0000E18D # } else {
159: 154 0000E18D 11 0d jbr L406
160: 155 0000E18F L405:
161: 156 0000E18F # sgl_op = FALSE;
162: 157 0000E18F 4d effffffe97 clrl _sgl_op
163: 158 0000E195 # acc_ld_size = DBL; /* use a dbl precision Acc. */
164: 159 0000E195 0d 02 effffffe90 movl $2,_acc_ld_size
165: 160 0000E19C # }
166: 161 0000E19C L406:
167: 162 0000E19C # if( (prt_hdrs) && (cycle == 1) ) {
168: 163 0000E19C 5d effffffe8a tstl _prt_hdrs
169: 164 0000E1A2 31 36 jeql L407
170: 165 0000E1A4 1d effffffe82 01 cmpl _cycle,$1
171: 166 0000E1AB 21 2d jneq L407
172: 167 0000E1AD # if( (!evt_inst) && /* print a line feed if */
173: 168 0000E1AD # (op_code == SUBD_OP_CODE) ) /* the 1st line is full */
174: 169 0000E1AD 5d effffffe79 tstl _evt_inst
175: 170 0000E1B3 21 18 jneq L408
176: 171 0000E1B5 1d effffffe71 8900d7 cmpl _op_code,$215
177: 172 0000E1BE 21 0d jneq L408
178: 173 0000E1C0 # writes("\n ");
179: 174 0000E1C0 .data 1
180: 175 0000025e * L409:
181: 176 0000025e * 0A20202020202020202020202 .ascii "\12 \0"
182: 0202020202020202020202000
183: 177 00000277 * .text
184: 178 0000E1C0 dd 8f0000025e pushl $L409
185: 179 0000E1C6 fe 08 effffffe5f callf $8,_writes
186: 180 0000E1CD # writes( op_name ); /* print the instruction's name */
187: 181 0000E1CD L408:
188: 182 0000E1CD dd effffffe59 pushl _op_name
189: 183 0000E1D3 fe 08 effffffe52 callf $8,_writes
190: 184 0000E1DA # }
191: 185 0000E1DA # test_inst();
192: 186 0000E1DA L407:
193: 187 0000E1DA fe 04 effffffe4b callf $4,_test_inst
194: 188 0000E1E1 # }
195: 189 0000E1E1 40 ret#2
196: 190 0000E1E2 .set L401,0x0
197: 191 0000E1E2 L403:
198: 192 0000E1E2 13 ff18 jbr L404
199: 193 0000E1E5 .data
200: 194 00000218 * .text
201: 195 0000E1E5 00 .align 1
202: 196 0000E1E6 .globl _get_resop_index
203: 197 0000E1E6 _get_resop_index:
204: 198 0000E1E6 0000 .word L411
205: 199 0000E1E8 #
206: 200 0000E1E8 #
207: 201 0000E1E8 #
208: 202 0000E1E8 # /*
209: 203 0000E1E8 # ***************************************************************************
210: 204 0000E1E8 # *
211: 205 0000E1E8 # * GET THE INSTRUCTION TABLE INDEX FOR AN OP-CODE
212: 206 0000E1E8 # *
213: 207 0000E1E8 # * Given the op_code of an instruction, return the instruction's index in
214: 208 0000E1E8 # * the reserved operand instruction table. Return a negative number if the
215: 209 0000E1E8 # * op-code isn't in the table.
216: 210 0000E1E8 # *
217: 211 0000E1E8 # * LOGF won't give reserved operand events with the "no-fpp" WCS firmware
218: 212 0000E1E8 # * so return a negative number if it is the test instruction.
219: 213 0000E1E8 # *
220: 214 0000E1E8 # **************************************************************************
221: 215 0000E1E8 # */
222: 216 0000E1E8 # get_resop_index( op_code )
223: 217 0000E1E8 # {
224: 218 0000E1E8 11 52 jbr L413
225: 219 0000E1EA L414:
226: 220 0000E1EA # int x;
227: 221 0000E1EA # x = 0;
228: 222 0000E1EA 4d adc8 clrl -56(fp)
229: 223 0000E1ED # while( (resop_tbl[x].inst_code != op_code) && (x < size_resop_tbl) )
230: 224 0000E1ED L415:
231: 225 0000E1ED 5c 18 adc8 50 mull3 $24,-56(fp),r0
232: 226 0000E1F2 1d e000000000 ad04 cmpl _resop_tbl(r0),4(fp)
233: 227 0000E1FA 31 0f jeql L416
234: 228 0000E1FC 1d adc8 effffffe28 cmpl -56(fp),_size_resop_tbl
235: 229 0000E204 81 05 jgeq L416
236: 230 0000E206 # x++;
237: 231 0000E206 6d adc8 incl -56(fp)
238: 232 0000E209 11 e2 jbr L415
239: 233 0000E20B L416:
240: 234 0000E20B # if( x == size_resop_tbl )
241: 235 0000E20B 1d adc8 effffffe19 cmpl -56(fp),_size_resop_tbl
242: 236 0000E213 21 04 jneq L417
243: 237 0000E215 # x = -1;
244: 238 0000E215 ec 01 adc8 mnegl $1,-56(fp)
245: 239 0000E219 # if( (no_fpp_wcs) && (resop_tbl[inst_index].inst_code == LOGF_OP_CODE) )
246: 240 0000E219 L417:
247: 241 0000E219 5d effffffe0d tstl _no_fpp_wcs
248: 242 0000E21F 31 15 jeql L418
249: 243 0000E221 5c 18 effffffe04 50 mull3 $24,_inst_index,r0
250: 244 0000E229 1d e000000000 35 cmpl _resop_tbl(r0),$53
251: 245 0000E230 21 04 jneq L418
252: 246 0000E232 # x = -1; /* don't test LOGF w/ no-fpp WCS */
253: 247 0000E232 ec 01 adc8 mnegl $1,-56(fp)
254: 248 0000E236 # return( x );
255: 249 0000E236 L418:
256: 250 0000E236 0d adc8 50 movl -56(fp),r0
257: 251 0000E23A 40 ret#1
258: 252 0000E23B # }
259: 253 0000E23B 40 ret#1
260: 254 0000E23C .set L411,0x0
261: 255 0000E23C L413:
262: 256 0000E23C 3c 38 5d 5e subl3 $56,fp,sp
263: 257 0000E240 11 a8 jbr L414
264: 258 0000E242 .data
265: 259 00000218 * #
266: 260 00000218 * #
267: 260 00000218 * #
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