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Up to [Power 6/32 Unix Tahoe 4.2BSD] / cci / d / fpevent|
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Power 6/32 Unix version 1.21
1 00000000
2 00000000 /* privileged registers constants (addresses) */
3 00000000
4 00000000
5 00000000
6 00000000 .set SBR,0 /*system base register */
7 00000000 .set SLR,1 /*system length reg */
8 00000000 .set P0BR,2 /*p0 base reg */
9 00000000 .set P0LR,3 /*p0 length reg */
10 00000000 .set P1BR,4 /*p1 base reg */
11 00000000 .set P1LR,5 /*p1 length reg */
12 00000000 .set P2BR,6 /*p2 base reg */
13 00000000 .set P2LR,7 /*p2 length reg */
14 00000000 .set IPL,8 /*int priority level reg */
15 00000000 .set MME,9 /*memory mgmt enable reg */
16 00000000 .set TBIA,10 /*trans buf invalidate all */
17 00000000 /*entries */
18 00000000 .set TBIS,11 /*trans buf invalidate single */
19 00000000 /*entry */
20 00000000 .set DCK,12 /*data cache key */
21 00000000 .set CCK,13 /*code cache key */
22 00000000 .set PCBB,14 /*process control block base */
23 00000000 .set ISP,15 /*interrupt stack pointer */
24 00000000 .set SIRR,16 /*software int request reg */
25 00000000 .set SISR,17 /*software int summary reg */
26 00000000 .set SCBB,18 /*system control block base reg */
27 00000000 .set KSP,19 /*kernel stack pointer reg */
28 00000000 .set USP,20 /*user stack pointer */
29 00000000 .set DCB,21 /*CPU2 DCB */
30 00000000 .set PACC,23 /*purge (invalidate) all pages */
31 00000000 /*of process in code cache */
32 00000000 .set P1DC,24 /*purge one page of data cache */
33 00000000 .set PADC,25 /*purge all the pages of */
34 00000000 /*process in data cache */
35 00000000 .set HISR,26 /* Hardware interrupt summary reg */
36 00000000 .set DCR,27 /* Diagnostic control register */
37 00000000 .set PDCS,28 /* Purge 1 data cache slot */
38 00000000
39 00000000 #
40 00000000 #TAHOE program status longword
41 00000000 #
42 00000000
43 00000000 .set PSL_C,0x00000001 /* carry bit */
44 00000000 .set PSL_V,0x00000002 /* overflow bit */
45 00000000 .set PSL_Z,0x00000004 /* zero bit */
46 00000000 .set Z,0x00000004
47 00000000 .set PSL_N,0x00000008 /* negative bit */
48 00000000 .set PSL_T,0x00000010 /* trace enable bit */
49 00000000 .set PSL_I,0x00000020 /* integer overflow enable bit */
50 00000000 .set PSL_EN_OVFL,0x20 /* integer overflow enable bit */
51 00000000 .set PSL_EN_UNDFL,0x40 /* floating underflow enable */
52 00000000 .set PSL_DBL,0x80 /* dbl precision Accumulator bit */
53 00000000 .set PSL_IPL,0x001f0000 /* interrupt priority level */
54 00000000 .set PSL_MOD,0x01000000 /* mode = 1 means user */
55 00000000 .set PSL_IS,0x04000000 /* interrupt stack */
56 00000000 .set PSL_TP,0x40000000 /* trace pending */
57 00000000
58 00000000 #
59 00000000 # TAHOE page table entry
60 00000000 #/
61 00000000 .set PG_V,0x8000000
62 00000000 .set PG_PROT,0x78000000
63 00000000 .set PG_M,0x04000000
64 00000000 .set PG_USED,0x02000000
65 00000000 .set PG_NC,0x01000000
66 00000000 .set PG_PFNUM,0x003fffff
67 00000000
68 00000000 .set PG_NOACC,0
69 00000000 .set PG_KR,0x40000000
70 00000000 .set PG_KW,0x60000000
71 00000000 .set PG_URKR,0x50000000
72 00000000 .set PG_URKW,0x70000000
73 00000000 .set PG_UW,0x78000000
74 00000000
75 00000000 #* PCB offsets & diagnostic extension to pcb */
76 00000000 #* PCB is at pcb0 */
77 00000000
78 00000000
79 00000000 .set PCB_SIZE, 24
80 00000000 .set PCB_KSP, 0
81 00000000 .set PCB_USP, 4
82 00000000 .set PCB_R0, 8
83 00000000 .set PCB_R1, 12
84 00000000 .set PCB_R2, 16
85 00000000 .set PCB_R3, 20
86 00000000 .set PCB_R4, 24
87 00000000 .set PCB_R5, 28
88 00000000 .set PCB_R6, 32
89 00000000 .set PCB_R7, 36
90 00000000 .set PCB_R8, 40
91 00000000 .set PCB_R9, 44
92 00000000 .set PCB_R10, 48
93 00000000 .set PCB_R11, 52
94 00000000 .set PCB_R12, 56
95 00000000 .set PCB_R13, 60
96 00000000 .set PCB_PC, 64
97 00000000 .set PCB_PSL, 68
98 00000000 .set PCB_P0BR, 72
99 00000000 .set PCB_P0LR, 76
100 00000000 .set PCB_P1BR, 80
101 00000000 .set PCB_P1LR, 84
102 00000000 .set PCB_P2BR, 88
103 00000000 .set PCB_P2LR, 92
104 00000000 .set PCB_ACCM, 96
105 00000000 .set PCB_ACCL, 100
106 00000000 #*
107 00000000 # Diagnostic pcb extension
108 00000000 #/
109 00000000 .set PCB_STAT, 104 /*process status,statistics,id,etc*/
110 00000000
111 00000000
112 00000000
113 00000000 #* fundamental constants */
114 00000000
115 00000000 #*
116 00000000 # fundamental constants of the implementation--
117 00000000 # cannot be changed easily.
118 00000000 #/
119 00000000
120 00000000 .set NBPG,1024
121 00000000 .set PGOFSET,(NBPG-1) /* byte offset into page */
122 00000000 .set PGSHIFT,10 /* LOG2(NBPG) */
123 00000000 .set HIGH,0x1f
124 00000000
125 00000000
126 00000000 #* SCB offsets */
127 00000000 #* SCB is at scb */
128 00000000
129 00000000 .set PFVEC,1*4 /*power fail */
130 00000000 .set PRVEC,2*4 /*power restore */
131 00000000 .set CLOCKVEC,7*4 /*hard clock vector */
132 00000000 .set CRVEC,0xa*4 /*console receive */
133 00000000 .set CXVEC,44 /*console transmit */
134 00000000 .set SIVEC1,0x1e*4 /*software int vec #1 */
135 00000000 /*for 2,3,..15, sub 4,8,.. 56 */
136 00000000 /*from SIVEC1 */
137 00000000 .set BEVEC,0x20*4 /*bus error */
138 00000000 .set SYSVEC,0x2b*4 /*system call (kcall) */
139 00000000 .set PINSTVEC,0x2c*4 /*privileged instruction fault */
140 00000000 .set PRIVSVEC,0x2c*4 /*privileged instruction fault */
141 00000000 .set ROVEC,0x2d*4 /*reserved operand fault */
142 00000000 .set RAVEC,0x2e*4 /*reserved addressing fault */
143 00000000 .set PROTVEC,0x2f*4 /*access control violation */
144 00000000 .set TRANS,0x30 /*translation fault vector */
145 00000000 .set TRANSVEC,0x30*4 /*translation fault vector */
146 00000000 .set KSPVEC,0x31*4 /*kernel stack not valid vector */
147 00000000 .set TRACEVEC,0x32*4 /*trace vector */
148 00000000 .set BPTVEC,0x33*4 /*break point fault */
149 00000000 .set ARITHVEC,0x34*4 /*arithmetic trap */
150 00000000 .set ALIGNVEC,0x35*4 /*alignment vector */
151 00000000 .set FPMVEC,0x37*4 /*fpp emulation vector */
152 00000000 .set IO14VEC,256 /*io vector, ipl #14 */
153 00000000 .set IO15VEC,320 /*io vector, ipl #15 */
154 00000000 .set IO16VEC,384 /*io vector, ipl #16 */
155 00000000 .set IO17VEC,448 /*io vector, ipl #17 */
156 00000000
157 00000000 #* SPT (system page table) offsets */
158 00000000 #* SPT is at Sysmap */
159 00000000
160 00000000 .set SCBPTE,8 /*system control block pte offset*/
161 00000000 .set BUFPTE,12 /*buffer pte offset */
162 00000000 .set ISPTE,16 /*interrupt stack page 0 */
163 00000000 .set IS1PTE,20 /*interrupt stack page 1 */
164 00000000 .set SPTPTE,20 /*system page table page 1 */
165 00000000 .set SPT1PTE,20 /*system page table page 2 */
166 00000000 .set IOMAPPTE,24 /*io map */
167 00000000 .set PCBPTE,28 /*process control blocks pte */
168 00000000 .set U0P0PTE,32 /*U0 p0pt pte */
169 00000000 .set U0P1PTE,36 /*U0 p1pt pte */
170 00000000 .set U0P2PTE,40 /*U0 p2pt pte */
171 00000000 .set U1P0PTE,44
172 00000000 .set U1P1PTE,48
173 00000000 .set U1P2PTE,52
174 00000000 .set U2P0PTE,56
175 00000000 .set U2P1PTE,60
176 00000000 .set U2P2PTE,64
177 00000000 .set U3P0PTE,68
178 00000000 .set U3P1PTE,72
179 00000000 .set U3P2PTE,76
180 00000000 .set U4P0PTE,80
181 00000000 .set U4P1PTE,84
182 00000000 .set U4P2PTE,88
183 00000000 .set U5P0PTE,92
184 00000000 .set U5P1PTE,96
185 00000000 .set U5P2PTE,100
186 00000000 .set U6P0PTE,104
187 00000000 .set U6P1PTE,108
188 00000000 .set U6P2PTE,112
189 00000000 .set U7P0PTE,116 /*U7 p0pt pte */
190 00000000 .set U7P1PTE,120 /*U7 p1pt pte */
191 00000000 .set U7P2PTE,124 /*U7 p2pt pte */
192 00000000 .set IOB0PTE,128 /*io buffer 0 pte */
193 00000000 .set IOB1PTE,132
194 00000000 .set IOB2PTE,136
195 00000000 .set IOB3PTE,140
196 00000000 .set IOB4PTE,144
197 00000000 .set IOB5PTE,148
198 00000000 .set IOB6PTE,152
199 00000000 .set IOB7PTE,156 /*io buffer 7 pte */
200 00000000
201 00000000
202 00000000 #* trap.h 4.6 81/03/03 */
203 00000000
204 00000000 #*
205 00000000 #* Trap type values
206 00000000 #/
207 00000000
208 00000000 .set RESADFLT,0 /* reserved addressing fault */
209 00000000 .set PRIVINFLT,1 /* privileged instruction fault */
210 00000000 .set RESOPFLT,2 /* reserved operand fault */
211 00000000 .set BPTFLT,3 /* bpt instruction fault */
212 00000000 .set ALIGNFLT,4 /* alignment fault */
213 00000000 .set SYSCALL,5 /* kcall instruction (syscall trap) */
214 00000000 .set ARITHTRAP,6 /* arithmetic trap */
215 00000000 .set PROTFLT,7 /* protection fault */
216 00000000 .set TRCTRAP,8 /* trace trap */
217 00000000 .set TRANSFLT,9 /* translation not valid fault */
218 00000000 .set DONE,255
219 00000000
220 00000000 #
221 00000000 # Event codes
222 00000000 #
223 00000000 .set RTCLOCK_CODE,7 /* real time clock event */
224 00000000 .set RESOP_CODE,0x2d /* reserved operand fault */
225 00000000 .set RESAD_CODE,0x2e /* reserved address fault */
226 00000000 .set ARITH_CODE,0x34 /* arithmetic fault */
227 00000000 .set FPM_CODE,0x37 /* fpp emulation trap */
228 00000000 .set INTEGER_OVERFLOW,1 /* code for arith. fault */
229 00000000
230 00000000 #
231 00000000 # Arithmetic Event types
232 00000000 #
233 00000000 .set INT_OVFL_CODE,1 /* integer overflow */
234 00000000 .set INT_0_DIV_CODE,2 /* integer divide by 0 */
235 00000000 .set FLT_0_DIV_CODE,3 /* floating divide by 0 */
236 00000000 .set FLT_OVFL_CODE,4 /* floating overflow */
237 00000000 .set FLT_UNDFL_CODE,5 /* floating underflow */
238 00000000
239 00000000 #
240 00000000 # Floating Point Instruction Op-Codes
241 00000000 #
242 00000000 .set LDF_OP_CODE,0x06 /* sgl load acc. instr */
243 00000000 .set LDD_OP_CODE,0x07 /* dbl load acc. instr */
244 00000000 .set LNF_OP_CODE,0x16 /* sgl load-neg acc. instr */
245 00000000 .set LND_OP_CODE,0x17 /* dbl load-neg acc. instr */
246 00000000 .set STF_OP_CODE,0x26 /* sgl store acc. instr */
247 00000000 .set STD_OP_CODE,0x27 /* dbl store acc. instr */
248 00000000 .set CMPF_OP_CODE,0x36 /* sgl compare instr */
249 00000000 .set CMPD_OP_CODE,0x37 /* dbl compare instr */
250 00000000 .set CMPF2_OP_CODE,0x46 /* sgl compare 2 instr */
251 00000000 .set CMPD2_OP_CODE,0x47 /* dbl compare 2 instr */
252 00000000 .set TSTF_OP_CODE,0x56 /* sgl test acc. instr */
253 00000000 .set TSTD_OP_CODE,0x57 /* dbl test acc. instr */
254 00000000 .set PUSHD_OP_CODE,0x67 /* dbl push acc. instr */
255 00000000 .set CVLF_OP_CODE,0x76 /* convert int to sgl instr */
256 00000000 .set CVLD_OP_CODE,0x77 /* convert int to dbl instr */
257 00000000 .set CVFL_OP_CODE,0x86 /* convert sgl to int instr */
258 00000000 .set CVDL_OP_CODE,0x87 /* convert dbl to int instr */
259 00000000 .set LDFD_OP_CODE,0x97 /* load sgl to dbl instr */
260 00000000 .set CVDF_OP_CODE,0xa6 /* convert dbl to sgl instr */
261 00000000 .set NEGF_OP_CODE,0xb6 /* negate sgl acc. instr */
262 00000000 .set NEGD_OP_CODE,0xb7 /* negate dbl acc. instr */
263 00000000 .set ADDF_OP_CODE,0xc6 /* sgl add instr */
264 00000000 .set ADDD_OP_CODE,0xc7 /* dbl add instr */
265 00000000 .set SUBF_OP_CODE,0xd6 /* sgl subtract instr */
266 00000000 .set SUBD_OP_CODE,0xd7 /* dbl subtract instr */
267 00000000 .set MULF_OP_CODE,0xe6 /* sgl multiply instr */
268 00000000 .set MULD_OP_CODE,0xe7 /* dbl multiply instr */
269 00000000 .set DIVF_OP_CODE,0xf6 /* sgl divide instr */
270 00000000 .set DIVD_OP_CODE,0xf7 /* dbl divide instr */
271 00000000 .set SINF_OP_CODE,0x05 /* sgl sine instr */
272 00000000 .set COSF_OP_CODE,0x15 /* sgl cosine instr */
273 00000000 .set ATANF_OP_CODE,0x25 /* sgl arc-tangent instr */
274 00000000 .set LOGF_OP_CODE,0x35 /* sgl natural log instr */
275 00000000 .set SQRTF_OP_CODE,0x45 /* sgl square root instr */
276 00000000 .set EXPF_OP_CODE,0x55 /* sgl "e to the x" instr */
277 00000000 .set MULL2_OP_CODE,0x4c /* integer multiply - 2 ops */
278 00000000 .set MULL3_OP_CODE,0x5c /* integer multiply - 3 ops */
279 00000000
280 00000000
281 00000000 #
282 00000000 # Addressing test constants - These must agree with "fpp_defs.h"
283 00000000 #
284 00000000 .set ADR_ABSOLUTE,1 /* absolute address */
285 00000000 .set ADR_LITERAL,2 /* literal -short immediate byte */
286 00000000 .set ADR_IM_B,3 /* immediate byte */
287 00000000 .set ADR_IM_W,4 /* immediate word */
288 00000000 .set ADR_IM_L,5 /* immediate long-word */
289 00000000 .set ADR_B_DSP,6 /* byte displ relative */
290 00000000 .set ADR_W_DSP,7 /* word displ relative */
291 00000000 .set ADR_L_DSP,8 /* long-word displ relative */
292 00000000 .set ADR_B_DSP_DEF,9 /* byte displ relative deferred */
293 00000000 .set ADR_W_DSP_DEF,10 /* word displ relative deferred */
294 00000000 .set ADR_L_DSP_DEF,11 /* L-word displ relative deferred */
295 00000000 .set ADR_REG,12 /* direct register */
296 00000000 .set ADR_REG_DEF,13 /* register deferred */
297 00000000 .set ADR_FP_DEF,14 /* FP deferred */
298 00000000 .set ADR_SP_DEF,15 /* SP deferred */
299 00000000 .set ADR_PUSH,16 /* auto-decrement SP */
300 00000000 .set ADR_POP,17 /* auto-increment SP */
301 00000000 .set ADR_POP_DEF,18 /* auto-increment SP deferred */
302 00000000 .set ADR_REG_B,19 /* register + byte displ */
303 00000000 .set ADR_REG_W,20 /* register + word displ */
304 00000000 .set ADR_REG_L,21 /* register + long-word displ */
305 00000000 .set ADR_REG_B_DEF,22 /* register + byte displ deferred */
306 00000000 .set ADR_REG_W_DEF,23 /* register + word displ deferred */
307 00000000 .set ADR_REG_L_DEF,24 /* register + L-word displ deferred */
308 00000000 .set ADR_I_FP_DEF,25 /* indexed (frame pointer deferred) */
309 00000000 .set ADR_I_L,26 /* indexed (longword displacement) */
310 00000000
311 00000000
312 00000000 #*************************************************************************
313 00000000 #
314 00000000 # Stuff for the Demand Paging , Events, & Addressing Tests
315 00000000 #
316 00000000 #************************************************************************/
317 00000000 .set SGL,1 /* sgl precision data */
318 00000000 .set DBL,2 /* dbl precision data */
319 00000000 .set ENABLE_EVENTS,0x60 /* enable ovfl & undfl events */
320 00000000 .set NONE,0 /* no operand flag */
321 00000000 .set LOAD,1 /* read-the-operand flag */
322 00000000 .set STORE,2 /* store-the-operand flag */
323 00000000
324 00000000 .set NO_EVT_HLT,1 /* halt code: did not Get event */
325 00000000 .set EVT_MSK_HLT,2 /* halt code: got masked event */
326 00000000 .set BAD_PSL_HLT,3 /* halt code: wrong PSL value */
327 00000000 .set PUSH_CNT_HLT,4 /* halt code: wrong # ops on stk */
328 00000000 .set PUSH_PSL_HLT,5 /* halt code: bad PSL on stack */
329 00000000 .set PUSH_PC_HLT,6 /* halt code: bad PC on stack */
330 00000000 .set BAD_REG_HLT,7 /* halt code: bad final register */
331 00000000 .set BAD_ACC_HLT,8 /* halt code: bad final Acc. */
332 00000000
333 00000000 #
334 00000000 # set DMP_PG_0 to the 1st empty page
335 00000000 #
336 00000000 .set DMP_PG_0,0x36000
337 00000000 .set DMP_PG_1,DMP_PG_0+0x400
338 00000000 .set DMP_PG_2,DMP_PG_1+0x400
339 00000000 .set DMP_PG_3,DMP_PG_2+0x400
340 00000000 .set DMP_PG_4,DMP_PG_3+0x400
341 00000000 .set DMP_PG_5,DMP_PG_4+0x400
342 00000000 .set DMP_PG_6,DMP_PG_5+0x400
343 00000000 .set DMP_PG_7,DMP_PG_6+0x400
344 00000000 .set DMP_PG_8,DMP_PG_7+0x400
345 00000000 .set DMP_PG_9,DMP_PG_8+0x400
346 00000000 .set DMP_PG_10,DMP_PG_9+0x400
347 00000000 .set DMP_PG_11,DMP_PG_10+0x400
348 00000000 .set DMP_PG_12,DMP_PG_11+0x400
349 00000000 .set DMP_PG_13,DMP_PG_12+0x400
350 00000000
351 00000000 #
352 00000000 # test code space for the address / demand page tests
353 00000000 #
354 00000000 .set START_OF_CODE,DMP_PG_1-20 /* 1st addr of test-code space */
355 00000000 .set CODE_BUF_SIZE,40 /* # bytes in test-code space */
356 00000000 .set END_OF_CODE,START_OF_CODE+CODE_BUF_SIZE
357 00000000
358 00000000 #
359 00000000 # data locations used by the event and demand page tests
360 00000000 #
361 00000000 .set _dmp_byte_op_1,DMP_PG_1+0x30 /* 'byte offset' data */
362 00000000 .set _dmp_byte_op_2,DMP_PG_1+0x50 /* 'byte offset' data */
363 00000000 .set _dmp_byte_op_3,DMP_PG_1+0x70 /* 'byte offset' data */
364 00000000 .set _dmp_op_1,DMP_PG_3-4 /* 1st data word */
365 00000000 .set _dmp_op_1_ptr,DMP_PG_4+0x30 /* ptr to 1st data wd */
366 00000000 .set _dmp_op_2_ptr,DMP_PG_5+0x30 /* ptr to 2nd data wd */
367 00000000 .set _dmp_op_2,DMP_PG_7-4 /* 2nd data word */
368 00000000 .set _dmp_op_3,DMP_PG_8 /* 3rd data word */
369 00000000 .set _dmp_op_3_ptr,DMP_PG_9+0x30 /* ptr to 3rd data wd */
370 00000000 .set _dmp_op_4,DMP_PG_10 /* 4th data (for pipes) */
371 00000000 .set _dmp_op_5,DMP_PG_11 /* 5th data (for pipes) */
372 00000000 .set _sp_minus,DMP_PG_13-4 /* SP for POPs */
373 00000000 .set _sp_page,DMP_PG_13 /* SP page boundary */
374 00000000 .set _sp_plus,DMP_PG_13+4 /* SP for PUSHs */
375 00000000
376 00000000
377 00000000 # ************************************************************************
378 00000000 # *
379 00000000 # * "RUN THE TEST CODE" ROUTINE
380 00000000 # *
381 00000000 # * The general template of the test code will be:
382 00000000 # *
383 00000000 # * <op-code> [<addr-mode>] [<op.#1>] [<addr-mode>] [<op.#2>]
384 00000000 # *
385 00000000 # * any unused bytes will be padded with NOPs. After the NOPs there will
386 00000000 # * be a jump back to this routine. The jump will only be taken if there
387 00000000 # * is no event generated by the test instruction.
388 00000000 # *
389 00000000 # * The event handler will verify the event type and return to this code
390 00000000 # * through the "event_return" pointer.
391 00000000 # * After the event, this routine will decide if the event should have
392 00000000 # * been masked or not. If it wasn't masked then this code will call the
393 00000000 # * routine to check the event results (reg's, PSL, etc.). The checking
394 00000000 # * routine is called from here because after the event, this was the
395 00000000 # * last routine with the right frame pointer.
396 00000000 # *
397 00000000 # * 30-May-85 added: ACC = 0 for pipelined test #2
398 00000000 # * 10-Jul-85 pulled instruction cache hit parts
399 00000000 # ************************************************************************
400 00000000 .set NOP_JMP,0x1010719f /* jump to an absolute address */
401 00000000 .text
402 00000000 .align 1
403 00000000 .globl _run_code
404 00000000 _run_code:
405 00014FBC 0000 .word 0
406 00014FBE ed 6d ef00000327 moval (r13),_rc_code_fp /* save the frame pointer */
407 00014FC5 ed 6e ef0000031c moval (r14),_rc_code_sp /* save the stack pointer */
408 00014FCC e9 ef00000293 ef00000319 movab _loop_n_leave,return /* exit for unexpected event */
409 00014FD7 fe 04 ef000002a4 callf $4,_fill_code_buff /* stuff the code buffer */
410 00014FDE ed ef000001dd efffffffd3 moval _evt_return,_event_return /* set up event return addr */
411 00014FE9
412 00014FE9 #########################################################################
413 00014FE9 # Invalidate the instruction cache (error loop starts here)
414 00014FE9 #########################################################################
415 00014FE9 _shift_loop:
416 00014FE9 6d efffffffcd incl _Codek /* Bump code cache key */
417 00014FEF 1d efffffffc7 8900ff cmpl _Codek,$255 /* Last key yet ? */
418 00014FF8 91 0b jlss 1f
419 00014FFA 0d 01 efffffffbb movl $1,_Codek /* Reset Code key to 1 */
420 00015001 ad 01 17 mtpr $1,$PACC /* Purge all code cache */
421 00015004 10 nop
422 00015005 1:
423 00015005 ad efffffffb1 0d mtpr _Codek,$CCK /* Set new key */
424 0001500C
425 0001500C #########################################################################
426 0001500C # If the addressing mode is POP or deferred POP, push the data needed
427 0001500C #########################################################################
428 0001500C 1d 89008e efffffffa7 cmpl $0x8e,_addr_code /* POP SP addressing? */
429 00015015 31 0b beql 1f
430 00015017 1d 89009e efffffff9c cmpl $0x9e,_addr_code /* POP SP deferred addr.? */
431 00015020 21 15 bneq 2f
432 00015022 1:
433 00015022 1d 01 efffffff93 cmpl $1,_no_ops /* push 1 or 2 operands? */
434 00015029 31 06 beql 1f
435 0001502B dd efffffff8b pushl _sgl_value_10 /* push the 2nd data operand */
436 00015031 1:
437 00015031 dd efffffff85 pushl _sgl_value_9 /* push the data to be popped */
438 00015037
439 00015037 2:
440 00015037 #########################################################################
441 00015037 # LOAD THE ACCUMULATOR AND THE REGISTERS
442 00015037 # If this is pipelined test #2, load a zero into the accumulator
443 00015037 #########################################################################
444 00015037 ed 6e efffffff7e moval (sp),_pre_event_sp /* save the stack pointer */
445 0001503E 1d 02 efffffff77 cmpl $2,_pipe_test
446 00015045 21 06 bneq 1f
447 00015047 4d 50 clrl r0 /* load the accumulator with */
448 00015049 4d 51 clrl r1 /* zero for pipe test #2 */
449 0001504B 11 0e brb 2f
450 0001504D 0d efffffff69 50 1: movl _dbl_ld_acc,r0 /* if not pipe test #2, load */
451 00015054 0d efffffff66 51 movl _dbl_ld_acc+4,r1 /* the ACC with the data */
452 0001505B 2:
453 0001505B 1d efffffff5b 02 cmpl _acc_ld_size,$DBL /* load DBL or SGL ACC? */
454 00015062 31 04 beql 1f
455 00015064 06 50 ldf r0 /* load the sgl accumulator */
456 00015066 11 02 brb 2f
457 00015068 07 50 1: ldd r0 /* load the dbl accumulator */
458 0001506A 2:
459 0001506A ab 893fff efffffff49 loadr $0x3fff,_load_regs /* load regs 0 - 13 (FP) */
460 00015073
461 00015073
462 00015073 #########################################################################
463 00015073 # ENABLE OR DISABLE THE EVENT, SET THE EVENT TYPE & EXECUTE THE TEST CODE
464 00015073 #########################################################################
465 00015073 8b 8860 bispsw $ENABLE_EVENTS /* enable ovfl & undfl events */
466 00015076 9b efffffff40 bicpsw _disable_mask /* disable events as needed */
467 0001507C 0d efffffff3a efffffff35 movl _test_event,_exp_event /* set the event expected flag */
468 00015087 cd efffffff2f movpsl _init_psl /* save PSL for error checking */
469 0001508D 71 ffffffff29 jmp *_code_addr /* execute the test code */
470 00015093 00 halt
471 00015094
472 00015094
473 00015094 ##########################################################################
474 00015094 # The only way here (knock on wood) is if we executed the test instruction
475 00015094 # without getting any events. If an event was expected, it is an error to
476 00015094 # come here.
477 00015094 # - Save the PSL and check if the event was disabled.
478 00015094 ##########################################################################
479 00015094 .globl _rc_code_return
480 00015094 _rc_code_return:
481 00015094 cd efffffff22 movpsl _psl_val /* save the final PSL */
482 0001509A 4d efffffff1c clrl _exp_event /* no more events expected */
483 000150A0 3d 890080 efffffff13 bitl $PSL_DBL,_psl_val /* check for DBL Acc. */
484 000150A9 21 0e bneq 1f
485 000150AB 26 efffffff0b stf _dbl_st_acc /* save the accumulator */
486 000150B1 4d efffffff09 clrl _dbl_st_acc+4
487 000150B7 11 06 brb 2f
488 000150B9 27 effffffefd 1: std _dbl_st_acc /* save the accumulator */
489 000150BF 2:
490 000150BF 5d effffffef7 tstl _evt_disabled /* Was the event disabled? */
491 000150C5 21 06 bneq 1f
492 000150C7 71 ef0000008d jmp _rc_no_event /* No -event not disabled */
493 000150CD 1:
494 000150CD
495 000150CD
496 000150CD ##########################################################################
497 000150CD # The event was disabled so we're OK so far. Check the PSL flags
498 000150CD ##########################################################################
499 000150CD fe 04 effffffee8 callf $4,_bad_final_psl /* check the final PSL */
500 000150D4 5d 50 tstl r0 /* was the PSL OK? */
501 000150D6 21 06 bneq 1f /* -NO. handle the error */
502 000150D8 71 ef00000187 jmp _loop_n_leave /* -YES. exit (or loop) */
503 000150DE 1:
504 000150DE 5d effffffed8 tstl _prt_error /* print an error message? */
505 000150E4 31 4e beql 1f
506 000150E6 dd effffffed0 pushl _bad_psl_msg /* "bad final PSL" message */
507 000150EC fe 08 effffffec9 callf $8,_prt_evt_er_msg /* print the error message */
508 000150F3 dd 8f00000338 pushl $_rc_f_psl_msg /* "final PSL = " */
509 000150F9 fe 08 effffffebc callf $8,_writes
510 00015100 dd effffffeb6 pushl _psl_val
511 00015106 fe 08 effffffeaf callf $8,_write32h
512 0001510D dd 8f00000345 pushl $_rc_e_psl_msg /* "expected PSL = " */
513 00015113 fe 08 effffffea2 callf $8,_writes
514 0001511A dd effffffe9c pushl _exp_psl
515 00015120 fe 08 effffffe95 callf $8,_write32h
516 00015127 dd 8f00000359 pushl $_rc_newline /* print a line feed */
517 0001512D fe 08 effffffe88 callf $8,_writec
518 00015134 1:
519 00015134 5d effffffe82 tstl _halt_flg /* halt on error? */
520 0001513A 31 09 beql 1f
521 0001513C dd 03 pushl $BAD_PSL_HLT
522 0001513E fe 08 effffffe77 callf $8,_event_halt /* set up regs and halt */
523 00015145 1:
524 00015145 5d effffffe71 tstl _loop_on_err /* loop on the error? */
525 0001514B 31 07 beql 1f
526 0001514D 0d 01 effffffe68 movl $1,_force_loop /* set the Force Loop flag */
527 00015154 1:
528 00015154 71 ef0000010b jmp _loop_n_leave /* exit or loop */
529 0001515A
530 0001515A
531 0001515A ##########################################################################
532 0001515A # BUMMER!! WE SHOULD HAVE GOTTEN AN EVENT
533 0001515A ##########################################################################
534 0001515A _rc_no_event:
535 0001515A bb 893fff effffffe59 storer $0x3fff,_store_regs /* store regs 0 - 13 */
536 00015163 0d ef00000183 5d movl _rc_code_fp,fp /* re-load the frame pointer */
537 0001516A 0d ef00000178 5e movl _rc_code_sp,sp /* re-load the stack pointer */
538 00015171 5d effffffe45 tstl _force_loop /* Is "force_loop" set? */
539 00015177 31 06 beql 1f
540 00015179 71 effffffe6a jmp _shift_loop /* Yes - loop on the error */
541 0001517F 1:
542 0001517F 6d effffffe37 incl _errcnt; /* bump the error count */
543 00015185 5d effffffe31 tstl _prt_error /* print an error message? */
544 0001518B 31 0d beql 1f
545 0001518D dd effffffe29 pushl _no_evt_msg /* "did not get event" msg */
546 00015193 fe 08 effffffe22 callf $8,_prt_evt_er_msg /* print the error message */
547 0001519A 1:
548 0001519A 5d effffffe1c tstl _halt_flg /* halt on error? */
549 000151A0 31 09 beql 1f
550 000151A2 dd 01 pushl $NO_EVT_HLT
551 000151A4 fe 08 effffffe11 callf $8,_event_halt /* halt with code of 1 */
552 000151AB 1:
553 000151AB 5d effffffe0b tstl _loop_on_err /* loop on the error? */
554 000151B1 31 07 beql 1f
555 000151B3 0d 01 effffffe02 movl $1,_force_loop /* set the force_loop flag */
556 000151BA 1:
557 000151BA 71 ef000000a5 jmp _loop_n_leave /* loop on the error or exit */
558 000151C0 00 halt /* we should never get here */
559 000151C1
560 000151C1
561 000151C1 ##########################################################################
562 000151C1 # The only way here (knock on wood) is if we got the correct event while
563 000151C1 # executing the instruction.
564 000151C1 ##########################################################################
565 000151C1 .globl _evt_return
566 000151C1 _evt_return:
567 000151C1 4d effffffdf5 clrl _exp_event /* no more events expected */
568 000151C7 0d effffffdef effffffdea movl _post_evt_acc,_dbl_st_acc /* save the accumulator */
569 000151D2 0d effffffde8 effffffde3 movl _post_evt_acc+4,_dbl_st_acc+4
570 000151DD 0d ef00000109 5d movl _rc_code_fp,fp /* re-load the frame pointer */
571 000151E4 0d ef000000fe 5e movl _rc_code_sp,sp /* re-load the stack pointer */
572 000151EB 5d effffffdcb tstl _force_loop /* Is "force_loop" set? */
573 000151F1 31 06 beql 1f
574 000151F3 71 effffffdf0 jmp _shift_loop /* then loop on the error */
575 000151F9
576 000151F9 1:
577 000151F9 ##########################################################################
578 000151F9 # NOW CHECK TO SEE IF THE EVENT WAS DISABLED WHEN IT OCCURRED
579 000151F9 ##########################################################################
580 000151F9 5d effffffdbd tstl _evt_disabled /* Was the interrupt disabled? */
581 000151FF 21 0d bneq 1f
582 00015201 fe 04 effffffdb4 callf $4,_chk_event /* No -verify the stack, etc. */
583 00015208 71 ef00000057 jmp _loop_n_leave /* Exit ( or loop if error ) */
584 0001520E
585 0001520E 1:
586 0001520E ##########################################################################
587 0001520E # BUMMER!! WE SHOULDN'T HAVE GOTTEN AN EVENT
588 0001520E ##########################################################################
589 0001520E 0d ef000000d8 5d movl _rc_code_fp,fp /* re-load the frame pointer */
590 00015215 0d ef000000cd 5e movl _rc_code_sp,sp /* re-load the stack pointer */
591 0001521C 5d effffffd9a tstl _force_loop /* Is "force_loop" set? */
592 00015222 31 06 beql 1f
593 00015224 71 effffffdbf jmp _shift_loop /* then loop on the error */
594 0001522A 1:
595 0001522A 6d effffffd8c incl _errcnt; /* bump the error count */
596 00015230 5d effffffd86 tstl _prt_error /* print an error message? */
597 00015236 31 0d beql 1f
598 00015238 dd effffffd7e pushl _disbl_evt_msg /* "event while disabled" msg */
599 0001523E fe 08 effffffd77 callf $8,_prt_evt_er_msg /* print the error message */
600 00015245 1:
601 00015245 5d effffffd71 tstl _halt_flg /* halt on error? */
602 0001524B 31 09 beql 1f
603 0001524D dd 02 pushl $EVT_MSK_HLT
604 0001524F fe 08 effffffd66 callf $8,_event_halt /* halt with code of 2 */
605 00015256 1:
606 00015256 5d effffffd60 tstl _loop_on_err /* loop on the error? */
607 0001525C 31 07 beql 1f
608 0001525E 0d 01 effffffd57 movl $1,_force_loop /* set the force_loop flag */
609 00015265
610 00015265 1:
611 00015265 #########################################################################
612 00015265 # THIS IS THE EXIT FROM THIS ROUTINE
613 00015265 # LOOP IF THE FORCE LOOP FLAG IS SET, OTHERWISE EXIT
614 00015265 #########################################################################
615 00015265 _loop_n_leave:
616 00015265 0d ef00000081 5d movl _rc_code_fp,fp /* re-load the frame pointer */
617 0001526C 0d ef00000076 5e movl _rc_code_sp,sp /* re-load the stack pointer */
618 00015273 5d effffffd43 tstl _force_loop /* Is "force_loop" set? */
619 00015279 31 06 beql 1f
620 0001527B 71 effffffd68 jmp _shift_loop /* then loop on the error */
621 00015281 1:
622 00015281 40 ret /* return */
623 00015282
624 00015282
625 00015282
626 00015282
627 00015282
628 00015282
629 00015282 # *************************************************************************
630 00015282 # *
631 00015282 # * FILL IN THE CODE BUFFER ROUTINE
632 00015282 # *
633 00015282 # * Set up the instruction code sequence. After the instruction code,
634 00015282 # * put a jump back to "execute_code" and fill the rest of the code buffer
635 00015282 # * with NOPs.
636 00015282 # *
637 00015282 # *************************************************************************
638 00015282 .text
639 00015282 .align 1
640 00015282 .globl _fill_code_buff
641 00015282 _fill_code_buff:
642 00015282 0000 .word 0
643 00015284 0d 8f000363ec 50 movl $START_OF_CODE,r0
644 0001528B 0d 50 effffffd2a movl r0,_code_addr /* save the starting address */
645 00015292 4d 51 clrl r1
646 00015294 09 e100000000 60 1: movb _inst_buf(r1),(r0) /* move the code to the code buf */
647 0001529B 6d 50 incl r0
648 0001529D 2f 10 51 fff2 aoblss $16,r1,1b
649 000152A2 ########################################################################
650 000152A2 # After the instruction code, put a jump back to "_rc_code_return"
651 000152A2 ########################################################################
652 000152A2 0d 8f1010719f effffffd0f movl $NOP_JMP,_sgl_dummy1 /* "<nop><nop><jmp><abs addr>" */
653 000152AD 4d 51 clrl r1
654 000152AF 09 e100000000 60 1: movb _sgl_dummy1(r1),(r0) /* move the code to the code buf */
655 000152B6 6d 50 incl r0
656 000152B8 2f 04 51 fff2 aoblss $4,r1,1b
657 000152BD
658 000152BD ed effffffdd1 effffffcf4 moval _rc_code_return,_sgl_dummy1 /* jmp to 'ex_code_return' */
659 000152C8 4d 51 clrl r1
660 000152CA 09 e100000000 60 1: movb _sgl_dummy1(r1),(r0) /* move the code to the code buf */
661 000152D1 6d 50 incl r0
662 000152D3 2f 04 51 fff2 aoblss $4,r1,1b
663 000152D8
664 000152D8 ########################################################################
665 000152D8 # Fill the rest of the buffer with NOPs and return
666 000152D8 ########################################################################
667 000152D8 0d 10 51 movl $0x10,r1 /* 0x10 = NOP op-code */
668 000152DB 09 51 60 1: movb r1,(r0) /* put NOPs in the code space */
669 000152DE 3f 8f00036414 51 fff4 aobleq $END_OF_CODE,r1,1b
670 000152E7 40 ret /* return */
671 000152E8
672 000152E8
673 000152E8
674 000152E8 ########################################################################
675 000152E8 # Variables
676 000152E8 ########################################################################
677 000152E8 .align 2
678 000152E8 .globl _rc_code_sp
679 000152E8 _rc_code_sp: /* save stack pointer value here */
680 000152E8 00000000 .long 0
681 000152EC .globl _rc_code_fp
682 000152EC _rc_code_fp: /* save frame pointer value here */
683 000152EC 00000000 .long 0
684 000152F0
685 000152F0 .globl return /* emergency indirect return addr */
686 000152F0 return:
687 000152F0 000002a9 .long _loop_n_leave /* return to loop or leave */
688 000152F4
689 000152F4 ########################################################################
690 000152F4 # ERROR MESSAGES
691 000152F4 ########################################################################
692 000152F4 _rc_f_psl_msg:
693 000152F4 66696E616C2050534C203D200 .ascii "final PSL = \0"
0
694 00015301 _rc_e_psl_msg:
695 00015301 2C20202065787065637465642 .ascii ", expected PSL = \0"
050534C203D2000
696 00015315 _rc_newline:
697 00015315 200A00 .ascii " \n\0"
697 0002A2D1 200A00 .ascii " \n\0"
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