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Up to [Power 6/32 Unix Tahoe 4.2BSD] / cci / d / fpevent|
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1.1 root 1: 1 00000000
2: 2 00000000 /* privileged registers constants (addresses) */
3: 3 00000000
4: 4 00000000
5: 5 00000000
6: 6 00000000 .set SBR,0 /*system base register */
7: 7 00000000 .set SLR,1 /*system length reg */
8: 8 00000000 .set P0BR,2 /*p0 base reg */
9: 9 00000000 .set P0LR,3 /*p0 length reg */
10: 10 00000000 .set P1BR,4 /*p1 base reg */
11: 11 00000000 .set P1LR,5 /*p1 length reg */
12: 12 00000000 .set P2BR,6 /*p2 base reg */
13: 13 00000000 .set P2LR,7 /*p2 length reg */
14: 14 00000000 .set IPL,8 /*int priority level reg */
15: 15 00000000 .set MME,9 /*memory mgmt enable reg */
16: 16 00000000 .set TBIA,10 /*trans buf invalidate all */
17: 17 00000000 /*entries */
18: 18 00000000 .set TBIS,11 /*trans buf invalidate single */
19: 19 00000000 /*entry */
20: 20 00000000 .set DCK,12 /*data cache key */
21: 21 00000000 .set CCK,13 /*code cache key */
22: 22 00000000 .set PCBB,14 /*process control block base */
23: 23 00000000 .set ISP,15 /*interrupt stack pointer */
24: 24 00000000 .set SIRR,16 /*software int request reg */
25: 25 00000000 .set SISR,17 /*software int summary reg */
26: 26 00000000 .set SCBB,18 /*system control block base reg */
27: 27 00000000 .set KSP,19 /*kernel stack pointer reg */
28: 28 00000000 .set USP,20 /*user stack pointer */
29: 29 00000000 .set DCB,21 /*CPU2 DCB */
30: 30 00000000 .set PACC,23 /*purge (invalidate) all pages */
31: 31 00000000 /*of process in code cache */
32: 32 00000000 .set P1DC,24 /*purge one page of data cache */
33: 33 00000000 .set PADC,25 /*purge all the pages of */
34: 34 00000000 /*process in data cache */
35: 35 00000000 .set HISR,26 /* Hardware interrupt summary reg */
36: 36 00000000 .set DCR,27 /* Diagnostic control register */
37: 37 00000000 .set PDCS,28 /* Purge 1 data cache slot */
38: 38 00000000
39: 39 00000000 #
40: 40 00000000 #TAHOE program status longword
41: 41 00000000 #
42: 42 00000000
43: 43 00000000 .set PSL_C,0x00000001 /* carry bit */
44: 44 00000000 .set PSL_V,0x00000002 /* overflow bit */
45: 45 00000000 .set PSL_Z,0x00000004 /* zero bit */
46: 46 00000000 .set Z,0x00000004
47: 47 00000000 .set PSL_N,0x00000008 /* negative bit */
48: 48 00000000 .set PSL_T,0x00000010 /* trace enable bit */
49: 49 00000000 .set PSL_I,0x00000020 /* integer overflow enable bit */
50: 50 00000000 .set PSL_EN_OVFL,0x20 /* integer overflow enable bit */
51: 51 00000000 .set PSL_EN_UNDFL,0x40 /* floating underflow enable */
52: 52 00000000 .set PSL_DBL,0x80 /* dbl precision Accumulator bit */
53: 53 00000000 .set PSL_IPL,0x001f0000 /* interrupt priority level */
54: 54 00000000 .set PSL_MOD,0x01000000 /* mode = 1 means user */
55: 55 00000000 .set PSL_IS,0x04000000 /* interrupt stack */
56: 56 00000000 .set PSL_TP,0x40000000 /* trace pending */
57: 57 00000000
58: 58 00000000 #
59: 59 00000000 # TAHOE page table entry
60: 60 00000000 #/
61: 61 00000000 .set PG_V,0x8000000
62: 62 00000000 .set PG_PROT,0x78000000
63: 63 00000000 .set PG_M,0x04000000
64: 64 00000000 .set PG_USED,0x02000000
65: 65 00000000 .set PG_NC,0x01000000
66: 66 00000000 .set PG_PFNUM,0x003fffff
67: 67 00000000
68: 68 00000000 .set PG_NOACC,0
69: 69 00000000 .set PG_KR,0x40000000
70: 70 00000000 .set PG_KW,0x60000000
71: 71 00000000 .set PG_URKR,0x50000000
72: 72 00000000 .set PG_URKW,0x70000000
73: 73 00000000 .set PG_UW,0x78000000
74: 74 00000000
75: 75 00000000 #* PCB offsets & diagnostic extension to pcb */
76: 76 00000000 #* PCB is at pcb0 */
77: 77 00000000
78: 78 00000000
79: 79 00000000 .set PCB_SIZE, 24
80: 80 00000000 .set PCB_KSP, 0
81: 81 00000000 .set PCB_USP, 4
82: 82 00000000 .set PCB_R0, 8
83: 83 00000000 .set PCB_R1, 12
84: 84 00000000 .set PCB_R2, 16
85: 85 00000000 .set PCB_R3, 20
86: 86 00000000 .set PCB_R4, 24
87: 87 00000000 .set PCB_R5, 28
88: 88 00000000 .set PCB_R6, 32
89: 89 00000000 .set PCB_R7, 36
90: 90 00000000 .set PCB_R8, 40
91: 91 00000000 .set PCB_R9, 44
92: 92 00000000 .set PCB_R10, 48
93: 93 00000000 .set PCB_R11, 52
94: 94 00000000 .set PCB_R12, 56
95: 95 00000000 .set PCB_R13, 60
96: 96 00000000 .set PCB_PC, 64
97: 97 00000000 .set PCB_PSL, 68
98: 98 00000000 .set PCB_P0BR, 72
99: 99 00000000 .set PCB_P0LR, 76
100: 100 00000000 .set PCB_P1BR, 80
101: 101 00000000 .set PCB_P1LR, 84
102: 102 00000000 .set PCB_P2BR, 88
103: 103 00000000 .set PCB_P2LR, 92
104: 104 00000000 .set PCB_ACCM, 96
105: 105 00000000 .set PCB_ACCL, 100
106: 106 00000000 #*
107: 107 00000000 # Diagnostic pcb extension
108: 108 00000000 #/
109: 109 00000000 .set PCB_STAT, 104 /*process status,statistics,id,etc*/
110: 110 00000000
111: 111 00000000
112: 112 00000000
113: 113 00000000 #* fundamental constants */
114: 114 00000000
115: 115 00000000 #*
116: 116 00000000 # fundamental constants of the implementation--
117: 117 00000000 # cannot be changed easily.
118: 118 00000000 #/
119: 119 00000000
120: 120 00000000 .set NBPG,1024
121: 121 00000000 .set PGOFSET,(NBPG-1) /* byte offset into page */
122: 122 00000000 .set PGSHIFT,10 /* LOG2(NBPG) */
123: 123 00000000 .set HIGH,0x1f
124: 124 00000000
125: 125 00000000
126: 126 00000000 #* SCB offsets */
127: 127 00000000 #* SCB is at scb */
128: 128 00000000
129: 129 00000000 .set PFVEC,1*4 /*power fail */
130: 130 00000000 .set PRVEC,2*4 /*power restore */
131: 131 00000000 .set CLOCKVEC,7*4 /*hard clock vector */
132: 132 00000000 .set CRVEC,0xa*4 /*console receive */
133: 133 00000000 .set CXVEC,44 /*console transmit */
134: 134 00000000 .set SIVEC1,0x1e*4 /*software int vec #1 */
135: 135 00000000 /*for 2,3,..15, sub 4,8,.. 56 */
136: 136 00000000 /*from SIVEC1 */
137: 137 00000000 .set BEVEC,0x20*4 /*bus error */
138: 138 00000000 .set SYSVEC,0x2b*4 /*system call (kcall) */
139: 139 00000000 .set PINSTVEC,0x2c*4 /*privileged instruction fault */
140: 140 00000000 .set PRIVSVEC,0x2c*4 /*privileged instruction fault */
141: 141 00000000 .set ROVEC,0x2d*4 /*reserved operand fault */
142: 142 00000000 .set RAVEC,0x2e*4 /*reserved addressing fault */
143: 143 00000000 .set PROTVEC,0x2f*4 /*access control violation */
144: 144 00000000 .set TRANS,0x30 /*translation fault vector */
145: 145 00000000 .set TRANSVEC,0x30*4 /*translation fault vector */
146: 146 00000000 .set KSPVEC,0x31*4 /*kernel stack not valid vector */
147: 147 00000000 .set TRACEVEC,0x32*4 /*trace vector */
148: 148 00000000 .set BPTVEC,0x33*4 /*break point fault */
149: 149 00000000 .set ARITHVEC,0x34*4 /*arithmetic trap */
150: 150 00000000 .set ALIGNVEC,0x35*4 /*alignment vector */
151: 151 00000000 .set FPMVEC,0x37*4 /*fpp emulation vector */
152: 152 00000000 .set IO14VEC,256 /*io vector, ipl #14 */
153: 153 00000000 .set IO15VEC,320 /*io vector, ipl #15 */
154: 154 00000000 .set IO16VEC,384 /*io vector, ipl #16 */
155: 155 00000000 .set IO17VEC,448 /*io vector, ipl #17 */
156: 156 00000000
157: 157 00000000 #* SPT (system page table) offsets */
158: 158 00000000 #* SPT is at Sysmap */
159: 159 00000000
160: 160 00000000 .set SCBPTE,8 /*system control block pte offset*/
161: 161 00000000 .set BUFPTE,12 /*buffer pte offset */
162: 162 00000000 .set ISPTE,16 /*interrupt stack page 0 */
163: 163 00000000 .set IS1PTE,20 /*interrupt stack page 1 */
164: 164 00000000 .set SPTPTE,20 /*system page table page 1 */
165: 165 00000000 .set SPT1PTE,20 /*system page table page 2 */
166: 166 00000000 .set IOMAPPTE,24 /*io map */
167: 167 00000000 .set PCBPTE,28 /*process control blocks pte */
168: 168 00000000 .set U0P0PTE,32 /*U0 p0pt pte */
169: 169 00000000 .set U0P1PTE,36 /*U0 p1pt pte */
170: 170 00000000 .set U0P2PTE,40 /*U0 p2pt pte */
171: 171 00000000 .set U1P0PTE,44
172: 172 00000000 .set U1P1PTE,48
173: 173 00000000 .set U1P2PTE,52
174: 174 00000000 .set U2P0PTE,56
175: 175 00000000 .set U2P1PTE,60
176: 176 00000000 .set U2P2PTE,64
177: 177 00000000 .set U3P0PTE,68
178: 178 00000000 .set U3P1PTE,72
179: 179 00000000 .set U3P2PTE,76
180: 180 00000000 .set U4P0PTE,80
181: 181 00000000 .set U4P1PTE,84
182: 182 00000000 .set U4P2PTE,88
183: 183 00000000 .set U5P0PTE,92
184: 184 00000000 .set U5P1PTE,96
185: 185 00000000 .set U5P2PTE,100
186: 186 00000000 .set U6P0PTE,104
187: 187 00000000 .set U6P1PTE,108
188: 188 00000000 .set U6P2PTE,112
189: 189 00000000 .set U7P0PTE,116 /*U7 p0pt pte */
190: 190 00000000 .set U7P1PTE,120 /*U7 p1pt pte */
191: 191 00000000 .set U7P2PTE,124 /*U7 p2pt pte */
192: 192 00000000 .set IOB0PTE,128 /*io buffer 0 pte */
193: 193 00000000 .set IOB1PTE,132
194: 194 00000000 .set IOB2PTE,136
195: 195 00000000 .set IOB3PTE,140
196: 196 00000000 .set IOB4PTE,144
197: 197 00000000 .set IOB5PTE,148
198: 198 00000000 .set IOB6PTE,152
199: 199 00000000 .set IOB7PTE,156 /*io buffer 7 pte */
200: 200 00000000
201: 201 00000000
202: 202 00000000 #* trap.h 4.6 81/03/03 */
203: 203 00000000
204: 204 00000000 #*
205: 205 00000000 #* Trap type values
206: 206 00000000 #/
207: 207 00000000
208: 208 00000000 .set RESADFLT,0 /* reserved addressing fault */
209: 209 00000000 .set PRIVINFLT,1 /* privileged instruction fault */
210: 210 00000000 .set RESOPFLT,2 /* reserved operand fault */
211: 211 00000000 .set BPTFLT,3 /* bpt instruction fault */
212: 212 00000000 .set ALIGNFLT,4 /* alignment fault */
213: 213 00000000 .set SYSCALL,5 /* kcall instruction (syscall trap) */
214: 214 00000000 .set ARITHTRAP,6 /* arithmetic trap */
215: 215 00000000 .set PROTFLT,7 /* protection fault */
216: 216 00000000 .set TRCTRAP,8 /* trace trap */
217: 217 00000000 .set TRANSFLT,9 /* translation not valid fault */
218: 218 00000000 .set DONE,255
219: 219 00000000
220: 220 00000000 #
221: 221 00000000 # Event codes
222: 222 00000000 #
223: 223 00000000 .set RTCLOCK_CODE,7 /* real time clock event */
224: 224 00000000 .set RESOP_CODE,0x2d /* reserved operand fault */
225: 225 00000000 .set RESAD_CODE,0x2e /* reserved address fault */
226: 226 00000000 .set ARITH_CODE,0x34 /* arithmetic fault */
227: 227 00000000 .set FPM_CODE,0x37 /* fpp emulation trap */
228: 228 00000000 .set INTEGER_OVERFLOW,1 /* code for arith. fault */
229: 229 00000000
230: 230 00000000 #
231: 231 00000000 # Arithmetic Event types
232: 232 00000000 #
233: 233 00000000 .set INT_OVFL_CODE,1 /* integer overflow */
234: 234 00000000 .set INT_0_DIV_CODE,2 /* integer divide by 0 */
235: 235 00000000 .set FLT_0_DIV_CODE,3 /* floating divide by 0 */
236: 236 00000000 .set FLT_OVFL_CODE,4 /* floating overflow */
237: 237 00000000 .set FLT_UNDFL_CODE,5 /* floating underflow */
238: 238 00000000
239: 239 00000000 #
240: 240 00000000 # Floating Point Instruction Op-Codes
241: 241 00000000 #
242: 242 00000000 .set LDF_OP_CODE,0x06 /* sgl load acc. instr */
243: 243 00000000 .set LDD_OP_CODE,0x07 /* dbl load acc. instr */
244: 244 00000000 .set LNF_OP_CODE,0x16 /* sgl load-neg acc. instr */
245: 245 00000000 .set LND_OP_CODE,0x17 /* dbl load-neg acc. instr */
246: 246 00000000 .set STF_OP_CODE,0x26 /* sgl store acc. instr */
247: 247 00000000 .set STD_OP_CODE,0x27 /* dbl store acc. instr */
248: 248 00000000 .set CMPF_OP_CODE,0x36 /* sgl compare instr */
249: 249 00000000 .set CMPD_OP_CODE,0x37 /* dbl compare instr */
250: 250 00000000 .set CMPF2_OP_CODE,0x46 /* sgl compare 2 instr */
251: 251 00000000 .set CMPD2_OP_CODE,0x47 /* dbl compare 2 instr */
252: 252 00000000 .set TSTF_OP_CODE,0x56 /* sgl test acc. instr */
253: 253 00000000 .set TSTD_OP_CODE,0x57 /* dbl test acc. instr */
254: 254 00000000 .set PUSHD_OP_CODE,0x67 /* dbl push acc. instr */
255: 255 00000000 .set CVLF_OP_CODE,0x76 /* convert int to sgl instr */
256: 256 00000000 .set CVLD_OP_CODE,0x77 /* convert int to dbl instr */
257: 257 00000000 .set CVFL_OP_CODE,0x86 /* convert sgl to int instr */
258: 258 00000000 .set CVDL_OP_CODE,0x87 /* convert dbl to int instr */
259: 259 00000000 .set LDFD_OP_CODE,0x97 /* load sgl to dbl instr */
260: 260 00000000 .set CVDF_OP_CODE,0xa6 /* convert dbl to sgl instr */
261: 261 00000000 .set NEGF_OP_CODE,0xb6 /* negate sgl acc. instr */
262: 262 00000000 .set NEGD_OP_CODE,0xb7 /* negate dbl acc. instr */
263: 263 00000000 .set ADDF_OP_CODE,0xc6 /* sgl add instr */
264: 264 00000000 .set ADDD_OP_CODE,0xc7 /* dbl add instr */
265: 265 00000000 .set SUBF_OP_CODE,0xd6 /* sgl subtract instr */
266: 266 00000000 .set SUBD_OP_CODE,0xd7 /* dbl subtract instr */
267: 267 00000000 .set MULF_OP_CODE,0xe6 /* sgl multiply instr */
268: 268 00000000 .set MULD_OP_CODE,0xe7 /* dbl multiply instr */
269: 269 00000000 .set DIVF_OP_CODE,0xf6 /* sgl divide instr */
270: 270 00000000 .set DIVD_OP_CODE,0xf7 /* dbl divide instr */
271: 271 00000000 .set SINF_OP_CODE,0x05 /* sgl sine instr */
272: 272 00000000 .set COSF_OP_CODE,0x15 /* sgl cosine instr */
273: 273 00000000 .set ATANF_OP_CODE,0x25 /* sgl arc-tangent instr */
274: 274 00000000 .set LOGF_OP_CODE,0x35 /* sgl natural log instr */
275: 275 00000000 .set SQRTF_OP_CODE,0x45 /* sgl square root instr */
276: 276 00000000 .set EXPF_OP_CODE,0x55 /* sgl "e to the x" instr */
277: 277 00000000 .set MULL2_OP_CODE,0x4c /* integer multiply - 2 ops */
278: 278 00000000 .set MULL3_OP_CODE,0x5c /* integer multiply - 3 ops */
279: 279 00000000
280: 280 00000000
281: 281 00000000 #
282: 282 00000000 # Addressing test constants - These must agree with "fpp_defs.h"
283: 283 00000000 #
284: 284 00000000 .set ADR_ABSOLUTE,1 /* absolute address */
285: 285 00000000 .set ADR_LITERAL,2 /* literal -short immediate byte */
286: 286 00000000 .set ADR_IM_B,3 /* immediate byte */
287: 287 00000000 .set ADR_IM_W,4 /* immediate word */
288: 288 00000000 .set ADR_IM_L,5 /* immediate long-word */
289: 289 00000000 .set ADR_B_DSP,6 /* byte displ relative */
290: 290 00000000 .set ADR_W_DSP,7 /* word displ relative */
291: 291 00000000 .set ADR_L_DSP,8 /* long-word displ relative */
292: 292 00000000 .set ADR_B_DSP_DEF,9 /* byte displ relative deferred */
293: 293 00000000 .set ADR_W_DSP_DEF,10 /* word displ relative deferred */
294: 294 00000000 .set ADR_L_DSP_DEF,11 /* L-word displ relative deferred */
295: 295 00000000 .set ADR_REG,12 /* direct register */
296: 296 00000000 .set ADR_REG_DEF,13 /* register deferred */
297: 297 00000000 .set ADR_FP_DEF,14 /* FP deferred */
298: 298 00000000 .set ADR_SP_DEF,15 /* SP deferred */
299: 299 00000000 .set ADR_PUSH,16 /* auto-decrement SP */
300: 300 00000000 .set ADR_POP,17 /* auto-increment SP */
301: 301 00000000 .set ADR_POP_DEF,18 /* auto-increment SP deferred */
302: 302 00000000 .set ADR_REG_B,19 /* register + byte displ */
303: 303 00000000 .set ADR_REG_W,20 /* register + word displ */
304: 304 00000000 .set ADR_REG_L,21 /* register + long-word displ */
305: 305 00000000 .set ADR_REG_B_DEF,22 /* register + byte displ deferred */
306: 306 00000000 .set ADR_REG_W_DEF,23 /* register + word displ deferred */
307: 307 00000000 .set ADR_REG_L_DEF,24 /* register + L-word displ deferred */
308: 308 00000000 .set ADR_I_FP_DEF,25 /* indexed (frame pointer deferred) */
309: 309 00000000 .set ADR_I_L,26 /* indexed (longword displacement) */
310: 310 00000000
311: 311 00000000
312: 312 00000000 #*************************************************************************
313: 313 00000000 #
314: 314 00000000 # Stuff for the Demand Paging , Events, & Addressing Tests
315: 315 00000000 #
316: 316 00000000 #************************************************************************/
317: 317 00000000 .set SGL,1 /* sgl precision data */
318: 318 00000000 .set DBL,2 /* dbl precision data */
319: 319 00000000 .set ENABLE_EVENTS,0x60 /* enable ovfl & undfl events */
320: 320 00000000 .set NONE,0 /* no operand flag */
321: 321 00000000 .set LOAD,1 /* read-the-operand flag */
322: 322 00000000 .set STORE,2 /* store-the-operand flag */
323: 323 00000000
324: 324 00000000 .set NO_EVT_HLT,1 /* halt code: did not Get event */
325: 325 00000000 .set EVT_MSK_HLT,2 /* halt code: got masked event */
326: 326 00000000 .set BAD_PSL_HLT,3 /* halt code: wrong PSL value */
327: 327 00000000 .set PUSH_CNT_HLT,4 /* halt code: wrong # ops on stk */
328: 328 00000000 .set PUSH_PSL_HLT,5 /* halt code: bad PSL on stack */
329: 329 00000000 .set PUSH_PC_HLT,6 /* halt code: bad PC on stack */
330: 330 00000000 .set BAD_REG_HLT,7 /* halt code: bad final register */
331: 331 00000000 .set BAD_ACC_HLT,8 /* halt code: bad final Acc. */
332: 332 00000000
333: 333 00000000 #
334: 334 00000000 # set DMP_PG_0 to the 1st empty page
335: 335 00000000 #
336: 336 00000000 .set DMP_PG_0,0x36000
337: 337 00000000 .set DMP_PG_1,DMP_PG_0+0x400
338: 338 00000000 .set DMP_PG_2,DMP_PG_1+0x400
339: 339 00000000 .set DMP_PG_3,DMP_PG_2+0x400
340: 340 00000000 .set DMP_PG_4,DMP_PG_3+0x400
341: 341 00000000 .set DMP_PG_5,DMP_PG_4+0x400
342: 342 00000000 .set DMP_PG_6,DMP_PG_5+0x400
343: 343 00000000 .set DMP_PG_7,DMP_PG_6+0x400
344: 344 00000000 .set DMP_PG_8,DMP_PG_7+0x400
345: 345 00000000 .set DMP_PG_9,DMP_PG_8+0x400
346: 346 00000000 .set DMP_PG_10,DMP_PG_9+0x400
347: 347 00000000 .set DMP_PG_11,DMP_PG_10+0x400
348: 348 00000000 .set DMP_PG_12,DMP_PG_11+0x400
349: 349 00000000 .set DMP_PG_13,DMP_PG_12+0x400
350: 350 00000000
351: 351 00000000 #
352: 352 00000000 # test code space for the address / demand page tests
353: 353 00000000 #
354: 354 00000000 .set START_OF_CODE,DMP_PG_1-20 /* 1st addr of test-code space */
355: 355 00000000 .set CODE_BUF_SIZE,40 /* # bytes in test-code space */
356: 356 00000000 .set END_OF_CODE,START_OF_CODE+CODE_BUF_SIZE
357: 357 00000000
358: 358 00000000 #
359: 359 00000000 # data locations used by the event and demand page tests
360: 360 00000000 #
361: 361 00000000 .set _dmp_byte_op_1,DMP_PG_1+0x30 /* 'byte offset' data */
362: 362 00000000 .set _dmp_byte_op_2,DMP_PG_1+0x50 /* 'byte offset' data */
363: 363 00000000 .set _dmp_byte_op_3,DMP_PG_1+0x70 /* 'byte offset' data */
364: 364 00000000 .set _dmp_op_1,DMP_PG_3-4 /* 1st data word */
365: 365 00000000 .set _dmp_op_1_ptr,DMP_PG_4+0x30 /* ptr to 1st data wd */
366: 366 00000000 .set _dmp_op_2_ptr,DMP_PG_5+0x30 /* ptr to 2nd data wd */
367: 367 00000000 .set _dmp_op_2,DMP_PG_7-4 /* 2nd data word */
368: 368 00000000 .set _dmp_op_3,DMP_PG_8 /* 3rd data word */
369: 369 00000000 .set _dmp_op_3_ptr,DMP_PG_9+0x30 /* ptr to 3rd data wd */
370: 370 00000000 .set _dmp_op_4,DMP_PG_10 /* 4th data (for pipes) */
371: 371 00000000 .set _dmp_op_5,DMP_PG_11 /* 5th data (for pipes) */
372: 372 00000000 .set _sp_minus,DMP_PG_13-4 /* SP for POPs */
373: 373 00000000 .set _sp_page,DMP_PG_13 /* SP page boundary */
374: 374 00000000 .set _sp_plus,DMP_PG_13+4 /* SP for PUSHs */
375: 375 00000000
376: 376 00000000
377: 377 00000000
378: 378 00000000
379: 379 00000000 # ***************************************************************************
380: 380 00000000 # *
381: 381 00000000 # * Test an instruction that has no operands
382: 382 00000000 # *
383: 383 00000000 # * Only the 1 byte instruction and some NOPs will go into the code buffer.
384: 384 00000000 # *
385: 385 00000000 # * 30-May-85 : added pipelined tests
386: 386 00000000 # * 22-Jul-85 : don't run pipeline 2 test w/ emulated instructions
387: 387 00000000 # ***************************************************************************
388: 388 00000000 .text
389: 389 00000000 .align 1
390: 390 00000000 .globl _test_0_ops
391: 391 00000000 _test_0_ops:
392: 392 0000EFA8 0000 .word 0
393: 393 0000EFAA /*
394: 396 0000EFAA 1d 01 effffffff7 * Set the sizes for loading and for storing the accumulator
395: 397 0000EFB1 21 14 */
396: 398 0000EFB3 0d 01 efffffffee cmpl $SGL,_precision
397: 399 0000EFBA 0d 01 efffffffe7 bneq 1f
398: 400 0000EFC1 71 ef00000020 movl $SGL,_acc_ld_size /* set ACC. load size */
399: 401 0000EFC7 movl $SGL,_acc_st_size /* set ACC. store size */
400: 402 0000EFC7 0d 02 efffffffda jmp 2f
401: 403 0000EFCE 0d 02 efffffffd3 1:
402: 404 0000EFD5 1d efffffffcd 8900a6 movl $DBL,_acc_ld_size /* set ACC. load size */
403: 405 0000EFDE 21 07 movl $DBL,_acc_st_size /* set ACC. store size */
404: 406 0000EFE0 0d 01 efffffffc1 cmpl _op_code,$CVDF_OP_CODE /* "cvdf" instruction? */
405: 407 0000EFE7 bneq 2f
406: 408 0000EFE7 fe 04 ef00000018 movl $SGL,_acc_st_size /* store sgl acc. for cvdf */
407: 409 0000EFEE fe 04 ef0000008b 2:
408: 410 0000EFF5 1d efffffffad 37 callf $4,_test_0_no_pipe /* test w/o pipelineing */
409: 411 0000EFFC 31 07 callf $4,_test_0_pipe1 /* test pipeline test #1 */
410: 412 0000EFFE fe 04 ef00000133 cmpl _test_event,$FPM_CODE /* Is this the FPM test? */
411: 413 0000F005 40 beql 1f /* don't run pipe #2 w/ FPM */
412: 414 0000F006 callf $4,_test_0_pipe2 /* test pipeline test #2 */
413: 415 0000F006 1: ret /* return */
414: 416 0000F006
415: 417 0000F006
416: 418 0000F006
417: 419 0000F006
418: 420 0000F006 # ***************************************************************************
419: 421 0000F006 # *
420: 422 0000F006 # * TEST A NO OPERAND INSTRUCTION WITH NO FPP INSTRUCTION IN FRONT OF IT
421: 423 0000F006 # *
422: 424 0000F006 # ***************************************************************************
423: 425 0000F006 .text
424: 426 0000F006 .align 1
425: 427 0000F006 0000 .globl _test_0_no_pipe
426: 428 0000F008 4d efffffff9a _test_0_no_pipe:
427: 429 0000F00E fe 04 efffffff93 .word 0
428: 430 0000F015 dd 8f00000000 clrl _pipe_test /* reset the pipe-test flag */
429: 431 0000F01B fe 08 efffffff86 callf $4,_pack_inst /* pack the instr's code */
430: 432 0000F022 dd 8f00000000 pushl $_load_regs /* buffer for loading regs */
431: 433 0000F028 fe 08 efffffff79 callf $8,_fill_reg_buf /* fill the buffer */
432: 434 0000F02F pushl $_exp_regs /* expected reg values */
433: 437 0000F02F 4d efffffff73 callf $8,_fill_reg_buf /* fill the buffer */
434: 438 0000F035 /*
435: 439 0000F035 5c 04 efffffff6c 50 * test the instruction
436: 440 0000F03D 0d 40ffffffff64 */
437: efffffff5f
438: 441 0000F049 6d 50 clrl _index
439: 442 0000F04B 0d 40ffffffff56 3:
440: efffffff55
441: 443 0000F057 mull3 $4,_index,r0 /* get longword offset */
442: 444 0000F057 fe 04 efffffff4a movl *_data_ptr[r0],_dbl_ld_acc /* get load data's MSW */
443: 445 0000F05E 5d efffffff44 incl r0
444: 446 0000F064 21 f1 movl *_data_ptr[r0],_dbl_ld_acc+4 /* get load data's LSW */
445: 447 0000F066 1d efffffff3c efffffff37 2:
446: 448 0000F071 81 0c callf $4,_run_code /* execute the instruction */
447: 449 0000F073 6d efffffff2f tstl _force_loop
448: 450 0000F079 71 efffffffb6 bneq 2b /* loop on an error */
449: 451 0000F07F cmpl _index,_max_index /* last data pattern? */
450: 452 0000F07F 40 bgeq 1f
451: 453 0000F080 incl _index /* bump the index */
452: 454 0000F080 jmp 3b /* test next data pattern */
453: 455 0000F080 1:
454: 456 0000F080 ret /* return to test_code */
455: 457 0000F080
456: 458 0000F080
457: 459 0000F080
458: 460 0000F080
459: 461 0000F080 # ***************************************************************************
460: 462 0000F080 # *
461: 463 0000F080 # * TEST A NO OPERAND INSTRUCTION WITH A LOAD INSTRUCION IN FRONT OF IT
462: 464 0000F080 # *
463: 465 0000F080 # ***************************************************************************
464: 466 0000F080 0000 .text
465: 467 0000F082 0d 01 efffffff1f .align 1
466: 468 0000F089 0d 8862 efffffff17 .globl _test_0_pipe1
467: 469 0000F091 1d 02 efffffff10 _test_0_pipe1:
468: 470 0000F098 31 09 .word 0
469: 471 0000F09A 0d 06 efffffff07 movl $1,_pipe_test /* set the pipe_test flag */
470: 472 0000F0A1 11 07 movl $0x62,_addr_code_p1 /* set the addr mode */
471: 473 0000F0A3 0d 07 effffffefe cmpl $DBL,_acc_ld_size /* DBL or SGL ACC? */
472: 474 0000F0AA beql 1f
473: 475 0000F0AA fe 04 effffffef7 movl $LDF_OP_CODE,_pipe_inst1 /* pipe inst = load single */
474: 476 0000F0B1 dd 8f00000000 brb 2f
475: 477 0000F0B7 fe 08 effffffeea 1: movl $LDD_OP_CODE,_pipe_inst1 /* pipe inst = load double */
476: 478 0000F0BE dd 8f00000000 2:
477: 479 0000F0C4 fe 08 effffffedd callf $4,_pack_inst /* pack the instr's code */
478: 480 0000F0CB ed effffffed7 effffffeda pushl $_load_regs /* buffer for loading regs */
479: 481 0000F0D6 ed effffffecc effffffecf callf $8,_fill_reg_buf /* fill the buffer */
480: 482 0000F0E1 pushl $_exp_regs /* expected reg values */
481: 485 0000F0E1 4d effffffec1 callf $8,_fill_reg_buf /* fill the buffer */
482: 486 0000F0E7 moval _dbl_ld_acc,_load_regs+8 /* R2 points to the data */
483: 487 0000F0E7 5c 04 effffffeba 50 moval _dbl_ld_acc,_exp_regs+8 /* R2 points to the data */
484: 488 0000F0EF 0d 40fffffffeb2 /*
485: effffffead
486: 489 0000F0FB 6d 50 * test the instruction
487: 490 0000F0FD 0d 40fffffffea4 */
488: effffffea3
489: 491 0000F109 clrl _index
490: 492 0000F109 fe 04 effffffe98 3:
491: 493 0000F110 5d effffffe92 mull3 $4,_index,r0 /* get longword offset */
492: 494 0000F116 21 f1 movl *_data_ptr[r0],_dbl_ld_acc /* get load data's MSW */
493: 495 0000F118 1d effffffe8a effffffe85 incl r0
494: 496 0000F123 81 0c movl *_data_ptr[r0],_dbl_ld_acc+4 /* get load data's LSW */
495: 497 0000F125 6d effffffe7d 2:
496: 498 0000F12B 71 efffffffb6 callf $4,_run_code /* execute the instruction */
497: 499 0000F131 tstl _force_loop
498: 500 0000F131 4d effffffe71 bneq 2b /* loop on an error */
499: 501 0000F137 40 cmpl _index,_max_index /* last data pattern? */
500: 502 0000F138 bgeq 1f
501: 503 0000F138 incl _index /* bump the index */
502: 504 0000F138 jmp 3b /* test next data pattern */
503: 505 0000F138 1:
504: 506 0000F138 clrl _pipe_test /* reset the pipe-test flag */
505: 507 0000F138 ret /* return to test_code */
506: 508 0000F138
507: 509 0000F138
508: 510 0000F138
509: 511 0000F138
510: 512 0000F138 # ***************************************************************************
511: 513 0000F138 # *
512: 514 0000F138 # * TEST A NO OPERAND INSTRUCTION WITH AN ADD INSTRUCION IN FRONT OF IT
513: 515 0000F138 0000 # *
514: 516 0000F13A 0d 02 effffffe67 # ***************************************************************************
515: 517 0000F141 0d 8862 effffffe5f .text
516: 518 0000F149 1d 02 effffffe58 .align 1
517: 519 0000F150 31 0b .globl _test_0_pipe2
518: 520 0000F152 0d 8900c6 effffffe4d _test_0_pipe2:
519: 521 0000F15B 11 09 .word 0
520: 522 0000F15D 0d 8900c7 effffffe42 movl $2,_pipe_test /* set the pipe_test flag */
521: 523 0000F166 movl $0x62,_addr_code_p1 /* set the addr mode */
522: 524 0000F166 fe 04 effffffe3b cmpl $DBL,_acc_ld_size /* DBL or SGL ACC? */
523: 525 0000F16D dd 8f00000000 beql 1f
524: 526 0000F173 fe 08 effffffe2e movl $ADDF_OP_CODE,_pipe_inst1 /* pipe inst = add single */
525: 527 0000F17A dd 8f00000000 brb 2f
526: 528 0000F180 fe 08 effffffe21 1: movl $ADDD_OP_CODE,_pipe_inst1 /* pipe inst = add double */
527: 529 0000F187 ed effffffe1b effffffe1e 2:
528: 530 0000F192 ed effffffe10 effffffe13 callf $4,_pack_inst /* pack the instr's code */
529: 531 0000F19D pushl $_load_regs /* buffer for loading regs */
530: 534 0000F19D 4d effffffe05 callf $8,_fill_reg_buf /* fill the buffer */
531: 535 0000F1A3 pushl $_exp_regs /* expected reg values */
532: 536 0000F1A3 5c 04 effffffdfe 50 callf $8,_fill_reg_buf /* fill the buffer */
533: 537 0000F1AB 0d 40fffffffdf6 moval _dbl_ld_acc,_load_regs+8 /* R2 points to the data */
534: effffffdf1
535: 538 0000F1B7 6d 50 moval _dbl_ld_acc,_exp_regs+8 /* R2 points to the data */
536: 539 0000F1B9 0d 40fffffffde8 /*
537: effffffde7
538: 540 0000F1C5 * test the instruction
539: 541 0000F1C5 fe 04 effffffddc */
540: 542 0000F1CC 5d effffffdd6 clrl _index
541: 543 0000F1D2 21 f1 3:
542: 544 0000F1D4 1d effffffdce effffffdc9 mull3 $4,_index,r0 /* get longword offset */
543: 545 0000F1DF 81 0c movl *_data_ptr[r0],_dbl_ld_acc /* get load data's MSW */
544: 546 0000F1E1 6d effffffdc1 incl r0
545: 547 0000F1E7 71 efffffffb6 movl *_data_ptr[r0],_dbl_ld_acc+4 /* get load data's LSW */
546: 548 0000F1ED 2:
547: 549 0000F1ED 4d effffffdb5 callf $4,_run_code /* execute the instruction */
548: 550 0000F1F3 40 tstl _force_loop
549: 551 0000024c * bneq 2b /* loop on an error */
550: 552 0000024c * cmpl _index,_max_index /* last data pattern? */
551: 553 0000024c * bgeq 1f
552: 553 0000024c * bgeq 1f
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