![[BACK]](/cvsweb/icons/back.gif){kind=icon}
Return to test_inst.lst CVS log ![[TXT]](/cvsweb/icons/text.gif){kind=icon}
![[DIR]](/cvsweb/icons/dir.gif){kind=icon}
Up to [Power 6/32 Unix Tahoe 4.2BSD] / cci / d / fpevent|
Return to test_inst.lst CVS log | Up to [Power 6/32 Unix Tahoe 4.2BSD] / cci / d / fpevent |
Power 6/32 Unix version 1.21
1 00000000 LL0:
2 00000000 .data
3 00000998 * .text
4 00000000 .align 1
5 00000000 .globl _test_inst
6 00000000 _test_inst:
7 0000E610 0000 .word L382
8 0000E612 # #include "evt_defs.h"
9 0000E612 #
10 0000E612 # /**************************************************************************
11 0000E612 # *
12 0000E612 # * Test the current instruction
13 0000E612 # *
14 0000E612 # * 10-Apr-85 - changed the test to just check a couple of addr. modes
15 0000E612 # * 30-May-85 - added pipeline tests for A-loaded and B-loaded entries.
16 0000E612 # * 20-Jul-85 - added 3 operands for MULL3 integer overflow
17 0000E612 # **************************************************************************/
18 0000E612 # test_inst()
19 0000E612 # {
20 0000E612 13 00a8 jbr L384
21 0000E615 L385:
22 0000E615 # *adr_op1_ptr = (int) adr_op1; /* set word offset ptr #1 */
23 0000E615 0d effffffff5 fffffffff0 movl _adr_op1,*_adr_op1_ptr
24 0000E620 # *adr_op2_ptr = (int) adr_op2; /* set word offset ptr #2 */
25 0000E620 0d efffffffea ffffffffe5 movl _adr_op2,*_adr_op2_ptr
26 0000E62B # *adr_op3_ptr = (int) adr_op3; /* set word offset ptr #3 */
27 0000E62B 0d efffffffdf ffffffffda movl _adr_op3,*_adr_op3_ptr
28 0000E636 # asm("moval (sp),_monitor_sp"); /* save the stack pointer */
29 0000E636 ed 6e efffffffd3 moval (sp),_monitor_sp
30 0000E63D # asm("moval (fp),_monitor_fp"); /* save the frame pointer */
31 0000E63D ed 6d efffffffcc moval (fp),_monitor_fp
32 0000E644 # asm("movab _test_inst_ret,_unexp_event_ret");
33 0000E644 e9 ef00000064 efffffffc1 movab _test_inst_ret,_unexp_event_ret
34 0000E64F # error = FALSE; /* clear error flag */
35 0000E64F 4d efffffffbb clrl _error
36 0000E655 # set_load_flag(); /* set the LOAD ACC. flag */
37 0000E655 fe 04 ef00000906 callf $4,_set_load_flag
38 0000E65C # if( !no_ops )
39 0000E65C 5d efffffffae tstl _no_ops
40 0000E662 21 09 jneq L387
41 0000E664 # test_0_ops(); /* test inst w/ no operands */
42 0000E664 fe 04 efffffffa5 callf $4,_test_0_ops
43 0000E66B # else {
44 0000E66B 11 41 jbr L389
45 0000E66D L387:
46 0000E66D # tst_l(); /* longword displacement relative */
47 0000E66D fe 04 ef0000004c callf $4,_tst_l
48 0000E674 # tst_r(); /* direct register */
49 0000E674 fe 04 ef0000010b callf $4,_tst_r
50 0000E67B # tst_r_d(); /* register deferred */
51 0000E67B fe 04 ef0000022a callf $4,_tst_r_d
52 0000E682 # tst_r_ld(); /* register + longword displacement */
53 0000E682 fe 04 ef000002ef callf $4,_tst_r_ld
54 0000E689 # tst_x_fpd(); /* FP deferred + longword index */
55 0000E689 fe 04 ef000003e4 callf $4,_tst_x_fpd
56 0000E690 # tst_p1(); /* pipeline test #1, LDx <op.> */
57 0000E690 fe 04 ef000004fd callf $4,_tst_p1
58 0000E697 # if( (!load_type_inst) && (!no_fpp_wcs) )
59 0000E697 5d efffffff73 tstl _load_type_inst
60 0000E69D 21 0f jneq L396
61 0000E69F 5d efffffff6b tstl _no_fpp_wcs
62 0000E6A5 21 07 jneq L396
63 0000E6A7 # tst_p2(); /* pipeline test #2, ADDx <op.> */
64 0000E6A7 fe 04 ef0000064a callf $4,_tst_p2
65 0000E6AE # }
66 0000E6AE L396:
67 0000E6AE L389:
68 0000E6AE # asm(".globl _test_inst_ret");
69 0000E6AE .globl _test_inst_ret
70 0000E6AE # asm("_test_inst_ret:");
71 0000E6AE _test_inst_ret:
72 0000E6AE # asm("movl _monitor_sp,sp"); /* restore the stack ptr. */
73 0000E6AE 0d efffffff5c 5e movl _monitor_sp,sp
74 0000E6B5 # asm("movl _monitor_fp,fp"); /* restore the frame ptr. */
75 0000E6B5 0d efffffff55 5d movl _monitor_fp,fp
76 0000E6BC # }
77 0000E6BC 40 ret#2
78 0000E6BD .set L382,0x0
79 0000E6BD L384:
80 0000E6BD 13 ff55 jbr L385
81 0000E6C0 .data
82 00000998 * .text
83 0000E6C0 .align 1
84 0000E6C0 .globl _tst_l
85 0000E6C0 _tst_l:
86 0000E6C0 0000 .word L398
87 0000E6C2 #
88 0000E6C2 #
89 0000E6C2 #
90 0000E6C2 #
91 0000E6C2 #
92 0000E6C2 #
93 0000E6C2 # /*******************************************************************
94 0000E6C2 # * LONGWORD DISPLACEMENT RELATIVE ADDRESSING:
95 0000E6C2 # * instruction = <op-code> <ef> <offset to dmp_op_1>
96 0000E6C2 # * { <ef> <offset to dmp_op_2> }
97 0000E6C2 # * { <ef> <offset to dmp_op_3> }
98 0000E6C2 # *******************************************************************/
99 0000E6C2 # tst_l()
100 0000E6C2 # {
101 0000E6C2 13 00bd jbr L400
102 0000E6C5 L401:
103 0000E6C5 # pipe_test = FALSE;
104 0000E6C5 4d efffffff45 clrl _pipe_test
105 0000E6CB # fill_reg_buf( load_regs ); /* set data for registers */
106 0000E6CB dd 8f00000000 pushl $_load_regs
107 0000E6D1 fe 08 efffffff38 callf $8,_fill_reg_buf
108 0000E6D8 # fill_reg_buf( exp_regs ); /* set data for registers */
109 0000E6D8 dd 8f00000000 pushl $_exp_regs
110 0000E6DE fe 08 efffffff2b callf $8,_fill_reg_buf
111 0000E6E5 # addr_mode = ADR_L_DSP;
112 0000E6E5 0d 08 efffffff24 movl $8,_addr_mode
113 0000E6EC # addr_code = addr_code2 = addr_code3 = 0xef;
114 0000E6EC 0d 8900ef efffffff1b movl $239,_addr_code3
115 0000E6F5 0d efffffff15 50 movl _addr_code3,r0
116 0000E6FC 0d 50 efffffff0d movl r0,_addr_code2
117 0000E703 0d efffffff07 50 movl _addr_code2,r0
118 0000E70A 0d 50 effffffeff movl r0,_addr_code
119 0000E711 # addr_size = 4; /* longword (4 byte) ops. */
120 0000E711 0d 04 effffffef8 movl $4,_addr_size
121 0000E718 # addr_1 = os_op1 + 14; /* offset to the data */
122 0000E718 1c 0e effffffef1 50 addl3 $14,_os_op1,r0
123 0000E720 0d 50 effffffee9 movl r0,_addr_1
124 0000E727 # addr_2 = os_op2 + 9;
125 0000E727 1c 09 effffffee2 50 addl3 $9,_os_op2,r0
126 0000E72F 0d 50 effffffeda movl r0,_addr_2
127 0000E736 # addr_3 = os_op3 + 4;
128 0000E736 1c 04 effffffed3 50 addl3 $4,_os_op3,r0
129 0000E73E 0d 50 effffffecb movl r0,_addr_3
130 0000E745 # pack_inst(); /* pack the instr. code */
131 0000E745 fe 04 effffffec4 callf $4,_pack_inst
132 0000E74C # for( index = 0; index <= max_index; index++ ) {
133 0000E74C 4d effffffebe clrl _index
134 0000E752 L406:
135 0000E752 1d effffffeb8 effffffeb3 cmpl _index,_max_index
136 0000E75D 41 22 jgtr L405
137 0000E75F # get_current_data( adr_op1, adr_op2 );
138 0000E75F dd effffffeab pushl _adr_op2
139 0000E765 dd effffffea5 pushl _adr_op1
140 0000E76B fe 0c ef000006ee callf $12,_get_current_data
141 0000E772 # run_code(); /* execute the instruction */
142 0000E772 fe 04 effffffe97 callf $4,_run_code
143 0000E779 # }
144 0000E779 L404:
145 0000E779 6d effffffe91 incl _index
146 0000E77F 11 d1 jbr L406
147 0000E781 L405:
148 0000E781 # }
149 0000E781 40 ret#2
150 0000E782 .set L398,0x0
151 0000E782 L400:
152 0000E782 13 ff40 jbr L401
153 0000E785 .data
154 00000998 * .text
155 0000E785 00 .align 1
156 0000E786 .globl _tst_r
157 0000E786 _tst_r:
158 0000E786 0000 .word L409
159 0000E788 #
160 0000E788 #
161 0000E788 #
162 0000E788 # /*******************************************************************
163 0000E788 # * DIRECT REGISTER ADDRESSING:
164 0000E788 # * instruction = <op-code> <50> { <54> <56> }
165 0000E788 # *******************************************************************/
166 0000E788 # tst_r()
167 0000E788 # {
168 0000E788 13 011e jbr L411
169 0000E78B L412:
170 0000E78B # pipe_test = FALSE;
171 0000E78B 4d effffffe7f clrl _pipe_test
172 0000E791 # fill_reg_buf( load_regs ); /* set data for registers */
173 0000E791 dd 8f00000000 pushl $_load_regs
174 0000E797 fe 08 effffffe72 callf $8,_fill_reg_buf
175 0000E79E # fill_reg_buf( exp_regs ); /* set data for registers */
176 0000E79E dd 8f00000000 pushl $_exp_regs
177 0000E7A4 fe 08 effffffe65 callf $8,_fill_reg_buf
178 0000E7AB # if( op_code == MULL3_OP_CODE )
179 0000E7AB 1d effffffe5f 885c cmpl _op_code,$92
180 0000E7B3 21 06 jneq L413
181 0000E7B5 # exp_regs[6] = 0; /* final op #3 should = 0 */
182 0000E7B5 4d effffffe6d clrl _exp_regs+24
183 0000E7BB # addr_mode = ADR_REG;
184 0000E7BB L413:
185 0000E7BB 0d 0c effffffe4e movl $12,_addr_mode
186 0000E7C2 # addr_code = 0x50; /* 1st op in registers 0/1 */
187 0000E7C2 0d 8850 effffffe46 movl $80,_addr_code
188 0000E7CA # addr_code2 = 0x54; /* 2nd op in registers 4/5 */
189 0000E7CA 0d 8854 effffffe3e movl $84,_addr_code2
190 0000E7D2 # addr_code3 = 0x56; /* 3rd op in registers 6 */
191 0000E7D2 0d 8856 effffffe36 movl $86,_addr_code3
192 0000E7DA # addr_size = 0; /* no addressing bytes */
193 0000E7DA 4d effffffe30 clrl _addr_size
194 0000E7E0 # pack_inst(); /* pack the instr. code */
195 0000E7E0 fe 04 effffffe29 callf $4,_pack_inst
196 0000E7E7 # for( index = 0; index <= max_index; index++ ) {
197 0000E7E7 4d effffffe23 clrl _index
198 0000E7ED L416:
199 0000E7ED 1d effffffe1d effffffe18 cmpl _index,_max_index
200 0000E7F8 51 03 13 00ab jgtr L415
201 0000E7FD # get_current_data( adr_op1, adr_op2 ); /* addr's not used */
202 0000E7FD dd effffffe0d pushl _adr_op2
203 0000E803 dd effffffe07 pushl _adr_op1
204 0000E809 fe 0c ef00000650 callf $12,_get_current_data
205 0000E810 # load_regs[0] = dbl_value_1.m; /* set the data */
206 0000E810 0d effffffdfa effffffdf5 movl _dbl_value_1,_load_regs
207 0000E81B # load_regs[1] = dbl_value_1.l;
208 0000E81B 0d effffffdf3 effffffdee movl _dbl_value_1+4,_load_regs+4
209 0000E826 # load_regs[4] = dbl_value_2.m;
210 0000E826 0d effffffde4 effffffdef movl _dbl_value_2,_load_regs+16
211 0000E831 # load_regs[5] = dbl_value_2.l;
212 0000E831 0d effffffddd effffffde8 movl _dbl_value_2+4,_load_regs+20
213 0000E83C # if( op_code == MULL2_OP_CODE )
214 0000E83C 1d effffffdce 884c cmpl _op_code,$76
215 0000E844 21 08 jneq L417
216 0000E846 # exp_regs[4] = 0; /* final op #2 should = 0 */
217 0000E846 4d effffffdd4 clrl _exp_regs+16
218 0000E84C # else /* op #2 shouldn't change */
219 0000E84C 11 0b jbr L418
220 0000E84E L417:
221 0000E84E # exp_regs[4] = dbl_value_2.m;
222 0000E84E 0d effffffdbc effffffdc7 movl _dbl_value_2,_exp_regs+16
223 0000E859 L418:
224 0000E859 # exp_regs[5] = dbl_value_2.l;
225 0000E859 0d effffffdb5 effffffdc0 movl _dbl_value_2+4,_exp_regs+20
226 0000E864 # exp_regs[1] = dbl_value_1.l; /* op #1's LSW won't change */
227 0000E864 0d effffffdaa effffffda5 movl _dbl_value_1+4,_exp_regs+4
228 0000E86F # if( (op_code == CVFL_OP_CODE) || /* correct for sgl store */
229 0000E86F # (op_code == CVDL_OP_CODE) )
230 0000E86F 1d effffffd9b 890086 cmpl _op_code,$134
231 0000E878 31 0b jeql L9999
232 0000E87A 1d effffffd90 890087 cmpl _op_code,$135
233 0000E883 21 08 jneq L419
234 0000E885 L9999:
235 0000E885 # exp_regs[0] = 0; /* ovfl results are cleared */
236 0000E885 4d effffffd85 clrl _exp_regs
237 0000E88B # else
238 0000E88B 11 0b jbr L420
239 0000E88D L419:
240 0000E88D # exp_regs[0] = dbl_value_1.m;
241 0000E88D 0d effffffd7d effffffd78 movl _dbl_value_1,_exp_regs
242 0000E898 L420:
243 0000E898 # run_code(); /* execute the instruction */
244 0000E898 fe 04 effffffd71 callf $4,_run_code
245 0000E89F # }
246 0000E89F L414:
247 0000E89F 6d effffffd6b incl _index
248 0000E8A5 13 ff45 jbr L416
249 0000E8A8 L415:
250 0000E8A8 # }
251 0000E8A8 40 ret#2
252 0000E8A9 .set L409,0x0
253 0000E8A9 L411:
254 0000E8A9 13 fedf jbr L412
255 0000E8AC .data
256 00000998 * .text
257 0000E8AC .align 1
258 0000E8AC .globl _tst_r_d
259 0000E8AC _tst_r_d:
260 0000E8AC 0000 .word L421
261 0000E8AE #
262 0000E8AE #
263 0000E8AE #
264 0000E8AE # /*******************************************************************
265 0000E8AE # * REGISTER DEFERRED ADDRESSING:
266 0000E8AE # * instruction = <op-code> <60> { <61> <62> }
267 0000E8AE # *******************************************************************/
268 0000E8AE # tst_r_d()
269 0000E8AE # {
270 0000E8AE 13 00c4 jbr L423
271 0000E8B1 L424:
272 0000E8B1 # pipe_test = FALSE;
273 0000E8B1 4d effffffd59 clrl _pipe_test
274 0000E8B7 # fill_reg_buf( load_regs ); /* set data for registers */
275 0000E8B7 dd 8f00000000 pushl $_load_regs
276 0000E8BD fe 08 effffffd4c callf $8,_fill_reg_buf
277 0000E8C4 # fill_reg_buf( exp_regs ); /* set data for registers */
278 0000E8C4 dd 8f00000000 pushl $_exp_regs
279 0000E8CA fe 08 effffffd3f callf $8,_fill_reg_buf
280 0000E8D1 # addr_mode = ADR_REG_DEF;
281 0000E8D1 0d 0d effffffd38 movl $13,_addr_mode
282 0000E8D8 # addr_code = 0x60;
283 0000E8D8 0d 8860 effffffd30 movl $96,_addr_code
284 0000E8E0 # addr_code2 = 0x61;
285 0000E8E0 0d 8861 effffffd28 movl $97,_addr_code2
286 0000E8E8 # addr_code3 = 0x62;
287 0000E8E8 0d 8862 effffffd20 movl $98,_addr_code3
288 0000E8F0 # addr_size = 0; /* no address byte(s) */
289 0000E8F0 4d effffffd1a clrl _addr_size
290 0000E8F6 # load_regs[0] = (int) adr_op1; /* get addr of op. 1 */
291 0000E8F6 0d effffffd14 effffffd0f movl _adr_op1,_load_regs
292 0000E901 # load_regs[1] = (int) adr_op2; /* get addr of op. 2 */
293 0000E901 0d effffffd09 effffffd08 movl _adr_op2,_load_regs+4
294 0000E90C # load_regs[2] = (int) adr_op3; /* get addr of op. 3 */
295 0000E90C 0d effffffcfe effffffd01 movl _adr_op3,_load_regs+8
296 0000E917 # exp_regs[0] = load_regs[0];
297 0000E917 0d effffffcf3 effffffcee movl _load_regs,_exp_regs
298 0000E922 # exp_regs[1] = load_regs[1];
299 0000E922 0d effffffcec effffffce7 movl _load_regs+4,_exp_regs+4
300 0000E92D # exp_regs[2] = load_regs[2];
301 0000E92D 0d effffffce5 effffffce0 movl _load_regs+8,_exp_regs+8
302 0000E938 # pack_inst(); /* pack the instr. code */
303 0000E938 fe 04 effffffcd1 callf $4,_pack_inst
304 0000E93F # for( index = 0; index <= max_index; index++ ) {
305 0000E93F 4d effffffccb clrl _index
306 0000E945 L427:
307 0000E945 1d effffffcc5 effffffcc0 cmpl _index,_max_index
308 0000E950 41 22 jgtr L426
309 0000E952 # get_current_data( adr_op1, adr_op2 );
310 0000E952 dd effffffcb8 pushl _adr_op2
311 0000E958 dd effffffcb2 pushl _adr_op1
312 0000E95E fe 0c ef000004fb callf $12,_get_current_data
313 0000E965 # run_code(); /* execute the instruction */
314 0000E965 fe 04 effffffca4 callf $4,_run_code
315 0000E96C # }
316 0000E96C L425:
317 0000E96C 6d effffffc9e incl _index
318 0000E972 11 d1 jbr L427
319 0000E974 L426:
320 0000E974 # }
321 0000E974 40 ret#2
322 0000E975 .set L421,0x0
323 0000E975 L423:
324 0000E975 13 ff39 jbr L424
325 0000E978 .data
326 00000998 * .text
327 0000E978 .align 1
328 0000E978 .globl _tst_r_ld
329 0000E978 _tst_r_ld:
330 0000E978 0000 .word L428
331 0000E97A #
332 0000E97A #
333 0000E97A #
334 0000E97A #
335 0000E97A # /*******************************************************************
336 0000E97A # * REGISTER + LONGWORD DISPLACEMENT DEFERRED ADDRESSING:
337 0000E97A # * instruction = <op-code> <f4> <(longword &ptr_to_op_1 -r4)>
338 0000E97A # * { <f5> <(longword &ptr_to_op_2 -r5)> }
339 0000E97A # * { <f6> <(longword &ptr_to_op_3 -r6)> }
340 0000E97A # *******************************************************************/
341 0000E97A # tst_r_ld()
342 0000E97A # {
343 0000E97A 13 00f3 jbr L430
344 0000E97D L431:
345 0000E97D # pipe_test = FALSE;
346 0000E97D 4d effffffc8d clrl _pipe_test
347 0000E983 # fill_reg_buf( load_regs ); /* set data for registers */
348 0000E983 dd 8f00000000 pushl $_load_regs
349 0000E989 fe 08 effffffc80 callf $8,_fill_reg_buf
350 0000E990 # fill_reg_buf( exp_regs ); /* set data for registers */
351 0000E990 dd 8f00000000 pushl $_exp_regs
352 0000E996 fe 08 effffffc73 callf $8,_fill_reg_buf
353 0000E99D # addr_mode = ADR_REG_L_DEF;
354 0000E99D 0d 18 effffffc6c movl $24,_addr_mode
355 0000E9A4 # addr_code = 0xf4; /* addr 1 is offset by r4 */
356 0000E9A4 0d 8900f4 effffffc63 movl $244,_addr_code
357 0000E9AD # addr_code2 = 0xf5; /* addr 2 is offset by r5 */
358 0000E9AD 0d 8900f5 effffffc5a movl $245,_addr_code2
359 0000E9B6 # addr_code3 = 0xf6; /* addr 3 is offset by r6 */
360 0000E9B6 0d 8900f6 effffffc51 movl $246,_addr_code3
361 0000E9BF # addr_size = 4; /* longword (4 byte) op. */
362 0000E9BF 0d 04 effffffc4a movl $4,_addr_size
363 0000E9C6 # addr_1 = (int) adr_op1_ptr - 123; /* set the 1st offset */
364 0000E9C6 3c 887b effffffc42 50 subl3 $123,_adr_op1_ptr,r0
365 0000E9CF 0d 50 effffffc3a movl r0,_addr_1
366 0000E9D6 # addr_2 = (int) adr_op2_ptr - 212; /* set the 2nd offset */
367 0000E9D6 3c 8900d4 effffffc31 50 subl3 $212,_adr_op2_ptr,r0
368 0000E9E0 0d 50 effffffc29 movl r0,_addr_2
369 0000E9E7 # addr_3 = (int) adr_op3_ptr - 256; /* set the 3rd offset */
370 0000E9E7 3c 890100 effffffc20 50 subl3 $256,_adr_op3_ptr,r0
371 0000E9F1 0d 50 effffffc18 movl r0,_addr_3
372 0000E9F8 # pack_inst(); /* pack the instr. code */
373 0000E9F8 fe 04 effffffc11 callf $4,_pack_inst
374 0000E9FF # load_regs[4] = 123; /* reg 4 = 123 */
375 0000E9FF 0d 887b effffffc19 movl $123,_load_regs+16
376 0000EA07 # load_regs[5] = 212; /* reg 5 = 212 */
377 0000EA07 0d 8900d4 effffffc14 movl $212,_load_regs+20
378 0000EA10 # load_regs[6] = 256; /* reg 5 = 212 */
379 0000EA10 0d 890100 effffffc0f movl $256,_load_regs+24
380 0000EA19 # exp_regs[4] = load_regs[4];
381 0000EA19 0d effffffc01 effffffbfc movl _load_regs+16,_exp_regs+16
382 0000EA24 # exp_regs[5] = load_regs[5];
383 0000EA24 0d effffffbfa effffffbf5 movl _load_regs+20,_exp_regs+20
384 0000EA2F # exp_regs[6] = load_regs[6];
385 0000EA2F 0d effffffbf3 effffffbee movl _load_regs+24,_exp_regs+24
386 0000EA3A # for( index = 0; index <= max_index; index++ ) {
387 0000EA3A 4d effffffbd0 clrl _index
388 0000EA40 L434:
389 0000EA40 1d effffffbca effffffbc5 cmpl _index,_max_index
390 0000EA4B 41 22 jgtr L433
391 0000EA4D # get_current_data( adr_op1, adr_op2 );
392 0000EA4D dd effffffbbd pushl _adr_op2
393 0000EA53 dd effffffbb7 pushl _adr_op1
394 0000EA59 fe 0c ef00000400 callf $12,_get_current_data
395 0000EA60 # run_code(); /* execute the instruction */
396 0000EA60 fe 04 effffffba9 callf $4,_run_code
397 0000EA67 # }
398 0000EA67 L432:
399 0000EA67 6d effffffba3 incl _index
400 0000EA6D 11 d1 jbr L434
401 0000EA6F L433:
402 0000EA6F # }
403 0000EA6F 40 ret#2
404 0000EA70 .set L428,0x0
405 0000EA70 L430:
406 0000EA70 13 ff0a jbr L431
407 0000EA73 .data
408 00000998 * .text
409 0000EA73 00 .align 1
410 0000EA74 .globl _tst_x_fpd
411 0000EA74 _tst_x_fpd:
412 0000EA74 0000 .word L435
413 0000EA76 #
414 0000EA76 #
415 0000EA76 #
416 0000EA76 # /*******************************************************************
417 0000EA76 # * FRAME POINTER DEFERRED + LONGWORD INDEX ADDRESSING:
418 0000EA76 # * instruction = <op-code> <44> <6d> { <45> <6d> <46> <6d> }
419 0000EA76 # *
420 0000EA76 # * The indeces used will be either quadword indeces ( for DBL operands )
421 0000EA76 # * of longword indeces ( for SGL operands ).
422 0000EA76 # *
423 0000EA76 # * NOTE:
424 0000EA76 # * dmp_op_2 is exactly 4 pages away from dmp_op_1. (200 hex quadwords)
425 0000EA76 # * IF THIS RELATIVE DISPLACEMENT IS CHANGED THEN THE R5 INDEX MUST
426 0000EA76 # * BE CHANGED IN THIS CODE!!! ( used by CMPF2, CMPD2, MULL2, MULL3 )
427 0000EA76 # * dmp_op_3 is exactly 5 pages and 4 bytes away from dmp_op_1 (501 hex
428 0000EA76 # * longwords). This is needed for MULL3.
429 0000EA76 # *******************************************************************/
430 0000EA76 # tst_x_fpd()
431 0000EA76 # {
432 0000EA76 13 0118 jbr L437
433 0000EA79 L438:
434 0000EA79 # pipe_test = FALSE;
435 0000EA79 4d effffffb91 clrl _pipe_test
436 0000EA7F # fill_reg_buf( load_regs ); /* set data for registers */
437 0000EA7F dd 8f00000000 pushl $_load_regs
438 0000EA85 fe 08 effffffb84 callf $8,_fill_reg_buf
439 0000EA8C # fill_reg_buf( exp_regs ); /* set data for registers */
440 0000EA8C dd 8f00000000 pushl $_exp_regs
441 0000EA92 fe 08 effffffb77 callf $8,_fill_reg_buf
442 0000EA99 # addr_mode = ADR_I_FP_DEF;
443 0000EA99 0d 19 effffffb70 movl $25,_addr_mode
444 0000EAA0 # addr_code = 0x44; /* code for reg. 4 index */
445 0000EAA0 0d 8844 effffffb68 movl $68,_addr_code
446 0000EAA8 # addr_code2 = 0x45; /* code for reg. 5 index */
447 0000EAA8 0d 8845 effffffb60 movl $69,_addr_code2
448 0000EAB0 # addr_code3 = 0x46; /* code for reg. 6 index */
449 0000EAB0 0d 8846 effffffb58 movl $70,_addr_code3
450 0000EAB8 # addr_codeB = 0x6d; /* code for FP deferred */
451 0000EAB8 0d 886d effffffb50 movl $109,_addr_codeB
452 0000EAC0 # addr_size = 0; /* no addr. field per se */
453 0000EAC0 4d effffffb4a clrl _addr_size
454 0000EAC6 # pack_inst(); /* pack the instr. code */
455 0000EAC6 fe 04 effffffb43 callf $4,_pack_inst
456 0000EACD # /*
457 0000EACD # * set the frame pointer to '&operand_1 - 16 bytes' (2 quad-words)
458 0000EACD # */
459 0000EACD # sgl_dummy1 = (int) adr_op1; /* get the addr of op #1 */
460 0000EACD 0d effffffb3d effffffb38 movl _adr_op1,_sgl_dummy1
461 0000EAD8 # load_regs[13] = sgl_dummy1-16; /* FP = op 1's addr - 16 */
462 0000EAD8 3c 10 effffffb31 50 subl3 $16,_sgl_dummy1,r0
463 0000EAE0 0d 50 effffffb5d movl r0,_load_regs+52
464 0000EAE7 # exp_regs[13] = load_regs[13];
465 0000EAE7 0d effffffb57 effffffb52 movl _load_regs+52,_exp_regs+52
466 0000EAF2 # if( (sgl_op) || /* Should we use a longword */
467 0000EAF2 # (op_code == LDFD_OP_CODE) || /* or a quadword index? */
468 0000EAF2 # (op_code == CVLD_OP_CODE) ) {
469 0000EAF2 5d effffffb18 tstl _sgl_op
470 0000EAF8 21 15 jneq L9998
471 0000EAFA 1d effffffb10 890097 cmpl _op_code,$151
472 0000EB03 31 0a jeql L9998
473 0000EB05 1d effffffb05 8877 cmpl _op_code,$119
474 0000EB0D 21 1b jneq L439
475 0000EB0F L9998:
476 0000EB0F # load_regs[4] = 4; /* FP to op_1 (longwords) */
477 0000EB0F 0d 04 effffffb0a movl $4,_load_regs+16
478 0000EB16 # load_regs[5] = 0x404; /* FP to op_2 (longwords) */
479 0000EB16 0d 890404 effffffb05 movl $1028,_load_regs+20
480 0000EB1F # load_regs[6] = 0x505; /* FP to op_3 (longwords) */
481 0000EB1F 0d 890505 effffffb00 movl $1285,_load_regs+24
482 0000EB28 # } else {
483 0000EB28 11 10 jbr L440
484 0000EB2A L439:
485 0000EB2A # load_regs[4] = 2; /* FP to op_1 (quadwords) */
486 0000EB2A 0d 02 effffffaef movl $2,_load_regs+16
487 0000EB31 # load_regs[5] = 0x202; /* FP to op_2 (quadwords) */
488 0000EB31 0d 890202 effffffaea movl $514,_load_regs+20
489 0000EB3A # }
490 0000EB3A L440:
491 0000EB3A # exp_regs[4] = load_regs[4];
492 0000EB3A 0d effffffae0 effffffadb movl _load_regs+16,_exp_regs+16
493 0000EB45 # exp_regs[5] = load_regs[5];
494 0000EB45 0d effffffad9 effffffad4 movl _load_regs+20,_exp_regs+20
495 0000EB50 # exp_regs[6] = load_regs[6];
496 0000EB50 0d effffffad2 effffffacd movl _load_regs+24,_exp_regs+24
497 0000EB5B # for( index = 0; index <= max_index; index++ ) {
498 0000EB5B 4d effffffaaf clrl _index
499 0000EB61 L443:
500 0000EB61 1d effffffaa9 effffffaa4 cmpl _index,_max_index
501 0000EB6C 41 22 jgtr L442
502 0000EB6E # get_current_data( adr_op1, adr_op2 );
503 0000EB6E dd effffffa9c pushl _adr_op2
504 0000EB74 dd effffffa96 pushl _adr_op1
505 0000EB7A fe 0c ef000002df callf $12,_get_current_data
506 0000EB81 # run_code(); /* execute the instruction */
507 0000EB81 fe 04 effffffa88 callf $4,_run_code
508 0000EB88 # }
509 0000EB88 L441:
510 0000EB88 6d effffffa82 incl _index
511 0000EB8E 11 d1 jbr L443
512 0000EB90 L442:
513 0000EB90 # }
514 0000EB90 40 ret#2
515 0000EB91 .set L435,0x0
516 0000EB91 L437:
517 0000EB91 13 fee5 jbr L438
518 0000EB94 .data
519 00000998 * .text
520 0000EB94 .align 1
521 0000EB94 .globl _tst_p1
522 0000EB94 _tst_p1:
523 0000EB94 0000 .word L444
524 0000EB96 #
525 0000EB96 #
526 0000EB96 #
527 0000EB96 #
528 0000EB96 # /*******************************************************************
529 0000EB96 # * PIPELINE TEST #1 -LOAD THE ACCUMULATOR JUST BEFORE THE OPERATION
530 0000EB96 # * instruction = <ldx> <62> <op-code> <50> { <54> <56> }
531 0000EB96 # *******************************************************************/
532 0000EB96 # tst_p1()
533 0000EB96 # {
534 0000EB96 13 015c jbr L446
535 0000EB99 L447:
536 0000EB99 # pipe_test = 1; /* pipeline test #1 */
537 0000EB99 0d 01 effffffa70 movl $1,_pipe_test
538 0000EBA0 # if( acc_ld_size == DBL )
539 0000EBA0 1d effffffa6a 02 cmpl _acc_ld_size,$2
540 0000EBA7 21 09 jneq L448
541 0000EBA9 # pipe_inst1 = LDD_OP_CODE;
542 0000EBA9 0d 07 effffffa60 movl $7,_pipe_inst1
543 0000EBB0 # else
544 0000EBB0 11 07 jbr L449
545 0000EBB2 L448:
546 0000EBB2 # pipe_inst1 = LDF_OP_CODE;
547 0000EBB2 0d 06 effffffa57 movl $6,_pipe_inst1
548 0000EBB9 L449:
549 0000EBB9 # fill_reg_buf( load_regs ); /* set data for registers */
550 0000EBB9 dd 8f00000000 pushl $_load_regs
551 0000EBBF fe 08 effffffa4a callf $8,_fill_reg_buf
552 0000EBC6 # fill_reg_buf( exp_regs ); /* set data for registers */
553 0000EBC6 dd 8f00000000 pushl $_exp_regs
554 0000EBCC fe 08 effffffa3d callf $8,_fill_reg_buf
555 0000EBD3 # if( op_code == MULL3_OP_CODE )
556 0000EBD3 1d effffffa37 885c cmpl _op_code,$92
557 0000EBDB 21 06 jneq L450
558 0000EBDD # exp_regs[6] = 0; /* op 3 s/b = 0 if MULL3 */
559 0000EBDD 4d effffffa45 clrl _exp_regs+24
560 0000EBE3 # addr_code_p1 = 0x62; /* piped load is via reg 2 */
561 0000EBE3 L450:
562 0000EBE3 0d 8862 effffffa25 movl $98,_addr_code_p1
563 0000EBEB # load_regs[2] = (int)&dbl_ld_acc; /* point R2 to the load data */
564 0000EBEB 0d 8f00000000 effffffa22 movl $_dbl_ld_acc,_load_regs+8
565 0000EBF6 # exp_regs[2] = (int)&dbl_ld_acc;
566 0000EBF6 0d 8f00000000 effffffa17 movl $_dbl_ld_acc,_exp_regs+8
567 0000EC01 # addr_mode = ADR_REG;
568 0000EC01 0d 0c effffffa08 movl $12,_addr_mode
569 0000EC08 # addr_code = 0x50; /* 1st op in registers 0/1 */
570 0000EC08 0d 8850 effffffa00 movl $80,_addr_code
571 0000EC10 # addr_code2 = 0x54; /* 2nd op in registers 4/5 */
572 0000EC10 0d 8854 effffff9f8 movl $84,_addr_code2
573 0000EC18 # addr_code3 = 0x56; /* 3rd op in register 6 */
574 0000EC18 0d 8856 effffff9f0 movl $86,_addr_code3
575 0000EC20 # addr_size = 0; /* no addressing bytes */
576 0000EC20 4d effffff9ea clrl _addr_size
577 0000EC26 # pack_inst(); /* pack the instr. code */
578 0000EC26 fe 04 effffff9e3 callf $4,_pack_inst
579 0000EC2D # for( index = 0; index <= max_index; index++ ) {
580 0000EC2D 4d effffff9dd clrl _index
581 0000EC33 L453:
582 0000EC33 1d effffff9d7 effffff9d2 cmpl _index,_max_index
583 0000EC3E 51 03 13 00ab jgtr L452
584 0000EC43 # get_current_data( adr_op1, adr_op2 ); /* addr's not used */
585 0000EC43 dd effffff9c7 pushl _adr_op2
586 0000EC49 dd effffff9c1 pushl _adr_op1
587 0000EC4F fe 0c ef0000020a callf $12,_get_current_data
588 0000EC56 # load_regs[0] = dbl_value_1.m; /* set the data */
589 0000EC56 0d effffff9b4 effffff9af movl _dbl_value_1,_load_regs
590 0000EC61 # load_regs[1] = dbl_value_1.l;
591 0000EC61 0d effffff9ad effffff9a8 movl _dbl_value_1+4,_load_regs+4
592 0000EC6C # load_regs[4] = dbl_value_2.m;
593 0000EC6C 0d effffff99e effffff9a9 movl _dbl_value_2,_load_regs+16
594 0000EC77 # load_regs[5] = dbl_value_2.l;
595 0000EC77 0d effffff997 effffff9a2 movl _dbl_value_2+4,_load_regs+20
596 0000EC82 # if( op_code == MULL2_OP_CODE )
597 0000EC82 1d effffff988 884c cmpl _op_code,$76
598 0000EC8A 21 08 jneq L454
599 0000EC8C # exp_regs[4] = 0; /* op 2 s/b = 0 if MULL2 */
600 0000EC8C 4d effffff98e clrl _exp_regs+16
601 0000EC92 # else
602 0000EC92 11 0b jbr L455
603 0000EC94 L454:
604 0000EC94 # exp_regs[4] = dbl_value_2.m;
605 0000EC94 0d effffff976 effffff981 movl _dbl_value_2,_exp_regs+16
606 0000EC9F L455:
607 0000EC9F # exp_regs[5] = dbl_value_2.l;
608 0000EC9F 0d effffff96f effffff97a movl _dbl_value_2+4,_exp_regs+20
609 0000ECAA # exp_regs[1] = dbl_value_1.l; /* op #1's LSW won't change */
610 0000ECAA 0d effffff964 effffff95f movl _dbl_value_1+4,_exp_regs+4
611 0000ECB5 # if( (op_code == CVFL_OP_CODE) || /* correct for sgl store */
612 0000ECB5 # (op_code == CVDL_OP_CODE) )
613 0000ECB5 1d effffff955 890086 cmpl _op_code,$134
614 0000ECBE 31 0b jeql L9997
615 0000ECC0 1d effffff94a 890087 cmpl _op_code,$135
616 0000ECC9 21 08 jneq L456
617 0000ECCB L9997:
618 0000ECCB # exp_regs[0] = 0; /* fault results are cleared */
619 0000ECCB 4d effffff93f clrl _exp_regs
620 0000ECD1 # else
621 0000ECD1 11 0b jbr L457
622 0000ECD3 L456:
623 0000ECD3 # exp_regs[0] = dbl_value_1.m;
624 0000ECD3 0d effffff937 effffff932 movl _dbl_value_1,_exp_regs
625 0000ECDE L457:
626 0000ECDE # run_code(); /* execute the instruction */
627 0000ECDE fe 04 effffff92b callf $4,_run_code
628 0000ECE5 # }
629 0000ECE5 L451:
630 0000ECE5 6d effffff925 incl _index
631 0000ECEB 13 ff45 jbr L453
632 0000ECEE L452:
633 0000ECEE # pipe_test = FALSE;
634 0000ECEE 4d effffff91c clrl _pipe_test
635 0000ECF4 # }
636 0000ECF4 40 ret#2
637 0000ECF5 .set L444,0x0
638 0000ECF5 L446:
639 0000ECF5 13 fea1 jbr L447
640 0000ECF8 .data
641 00000998 * .text
642 0000ECF8 .align 1
643 0000ECF8 .globl _tst_p2
644 0000ECF8 _tst_p2:
645 0000ECF8 0000 .word L458
646 0000ECFA #
647 0000ECFA #
648 0000ECFA #
649 0000ECFA #
650 0000ECFA #
651 0000ECFA # /*******************************************************************
652 0000ECFA # * PIPELINE TEST #2 -ADD TO THE ACCUMULATOR JUST BEFORE THE OPERATION
653 0000ECFA # * instruction = <addx> <62> <op-code> <50> { <54> <56> }
654 0000ECFA # *******************************************************************/
655 0000ECFA # tst_p2()
656 0000ECFA # {
657 0000ECFA 13 0160 jbr L460
658 0000ECFD L461:
659 0000ECFD # pipe_test = 2; /* pipeline test #2 */
660 0000ECFD 0d 02 effffff90c movl $2,_pipe_test
661 0000ED04 # if( acc_ld_size == DBL )
662 0000ED04 1d effffff906 02 cmpl _acc_ld_size,$2
663 0000ED0B 21 0b jneq L462
664 0000ED0D # pipe_inst1 = ADDD_OP_CODE;
665 0000ED0D 0d 8900c7 effffff8fa movl $199,_pipe_inst1
666 0000ED16 # else
667 0000ED16 11 09 jbr L463
668 0000ED18 L462:
669 0000ED18 # pipe_inst1 = ADDF_OP_CODE;
670 0000ED18 0d 8900c6 effffff8ef movl $198,_pipe_inst1
671 0000ED21 L463:
672 0000ED21 # fill_reg_buf( load_regs ); /* set data for registers */
673 0000ED21 dd 8f00000000 pushl $_load_regs
674 0000ED27 fe 08 effffff8e2 callf $8,_fill_reg_buf
675 0000ED2E # fill_reg_buf( exp_regs ); /* set data for registers */
676 0000ED2E dd 8f00000000 pushl $_exp_regs
677 0000ED34 fe 08 effffff8d5 callf $8,_fill_reg_buf
678 0000ED3B # addr_code_p1 = 0x62; /* piped load is via reg 2 */
679 0000ED3B 0d 8862 effffff8cd movl $98,_addr_code_p1
680 0000ED43 # load_regs[2] = (int)&dbl_ld_acc; /* point R2 to the load data */
681 0000ED43 0d 8f00000000 effffff8ca movl $_dbl_ld_acc,_load_regs+8
682 0000ED4E # exp_regs[2] = (int)&dbl_ld_acc;
683 0000ED4E 0d 8f00000000 effffff8bf movl $_dbl_ld_acc,_exp_regs+8
684 0000ED59 # if( op_code == MULL3_OP_CODE )
685 0000ED59 1d effffff8b1 885c cmpl _op_code,$92
686 0000ED61 21 06 jneq L464
687 0000ED63 # exp_regs[6] = 0; /* op 3 s/b = 0 */
688 0000ED63 4d effffff8bf clrl _exp_regs+24
689 0000ED69 # addr_mode = ADR_REG;
690 0000ED69 L464:
691 0000ED69 0d 0c effffff8a0 movl $12,_addr_mode
692 0000ED70 # addr_code = 0x50; /* 1st op in registers 0/1 */
693 0000ED70 0d 8850 effffff898 movl $80,_addr_code
694 0000ED78 # addr_code2 = 0x54; /* 2nd op in registers 4/5 */
695 0000ED78 0d 8854 effffff890 movl $84,_addr_code2
696 0000ED80 # addr_code3 = 0x56; /* 3rd op in register 6 */
697 0000ED80 0d 8856 effffff888 movl $86,_addr_code3
698 0000ED88 # addr_size = 0; /* no addressing bytes */
699 0000ED88 4d effffff882 clrl _addr_size
700 0000ED8E # pack_inst(); /* pack the instr. code */
701 0000ED8E fe 04 effffff87b callf $4,_pack_inst
702 0000ED95 # for( index = 0; index <= max_index; index++ ) {
703 0000ED95 4d effffff875 clrl _index
704 0000ED9B L467:
705 0000ED9B 1d effffff86f effffff86a cmpl _index,_max_index
706 0000EDA6 51 03 13 00ab jgtr L466
707 0000EDAB # get_current_data( adr_op1, adr_op2 ); /* addr's not used */
708 0000EDAB dd effffff85f pushl _adr_op2
709 0000EDB1 dd effffff859 pushl _adr_op1
710 0000EDB7 fe 0c ef000000a2 callf $12,_get_current_data
711 0000EDBE # load_regs[0] = dbl_value_1.m; /* set the data */
712 0000EDBE 0d effffff84c effffff847 movl _dbl_value_1,_load_regs
713 0000EDC9 # load_regs[1] = dbl_value_1.l;
714 0000EDC9 0d effffff845 effffff840 movl _dbl_value_1+4,_load_regs+4
715 0000EDD4 # load_regs[4] = dbl_value_2.m;
716 0000EDD4 0d effffff836 effffff841 movl _dbl_value_2,_load_regs+16
717 0000EDDF # load_regs[5] = dbl_value_2.l;
718 0000EDDF 0d effffff82f effffff83a movl _dbl_value_2+4,_load_regs+20
719 0000EDEA # if( op_code == MULL2_OP_CODE )
720 0000EDEA 1d effffff820 884c cmpl _op_code,$76
721 0000EDF2 21 08 jneq L468
722 0000EDF4 # exp_regs[4] = 0; /* op 2 s/b = 0 */
723 0000EDF4 4d effffff826 clrl _exp_regs+16
724 0000EDFA # else
725 0000EDFA 11 0b jbr L469
726 0000EDFC L468:
727 0000EDFC # exp_regs[4] = dbl_value_2.m; /* op #2 s/n change */
728 0000EDFC 0d effffff80e effffff819 movl _dbl_value_2,_exp_regs+16
729 0000EE07 L469:
730 0000EE07 # exp_regs[5] = dbl_value_2.l;
731 0000EE07 0d effffff807 effffff812 movl _dbl_value_2+4,_exp_regs+20
732 0000EE12 # exp_regs[1] = dbl_value_1.l; /* op #1's LSW won't change */
733 0000EE12 0d effffff7fc effffff7f7 movl _dbl_value_1+4,_exp_regs+4
734 0000EE1D # if( (op_code == CVFL_OP_CODE) || /* correct for sgl store */
735 0000EE1D # (op_code == CVDL_OP_CODE) )
736 0000EE1D 1d effffff7ed 890086 cmpl _op_code,$134
737 0000EE26 31 0b jeql L9996
738 0000EE28 1d effffff7e2 890087 cmpl _op_code,$135
739 0000EE31 21 08 jneq L470
740 0000EE33 L9996:
741 0000EE33 # exp_regs[0] = 0; /* fault results are cleared */
742 0000EE33 4d effffff7d7 clrl _exp_regs
743 0000EE39 # else
744 0000EE39 11 0b jbr L471
745 0000EE3B L470:
746 0000EE3B # exp_regs[0] = dbl_value_1.m;
747 0000EE3B 0d effffff7cf effffff7ca movl _dbl_value_1,_exp_regs
748 0000EE46 L471:
749 0000EE46 # run_code(); /* execute the instruction */
750 0000EE46 fe 04 effffff7c3 callf $4,_run_code
751 0000EE4D # }
752 0000EE4D L465:
753 0000EE4D 6d effffff7bd incl _index
754 0000EE53 13 ff45 jbr L467
755 0000EE56 L466:
756 0000EE56 # pipe_test = FALSE;
757 0000EE56 4d effffff7b4 clrl _pipe_test
758 0000EE5C # }
759 0000EE5C 40 ret#2
760 0000EE5D .set L458,0x0
761 0000EE5D L460:
762 0000EE5D 13 fe9d jbr L461
763 0000EE60 .data
764 00000998 * .text
765 0000EE60 .align 1
766 0000EE60 .globl _get_current_data
767 0000EE60 _get_current_data:
768 0000EE60 0000 .word L472
769 0000EE62 #
770 0000EE62 #
771 0000EE62 #
772 0000EE62 #
773 0000EE62 #
774 0000EE62 #
775 0000EE62 #
776 0000EE62 # /***************************************************************************
777 0000EE62 # * Get the Current Data Values
778 0000EE62 # *
779 0000EE62 # * In most cases the first operand is loaded into the accumulator.
780 0000EE62 # * If we're testing Reserved Operands then, unless it's LOGF, we'd better not
781 0000EE62 # * load the Accumulator with the Resop before executing the instruction.
782 0000EE62 # * Ergo and towit, we'll use a dummy Acc. for those cases.
783 0000EE62 # * The 4 instructions currently tested that have 2 or more operands are:
784 0000EE62 # * CMPF2, CMPD2, MULL2, MULL3. None of these accesses the accumulator so we'll
785 0000EE62 # * use dummy accumulator data for these too.
786 0000EE62 # ***************************************************************************/
787 0000EE62 # get_current_data( dptr_1, dptr_2 )
788 0000EE62 # struct u64 *dptr_1; /* pointer to 1st operand */
789 0000EE62 # struct u64 *dptr_2; /* pointer to 2nd operand */
790 0000EE62 # {
791 0000EE62 13 00fa jbr L474
792 0000EE65 L475:
793 0000EE65 # if( (no_ops >= 2) ||
794 0000EE65 # ((test_event == RESOP_CODE) && (op_code != LOGF_OP_CODE)) ) {
795 0000EE65 1d effffff7a5 02 cmpl _no_ops,$2
796 0000EE6C 81 12 jgeq L9995
797 0000EE6E 1d effffff79c 2d cmpl _test_event,$45
798 0000EE75 21 6a jneq L476
799 0000EE77 1d effffff793 35 cmpl _op_code,$53
800 0000EE7E 31 61 jeql L476
801 0000EE80 L9995:
802 0000EE80 # dbl_ld_acc = acc_data[ index ];
803 0000EE80 48 03 effffff789 50 shll $3,_index,r0
804 0000EE88 0c 8f00000000 50 addl2 $_acc_data,r0
805 0000EE8F 0d a004 effffff77d movl 4(r0),_dbl_ld_acc+4
806 0000EE97 0d 60 effffff772 movl (r0),_dbl_ld_acc
807 0000EE9E # dbl_value_1 = data_ptr[ index ].op_1;
808 0000EE9E 48 04 effffff76b 50 shll $4,_index,r0
809 0000EEA6 1c 50 effffff763 50 addl3 r0,_data_ptr,r0
810 0000EEAE 0d a004 effffff75e movl 4(r0),_dbl_value_1+4
811 0000EEB6 0d 60 effffff753 movl (r0),_dbl_value_1
812 0000EEBD # dbl_value_2 = data_ptr[ index ].op_2;
813 0000EEBD 48 04 effffff74c 50 shll $4,_index,r0
814 0000EEC5 1c 50 effffff744 50 addl3 r0,_data_ptr,r0
815 0000EECD 0c 08 50 addl2 $8,r0
816 0000EED0 0d a004 effffff73c movl 4(r0),_dbl_value_2+4
817 0000EED8 0d 60 effffff731 movl (r0),_dbl_value_2
818 0000EEDF # } else {
819 0000EEDF 11 57 jbr L477
820 0000EEE1 L476:
821 0000EEE1 # dbl_ld_acc = data_ptr[ index ].op_1;
822 0000EEE1 48 04 effffff728 50 shll $4,_index,r0
823 0000EEE9 1c 50 effffff720 50 addl3 r0,_data_ptr,r0
824 0000EEF1 0d a004 effffff71b movl 4(r0),_dbl_ld_acc+4
825 0000EEF9 0d 60 effffff710 movl (r0),_dbl_ld_acc
826 0000EF00 # dbl_value_1 = data_ptr[ index ].op_2;
827 0000EF00 48 04 effffff709 50 shll $4,_index,r0
828 0000EF08 1c 50 effffff701 50 addl3 r0,_data_ptr,r0
829 0000EF10 0c 08 50 addl2 $8,r0
830 0000EF13 0d a004 effffff6f9 movl 4(r0),_dbl_value_1+4
831 0000EF1B 0d 60 effffff6ee movl (r0),_dbl_value_1
832 0000EF22 # dbl_value_2 = dbl_value_1;
833 0000EF22 0d effffff6ec effffff6e7 movl _dbl_value_1+4,_dbl_value_2+4
834 0000EF2D 0d effffff6dd effffff6d8 movl _dbl_value_1,_dbl_value_2
835 0000EF38 # }
836 0000EF38 L477:
837 0000EF38 # *dptr_1 = dbl_value_1; /* set 1st operand */
838 0000EF38 0d 8f00000000 50 movl $_dbl_value_1,r0
839 0000EF3F 0d ad04 51 movl 4(fp),r1
840 0000EF43 0d a004 a104 movl 4(r0),4(r1)
841 0000EF48 0d 60 61 movl (r0),(r1)
842 0000EF4B # *dptr_2 = dbl_value_2; /* set 2nd operand */
843 0000EF4B 0d 8f00000000 50 movl $_dbl_value_2,r0
844 0000EF52 0d ad08 51 movl 8(fp),r1
845 0000EF56 0d a004 a104 movl 4(r0),4(r1)
846 0000EF5B 0d 60 61 movl (r0),(r1)
847 0000EF5E # }
848 0000EF5E 40 ret#2
849 0000EF5F .set L472,0x0
850 0000EF5F L474:
851 0000EF5F 13 ff03 jbr L475
852 0000EF62 .data
853 00000998 * .text
854 0000EF62 .align 1
855 0000EF62 .globl _set_load_flag
856 0000EF62 _set_load_flag:
857 0000EF62 0000 .word L478
858 0000EF64 #
859 0000EF64 #
860 0000EF64 #
861 0000EF64 #
862 0000EF64 # /*
863 0000EF64 # ***************************************************************************
864 0000EF64 # *
865 0000EF64 # * Set or reset the LOAD_ACCUMULATOR flag
866 0000EF64 # *
867 0000EF64 # * If the current instruction loads the accumulator then set the flag.
868 0000EF64 # ***************************************************************************
869 0000EF64 # */
870 0000EF64 # set_load_flag()
871 0000EF64 # {
872 0000EF64 11 3f jbr L480
873 0000EF66 L481:
874 0000EF66 # if( (op_code == LDF_OP_CODE) || /* load SGL Acc. */
875 0000EF66 # (op_code == LNF_OP_CODE) || /* load / negate SGL Acc. */
876 0000EF66 # (op_code == LDD_OP_CODE) || /* load SGL Acc. */
877 0000EF66 # (op_code == LND_OP_CODE) || /* load / negate SGL Acc. */
878 0000EF66 # (op_code == LDFD_OP_CODE) ) /* load SGL to DBL Acc. */
879 0000EF66 1d effffff6a4 06 cmpl _op_code,$6
880 0000EF6D 31 26 jeql L9994
881 0000EF6F 1d effffff69b 16 cmpl _op_code,$22
882 0000EF76 31 1d jeql L9994
883 0000EF78 1d effffff692 07 cmpl _op_code,$7
884 0000EF7F 31 14 jeql L9994
885 0000EF81 1d effffff689 17 cmpl _op_code,$23
886 0000EF88 31 0b jeql L9994
887 0000EF8A 1d effffff680 890097 cmpl _op_code,$151
888 0000EF93 21 09 jneq L482
889 0000EF95 L9994:
890 0000EF95 # load_type_inst = TRUE;
891 0000EF95 0d 01 effffff674 movl $1,_load_type_inst
892 0000EF9C # else
893 0000EF9C 11 06 jbr L483
894 0000EF9E L482:
895 0000EF9E # load_type_inst = FALSE;
896 0000EF9E 4d effffff66c clrl _load_type_inst
897 0000EFA4 L483:
898 0000EFA4 # }
899 0000EFA4 40 ret#2
900 0000EFA5 .set L478,0x0
901 0000EFA5 L480:
902 0000EFA5 11 bf jbr L481
903 0000EFA7 .data
904 00000998 * #
904 00000998 * #
This archive runs on limited infrastructure. Preserving old code on modern bandwidth. Automated agents are requested to crawl responsibly.