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1.1 root 1: 1 00000000 LL0:
2: 2 00000000 .data
3: 3 000001ec * .text
4: 4 00000000 .align 1
5: 5 00000000 .globl _undfl_test
6: 6 00000000 _undfl_test:
7: 7 0000E244 0000 .word L381
8: 8 0000E246 #
9: 9 0000E246 # #include "evt_defs.h"
10: 10 0000E246 #
11: 11 0000E246 # /*
12: 12 0000E246 # ********************************************************************
13: 13 0000E246 # *
14: 14 0000E246 # * MONITOR FOR THE FPP UNDERFLOW EVENT TEST
15: 15 0000E246 # *
16: 16 0000E246 # * 25-Mar-85 JJM: written
17: 17 0000E246 # * 29-Mar-85 JJM: mauled the beast for CVDF (cvdf has ovfl but no undfl)
18: 18 0000E246 # *
19: 19 0000E246 # ********************************************************************
20: 20 0000E246 # */
21: 21 0000E246 # undfl_test()
22: 22 0000E246 # {
23: 23 0000E246 13 00e1 jbr L383
24: 24 0000E249 L384:
25: 25 0000E249 # event_msg = "Underflow";
26: 26 0000E249 .data 1
27: 27 000001ec * L385:
28: 28 000001ec * 556E646572666C6F7700 .ascii "Underflow\0"
29: 29 000001f6 * .text
30: 30 0000E249 0d 8f000001ec effffffff0 movl $L385,_event_msg
31: 31 0000E254 # test_event = ARITH_CODE; /* expect an arithmetic fault */
32: 32 0000E254 0d 34 efffffffe9 movl $52,_test_event
33: 33 0000E25B # exp_code = FLT_UNDFL_CODE; /* -specificly floating underflow */
34: 34 0000E25B 0d 05 efffffffe2 movl $5,_exp_code
35: 35 0000E262 # if( evt_inst ) /* was the op-code specified? */
36: 36 0000E262 5d efffffffdc tstl _evt_inst
37: 37 0000E268 31 7a jeql L386
38: 38 0000E26A # {
39: 39 0000E26A # inst_index = get_ovfl_index( evt_inst );
40: 40 0000E26A dd efffffffd4 pushl _evt_inst
41: 41 0000E270 fe 08 efffffffcd callf $8,_get_ovfl_index
42: 42 0000E277 0d 50 efffffffc6 movl r0,_inst_index
43: 43 0000E27E # if( (inst_index < 0) ||
44: 44 0000E27E # (ovfl_tbl[inst_index].undfl_data == null_data) )
45: 45 0000E27E 5d efffffffc0 tstl _inst_index
46: 46 0000E284 91 18 jlss L9999
47: 47 0000E286 0d efffffffb8 50 movl _inst_index,r0
48: 48 0000E28D 48 05 50 50 shll $5,r0,r0
49: 49 0000E291 1d e000000018 8f00000000 cmpl _ovfl_tbl+24(r0),$_null_data
50: 50 0000E29C 21 3d jneq L388
51: 51 0000E29E L9999:
52: 52 0000E29E # {
53: 53 0000E29E # if( (prt_hdrs) && (cycle == 1) )
54: 54 0000E29E 5d efffffffa0 tstl _prt_hdrs
55: 55 0000E2A4 31 33 jeql L389
56: 56 0000E2A6 1d efffffff98 01 cmpl _cycle,$1
57: 57 0000E2AD 21 2a jneq L389
58: 58 0000E2AF # {
59: 59 0000E2AF # writes(
60: 60 0000E2AF # "There are no UNDERFLOW faults with op-code ");
61: 61 0000E2AF .data 1
62: 62 000001f6 * L391:
63: 63 000001f6 * 546865726520617265206E6F2 .ascii "There are no UNDERFLOW faults with op-code \0"
64: 0554E444552464C4F57206661
65: 756C74732077697468206F702
66: D636F64652000
67: 64 00000222 * .text
68: 65 0000E2AF dd 8f000001f6 pushl $L391
69: 66 0000E2B5 fe 08 efffffff88 callf $8,_writes
70: 67 0000E2BC # writeh( evt_inst ); /* print the ersatz op-code */
71: 68 0000E2BC dd efffffff82 pushl _evt_inst
72: 69 0000E2C2 fe 08 efffffff7b callf $8,_writeh
73: 70 0000E2C9 # writec('\n');
74: 71 0000E2C9 dd 0a pushl $10
75: 72 0000E2CB fe 08 efffffff72 callf $8,_writec
76: 73 0000E2D2 # error = TRUE; /* needed for line feeds */
77: 74 0000E2D2 0d 01 efffffff6b movl $1,_error
78: 75 0000E2D9 # }
79: 76 0000E2D9 # } else
80: 77 0000E2D9 L389:
81: 78 0000E2D9 11 07 jbr L394
82: 79 0000E2DB L388:
83: 80 0000E2DB # test_undfl_inst(); /* test the instruction */
84: 81 0000E2DB fe 04 ef0000004c callf $4,_test_undfl_inst
85: 82 0000E2E2 L394:
86: 83 0000E2E2 # } else /* test all applicable op-codes */
87: 84 0000E2E2 11 45 jbr L396
88: 85 0000E2E4 L386:
89: 86 0000E2E4 # for(inst_index=0; inst_index < size_ovfl_tbl; inst_index++)
90: 87 0000E2E4 4d efffffff5a clrl _inst_index
91: 88 0000E2EA L399:
92: 89 0000E2EA 1d efffffff54 efffffff4f cmpl _inst_index,_size_ovfl_tbl
93: 90 0000E2F5 81 32 jgeq L398
94: 91 0000E2F7 # {
95: 92 0000E2F7 # data_ptr = ovfl_tbl[ inst_index ].undfl_data;
96: 93 0000E2F7 0d efffffff47 50 movl _inst_index,r0
97: 94 0000E2FE 48 05 50 50 shll $5,r0,r0
98: 95 0000E302 0d e000000018 efffffff37 movl _ovfl_tbl+24(r0),_data_ptr
99: 96 0000E30D # if( data_ptr != null_data )
100: 97 0000E30D 1d efffffff31 8f00000000 cmpl _data_ptr,$_null_data
101: 98 0000E318 31 07 jeql L400
102: 99 0000E31A # test_undfl_inst(); /* test the instruction */
103: 100 0000E31A fe 04 ef0000000d callf $4,_test_undfl_inst
104: 101 0000E321 # }
105: 102 0000E321 L400:
106: 103 0000E321 L397:
107: 104 0000E321 6d efffffff1d incl _inst_index
108: 105 0000E327 11 c1 jbr L399
109: 106 0000E329 L398:
110: 107 0000E329 L396:
111: 108 0000E329 # }
112: 109 0000E329 40 ret#2
113: 110 0000E32A .set L381,0x0
114: 111 0000E32A L383:
115: 112 0000E32A 13 ff1c jbr L384
116: 113 0000E32D .data
117: 114 000001ec * .text
118: 115 0000E32D 00 .align 1
119: 116 0000E32E .globl _test_undfl_inst
120: 117 0000E32E _test_undfl_inst:
121: 118 0000E32E 0000 .word L401
122: 119 0000E330 #
123: 120 0000E330 #
124: 121 0000E330 #
125: 122 0000E330 # /*
126: 123 0000E330 # ********************************************************************
127: 124 0000E330 # *
128: 125 0000E330 # * TEST THE UNDERFLOW EVENT ON AN INSTRUCTION
129: 126 0000E330 # *
130: 127 0000E330 # ********************************************************************
131: 128 0000E330 # */
132: 129 0000E330 # test_undfl_inst()
133: 130 0000E330 # {
134: 131 0000E330 13 00f9 jbr L403
135: 132 0000E333 L404:
136: 133 0000E333 # valid_test = TRUE; /* a test is being run */
137: 134 0000E333 0d 01 efffffff0a movl $1,_valid_test
138: 135 0000E33A # op_code = ovfl_tbl[ inst_index ].inst_code;
139: 136 0000E33A 0d efffffff04 50 movl _inst_index,r0
140: 137 0000E341 48 05 50 50 shll $5,r0,r0
141: 138 0000E345 0d e000000000 effffffef4 movl _ovfl_tbl(r0),_op_code
142: 139 0000E350 # op_name = ovfl_tbl[ inst_index ].name;
143: 140 0000E350 0d effffffeee 50 movl _inst_index,r0
144: 141 0000E357 48 05 50 50 shll $5,r0,r0
145: 142 0000E35B 0d e000000004 effffffede movl _ovfl_tbl+4(r0),_op_name
146: 143 0000E366 # no_ops = ovfl_tbl[ inst_index ].no_operands;
147: 144 0000E366 0d effffffed8 50 movl _inst_index,r0
148: 145 0000E36D 48 05 50 50 shll $5,r0,r0
149: 146 0000E371 0d e000000008 effffffec8 movl _ovfl_tbl+8(r0),_no_ops
150: 147 0000E37C # precision = ovfl_tbl[ inst_index ].precision;
151: 148 0000E37C 0d effffffec2 50 movl _inst_index,r0
152: 149 0000E383 48 05 50 50 shll $5,r0,r0
153: 150 0000E387 0d e00000000c effffffeb2 movl _ovfl_tbl+12(r0),_precision
154: 151 0000E392 # data_ptr = ovfl_tbl[ inst_index ].undfl_data;
155: 152 0000E392 0d effffffeac 50 movl _inst_index,r0
156: 153 0000E399 48 05 50 50 shll $5,r0,r0
157: 154 0000E39D 0d e000000018 effffffe9c movl _ovfl_tbl+24(r0),_data_ptr
158: 155 0000E3A8 # max_index = *ovfl_tbl[ inst_index ].undfl_cnt;
159: 156 0000E3A8 0d effffffe96 50 movl _inst_index,r0
160: 157 0000E3AF 48 05 50 50 shll $5,r0,r0
161: 158 0000E3B3 0d f00000001c effffffe86 movl *_ovfl_tbl+28(r0),_max_index
162: 159 0000E3BE # if( precision == SGL ) {
163: 160 0000E3BE 1d effffffe80 01 cmpl _precision,$1
164: 161 0000E3C5 21 10 jneq L405
165: 162 0000E3C7 # sgl_op = TRUE;
166: 163 0000E3C7 0d 01 effffffe76 movl $1,_sgl_op
167: 164 0000E3CE # acc_ld_size = SGL; /* use a sgl precision Acc. */
168: 165 0000E3CE 0d 01 effffffe6f movl $1,_acc_ld_size
169: 166 0000E3D5 # } else {
170: 167 0000E3D5 11 0d jbr L406
171: 168 0000E3D7 L405:
172: 169 0000E3D7 # sgl_op = FALSE;
173: 170 0000E3D7 4d effffffe67 clrl _sgl_op
174: 171 0000E3DD # acc_ld_size = DBL; /* use a dbl precision Acc. */
175: 172 0000E3DD 0d 02 effffffe60 movl $2,_acc_ld_size
176: 173 0000E3E4 # }
177: 174 0000E3E4 L406:
178: 175 0000E3E4 # if( (prt_hdrs) && (cycle == 1) )
179: 176 0000E3E4 5d effffffe5a tstl _prt_hdrs
180: 177 0000E3EA 31 16 jeql L407
181: 178 0000E3EC 1d effffffe52 01 cmpl _cycle,$1
182: 179 0000E3F3 21 0d jneq L407
183: 180 0000E3F5 # writes( op_name );
184: 181 0000E3F5 dd effffffe49 pushl _op_name
185: 182 0000E3FB fe 08 effffffe42 callf $8,_writes
186: 183 0000E402 # disable_mask = 0; /* all events enabled */
187: 184 0000E402 L407:
188: 185 0000E402 4b effffffe3c clrw _disable_mask
189: 186 0000E408 # evt_disabled = FALSE;
190: 187 0000E408 4d effffffe36 clrl _evt_disabled
191: 188 0000E40E # test_inst(); /* test the instruction */
192: 189 0000E40E fe 04 effffffe2f callf $4,_test_inst
193: 190 0000E415 # disable_mask = PSL_EN_UNDFL; /* disable underflows */
194: 191 0000E415 7f 8840 effffffe27 cvtlw $64,_disable_mask
195: 192 0000E41D # evt_disabled = TRUE;
196: 193 0000E41D 0d 01 effffffe20 movl $1,_evt_disabled
197: 194 0000E424 # test_inst(); /* test the instruction */
198: 195 0000E424 fe 04 effffffe19 callf $4,_test_inst
199: 196 0000E42B # }
200: 197 0000E42B 40 ret#2
201: 198 0000E42C .set L401,0x0
202: 199 0000E42C L403:
203: 200 0000E42C 13 ff04 jbr L404
204: 201 0000E42F .data
205: 201 0001C673 .data
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