![[BACK]](/cvsweb/icons/back.gif){kind=icon}
Return to ioboth.s CVS log ![[TXT]](/cvsweb/icons/text.gif){kind=icon}
![[DIR]](/cvsweb/icons/dir.gif){kind=icon}
Up to [Power 6/32 Unix Tahoe 4.2BSD] / cci / d / io|
Return to ioboth.s CVS log | Up to [Power 6/32 Unix Tahoe 4.2BSD] / cci / d / io |
1.1 root 1:
2: /* privileged registers constants (addresses) */
3:
4:
5:
6: .set SBR,0 /*system base register */
7: .set SLR,1 /*system length reg */
8: .set P0BR,2 /*p0 base reg */
9: .set P0LR,3 /*p0 length reg */
10: .set P1BR,4 /*p1 base reg */
11: .set P1LR,5 /*p1 length reg */
12: .set P2BR,6 /*p2 base reg */
13: .set P2LR,7 /*p2 length reg */
14: .set IPL,8 /*int priority level reg */
15: .set MME,9 /*memory mgmt enable reg */
16: .set TBIA,10 /*trans buf invalidate all */
17: /*entries */
18: .set TBIS,11 /*trans buf invalidate single */
19: /*entry */
20: .set DCK,12 /*data cache key */
21: .set CCK,13 /*code cache key */
22: .set PCBB,14 /*process control block base */
23: .set ISP,15 /*interrupt stack pointer */
24: .set SIRR,16 /*software int request reg */
25: .set SISR,17 /*software int summary reg */
26: .set SCBB,18 /*system control block base reg */
27: .set KSP,19 /*kernel stack pointer reg */
28: .set USP,20 /*user stack pointer */
29: .set P1CC,21 /*purge (invalidate) one page */
30: /*of code cache */
31: .set PACC,23 /*purge (invalidate) all pages */
32: /*of process in code cache */
33: .set P1DC,24 /*purge one page of data cache */
34: .set PADC,25 /*purge all the pages of */
35: /*process in data cache */
36: .set HISR,26 /* Hardware interrupt summary reg */
37:
38:
39:
40: .set PSL_C,0x00000001 /* carry bit */
41: .set PSL_V,0x00000002 /* overflow bit */
42: .set PSL_Z,0x00000004 /* zero bit */
43: .set Z,0x00000004
44: .set PSL_N,0x00000008 /* negative bit */
45: .set PSL_T,0x00000010 /* trace enable bit */
46: .set PSL_I,0x00000020 /* integer overflow enable bit */
47: .set PSL_IPL,0x001f0000 /* interrupt priority level */
48: .set PSL_MOD,0x01000000 /* mode = 1 means user*/
49: .set PSL_IS,0x04000000 /* interrupt stack */
50: .set PSL_TP,0x40000000 /* trace pending */
51:
52: .set PG_V,0x80000000
53: .set PG_PROT,0x78000000
54: .set PG_M,0x04000000
55: .set PG_USED,0x02000000
56: .set PG_NC,0x01000000
57: .set PG_PFNUM,0x003fffff
58:
59: .set PG_NOACC,0
60: .set PG_KR,0x40000000
61: .set PG_KW,0x60000000
62: .set PG_URKR,0x50000000
63: .set PG_URKW,0x70000000
64: .set PG_UW,0x78000000
65:
66: /* PCB offsets & diagnostic extension to pcb */
67:
68:
69: .set PCB_KSP, 0
70: .set PCB_USP, 4
71: .set PCB_R0, 8
72: .set PCB_R1, 12
73: .set PCB_R2, 16
74: .set PCB_R3, 20
75: .set PCB_R4, 24
76: .set PCB_R5, 28
77: .set PCB_R6, 32
78: .set PCB_R7, 36
79: .set PCB_R8, 40
80: .set PCB_R9, 44
81: .set PCB_R10, 48
82: .set PCB_R11, 52
83: .set PCB_R12, 56
84: .set PCB_R13, 60
85: .set PCB_PC, 64
86: .set PCB_PSL, 68
87: .set PCB_P0BR, 72
88: .set PCB_P0LR, 76
89: .set PCB_P1BR, 80
90: .set PCB_P1LR, 84
91: .set PCB_P2BR, 88
92: .set PCB_P2LR, 92
93: .set PCB_STAT, 96 /*process status,statistics,id,etc*/
94:
95:
96:
97: /* fundamental constants */
98:
99:
100: .set NBPG,1024
101: .set PGOFSET,(NBPG-1) /* byte offset into page */
102: .set PGSHIFT,10 /* LOG2(NBPG) */
103: .set HIGH,0x1f
104: .set PAGE,1024
105:
106:
107: /* SCB offsets */
108:
109: .set PFVEC,4 /*power fail */
110: .set CLOCKVEC,28 /*hard clock vector */
111: .set CRVEC,40 /*console receive */
112: .set CXVEC,44 /*console transmit */
113: .set SIVEC1,120 /*software int vec #1 */
114: /*for 2,3,..15, sub 4,8,.. 56 */
115: /*from SIVEC1 */
116: .set BEVEC,128 /*bus error */
117: .set SYSVEC,172 /*system call (kcall) */
118: .set PINSTVEC,176 /*privileged instruction fault */
119: .set ROVEC,180 /*reserved operand fault */
120: .set RAVEC,184 /*reserved addressing fault */
121: .set PROTVEC,188 /*access control violation */
122: .set TRANSVEC,192 /*translation fault vector */
123: .set KSPVEC,196 /*kernel stack not valid vector */
124: .set TRACEVEC,200 /*trace vector */
125: .set BPTVEC,204 /*break point fault */
126: .set ARITHVEC,208 /*arithmetic trap */
127: .set ALIGNVEC,212 /*alignment vector */
128: .set IO14VEC,256 /*io vector, ipl #14 */
129: .set IO15VEC,320 /*io vector, ipl #15 */
130: .set IO16VEC,384 /*io vector, ipl #16 */
131: .set IO17VEC,448 /*io vector, ipl #17 */
132:
133: /* SPT (system page table) offsets */
134:
135: .set SCBPTE,8 /*system control block pte offset*/
136: .set BUFPTE,12 /*buffer pte offset */
137: .set ISPTE,16 /*interrupt stack page 0 */
138: .set IS1PTE,20 /*interrupt stack page 1 */
139: .set SPTPTE,20 /*system page table page 1 */
140: .set SPT1PTE,20 /*system page table page 2 */
141: .set IOMAPPTE,24 /*io map */
142: .set PCBPTE,28 /*process control blocks pte */
143: .set U0P0PTE,32 /*U0 p0pt pte */
144: .set U0P1PTE,36 /*U0 p1pt pte */
145: .set U0P2PTE,40 /*U0 p2pt pte */
146: .set U1P0PTE,44
147: .set U1P1PTE,48
148: .set U1P2PTE,52
149: .set U2P0PTE,56
150: .set U2P1PTE,60
151: .set U2P2PTE,64
152: .set U3P0PTE,68
153: .set U3P1PTE,72
154: .set U3P2PTE,76
155: .set U4P0PTE,80
156: .set U4P1PTE,84
157: .set U4P2PTE,88
158: .set U5P0PTE,92
159: .set U5P1PTE,96
160: .set U5P2PTE,100
161: .set U6P0PTE,104
162: .set U6P1PTE,108
163: .set U6P2PTE,112
164: .set U7P0PTE,116 /*U7 p0pt pte */
165: .set U7P1PTE,120 /*U7 p1pt pte */
166: .set U7P2PTE,124 /*U7 p2pt pte */
167: .set IOB0PTE,128 /*io buffer 0 pte */
168: .set IOB1PTE,132
169: .set IOB2PTE,136
170: .set IOB3PTE,140
171: .set IOB4PTE,144
172: .set IOB5PTE,148
173: .set IOB6PTE,152
174: .set IOB7PTE,156 /*io buffer 7 pte */
175:
176:
177: /* trap.h 4.6 81/03/03 */
178:
179:
180: .set RESADFLT,0 /* reserved addressing fault */
181: .set PRIVINFLT,1 /* privileged instruction fault */
182: .set RESOPFLT,2 /* reserved operand fault */
183: .set BPTFLT,3 /* bpt instruction fault */
184: .set ALIGNFLT,4 /* alignment fault */
185: .set SYSCALL,5 /* kcall instruction (syscall trap) */
186: .set ARITHTRAP,6 /* arithmetic trap */
187: .set PROTFLT,7 /* protection fault */
188: .set TRCTRAP,8 /* trace trap */
189: .set TRANSFLT,9 /* translation not valid fault */
190: .set DONE,255
191: .set CPMDCB,21
192: .set PDCS,28
193: .set ISTK,0x10000
194: .globl _ioboth
195: .set SYSP,0x20000
196: .set SSP,0x30000
197: .set CPCONS,0x01
198: .set CPWRITE,0x01
199: .set CLOCKVEC,28 /*hard clock vector */
200: .set RRVEC,48 /*remote receive */
201: .set RXVEC,52 /*remote transmit */
202: .set CPRMTE,0x02
203: .set CPWRITE,0x01
204: .set CPREAD,0x02
205: .set RDONE,0x4000
206: .set TIME,0x0fffffff
207: .set BFSZ,0x01
208: .set A,0x41
209: .set a,0x61
210: .set Z,0x5a
211: .set z,0x7a
212:
213:
214: /* Local and Remote console output test */
215:
216:
217: _ioboth:movl $0x00,r1
218: movab bitbl,r0
219: lvec: movl r0,_scb [r1]
220: addl2 $4,r0
221: addl2 $1,r1
222: cmpl $0xff,r1
223: jneq lvec
224: movb $A,ucase /* load starting value of upper case */
225: movb $a,lcase /* load starting value of lower case */
226: mtpr $_scb,$SCBB /* initialize SCBB */
227: movl $SSP,sp /* initialize system stack pointer */
228: movab liint,_scb + CRVEC /* addr rx interrupt routine */
229: movab loint,_scb + CXVEC /* addr tx interrupt routine */
230: movab riint,_scb + RRVEC /* addr rrx interrupt routine */
231: movab roint,_scb + RXVEC /* addr rtx interrupt routine */
232: movab clkint,_scb + CLOCKVEC
233:
234: movab LIDCB,r7
235: movb $CPCONS,0(r7) /* set up CPDCB for console */
236: movb $CPREAD,1(r7)
237: movw $BFSZ,2(r7)
238: movb $0,4(r7)
239: mtpr r7,$CPMDCB /* send read interrupt to cp */
240: ili: mtpr r7,$PDCS
241: movw 0(r7),r8 /* read CP command word */
242: andw2 $RDONE,r8 /* check buffer read is done */
243: jeql ili /* not done check again */
244: movab RIDCB,r7
245: movb $CPRMTE,0(r7) /* set up CPDCB for remote */
246: movb $CPREAD,1(r7)
247: movw $BFSZ,2(r7)
248: movb $0,4(r7)
249: mtpr r7,$CPMDCB /* send read interrupt to cp */
250: iri: mtpr r7,$PDCS
251: movw 0(r7),r8 /* read CP command word */
252: andw2 $RDONE,r8 /* check buffer read is done */
253: jeql iri /* not done check again */
254: movab LODCB,r7
255: movb $CPCONS,0(r7) /* set up CPDCB for console */
256: movb $CPWRITE,1(r7)
257: movw $BFSZ,2(r7)
258: movb ucase,4(r7) /* load upper case character to xmit */
259: mtpr r7,$CPMDCB /* send xmit interrupt to cp */
260: ilo: mtpr r7,$PDCS
261: movw 0(r7),r8 /* read CP command word */
262: andw2 $RDONE,r8 /* check buffer read is done */
263: jeql ilo /* not done check again */
264: movab RODCB,r7
265: movb $CPRMTE,0(r7) /* set up CPDCB for remote */
266: movb $CPWRITE,1(r7)
267: movw $BFSZ,2(r7)
268: movb lcase,4(r7) /* load lower case character to xmit */
269: mtpr r7,$CPMDCB /* send xmit interrupt to cp */
270: iro: mtpr r7,$PDCS
271: movw 0(r7),r8 /* read CP command word */
272: andw2 $RDONE,r8 /* check buffer read is done */
273: jeql iro /* not done check again */
274:
275: clrl r6
276: loop: tstl r6
277: jneq loopc
278: movl $0x1f,r6
279: loopc: mtpr r6,$IPL /* lower ipl to allow all interrupts */
280: decl r6
281: jmp loop /* jump self to transmit characters */
282: tdone: movl $0xCAFEBABE,r0 /* good test */
283: halt
284:
285: liint: mfpr $CPMDCB,r5
286: mtpr r5,$PDCS
287: movw (r5),r4 /* read CP command word */
288: andw2 $RDONE,r4 /* check buffer read is done */
289: jeql liint /* not done check again */
290: movab LIDCB,r5
291: movb $CPCONS,(r5) /* set up CPDCB for console */
292: movb $CPREAD,1(r5)
293: movab 4(r5),r4
294: mtpr r4,$PDCS
295: movb 4(r5),ucase
296: movb $0,4(r5)
297: movb ucase,r4 /* get character read */
298: andl2 $127,r4 /* mask parity */
299: cmpl $4,r4 /* check for control d */
300: jeql tdone /* yes--all done */
301: mtpr r5,$CPMDCB /* send read interrupt to cp */
302: liret: rei
303:
304: loint: mfpr $CPMDCB,r5
305: mtpr r5,$PDCS
306: movw (r5),r4 /* read CP command word */
307: andw2 $RDONE,r4 /* check buffer read is done */
308: jeql loint /* not done check again */
309: movab LODCB,r5
310: movb $CPCONS,(r5) /* set up dcb for console */
311: movb ucase,4(r5) /* load character to xmit */
312: mtpr r5,$CPMDCB /* issue " go " command */
313: loret: rei
314:
315: riint: mfpr $CPMDCB,r5
316: mtpr r5,$PDCS
317: movw (r5),r4 /* read CP command word */
318: andw2 $RDONE,r4 /* check buffer read is done */
319: jeql riint /* not done check again */
320: movab RIDCB,r5
321: movb $CPRMTE,(r5) /* set up CPDCB for remote */
322: movb $CPREAD,1(r5)
323: movab 4(r5),r4
324: mtpr r4,$PDCS
325: movb 4(r5),lcase
326: movb $0,4(r5)
327: mtpr r5,$CPMDCB /* send read interrupt to cp */
328: movl lcase,r4 /* get character read */
329: andl2 $127,r4 /* mask parity */
330: cmpl $4,r4 /* check for control d */
331: jeql tdone /* yes--all done */
332: riret: rei
333:
334: roint: mfpr $CPMDCB,r5
335: mtpr r5,$PDCS
336: movw (r5),r4 /* read CP command word */
337: andw2 $RDONE,r4 /* check buffer read is done */
338: jeql roint /* not done check again */
339: movab RODCB,r5
340: movb $CPRMTE,(r5) /* set up dcb for console */
341: movb lcase,4(r5) /* load character to xmit */
342: mtpr r5,$CPMDCB /* issue " go " command */
343: roret: rei
344:
345: clkint: rei /* dummy routine to handle clock int */
346: .data
347: _scb:
348: .space 1024
349:
350: bitbl:
351: .space 1024
352:
353: .align 2
354: LIDCB:
355: .space 20
356:
357: .align 2
358: LODCB:
359: .space 20
360:
361: .align 2
362: RIDCB:
363: .space 20
364:
365: .align 2
366: RODCB:
367: .space 20
368:
369: .align 2
370:
371: ucase: .space 4
372:
373: lcase: .space 4
This archive runs on limited infrastructure. Preserving old code on modern bandwidth. Automated agents are requested to crawl responsibly.