cci/d/io/ioboth.s - view

File: [Power 6/32 Unix Tahoe 4.2BSD] / cci / d / io / ioboth.s
Revision 1.1.1.1 (vendor branch): download - view: text, annotated - select for diffs
Sun Jul 28 12:24:19 2019 UTC (7 years ago) by root
Branches: bsd, MAIN
CVS tags: v12b, v121, HEAD

Power 6/32 Unix version 1.2b

/* privileged registers constants (addresses) */ .set SBR,0 /*system base register */ .set SLR,1 /*system length reg */ .set P0BR,2 /*p0 base reg */ .set P0LR,3 /*p0 length reg */ .set P1BR,4 /*p1 base reg */ .set P1LR,5 /*p1 length reg */ .set P2BR,6 /*p2 base reg */ .set P2LR,7 /*p2 length reg */ .set IPL,8 /*int priority level reg */ .set MME,9 /*memory mgmt enable reg */ .set TBIA,10 /*trans buf invalidate all */ /*entries */ .set TBIS,11 /*trans buf invalidate single */ /*entry */ .set DCK,12 /*data cache key */ .set CCK,13 /*code cache key */ .set PCBB,14 /*process control block base */ .set ISP,15 /*interrupt stack pointer */ .set SIRR,16 /*software int request reg */ .set SISR,17 /*software int summary reg */ .set SCBB,18 /*system control block base reg */ .set KSP,19 /*kernel stack pointer reg */ .set USP,20 /*user stack pointer */ .set P1CC,21 /*purge (invalidate) one page */ /*of code cache */ .set PACC,23 /*purge (invalidate) all pages */ /*of process in code cache */ .set P1DC,24 /*purge one page of data cache */ .set PADC,25 /*purge all the pages of */ /*process in data cache */ .set HISR,26 /* Hardware interrupt summary reg */ .set PSL_C,0x00000001 /* carry bit */ .set PSL_V,0x00000002 /* overflow bit */ .set PSL_Z,0x00000004 /* zero bit */ .set Z,0x00000004 .set PSL_N,0x00000008 /* negative bit */ .set PSL_T,0x00000010 /* trace enable bit */ .set PSL_I,0x00000020 /* integer overflow enable bit */ .set PSL_IPL,0x001f0000 /* interrupt priority level */ .set PSL_MOD,0x01000000 /* mode = 1 means user*/ .set PSL_IS,0x04000000 /* interrupt stack */ .set PSL_TP,0x40000000 /* trace pending */ .set PG_V,0x80000000 .set PG_PROT,0x78000000 .set PG_M,0x04000000 .set PG_USED,0x02000000 .set PG_NC,0x01000000 .set PG_PFNUM,0x003fffff .set PG_NOACC,0 .set PG_KR,0x40000000 .set PG_KW,0x60000000 .set PG_URKR,0x50000000 .set PG_URKW,0x70000000 .set PG_UW,0x78000000 /* PCB offsets & diagnostic extension to pcb */ .set PCB_KSP, 0 .set PCB_USP, 4 .set PCB_R0, 8 .set PCB_R1, 12 .set PCB_R2, 16 .set PCB_R3, 20 .set PCB_R4, 24 .set PCB_R5, 28 .set PCB_R6, 32 .set PCB_R7, 36 .set PCB_R8, 40 .set PCB_R9, 44 .set PCB_R10, 48 .set PCB_R11, 52 .set PCB_R12, 56 .set PCB_R13, 60 .set PCB_PC, 64 .set PCB_PSL, 68 .set PCB_P0BR, 72 .set PCB_P0LR, 76 .set PCB_P1BR, 80 .set PCB_P1LR, 84 .set PCB_P2BR, 88 .set PCB_P2LR, 92 .set PCB_STAT, 96 /*process status,statistics,id,etc*/ /* fundamental constants */ .set NBPG,1024 .set PGOFSET,(NBPG-1) /* byte offset into page */ .set PGSHIFT,10 /* LOG2(NBPG) */ .set HIGH,0x1f .set PAGE,1024 /* SCB offsets */ .set PFVEC,4 /*power fail */ .set CLOCKVEC,28 /*hard clock vector */ .set CRVEC,40 /*console receive */ .set CXVEC,44 /*console transmit */ .set SIVEC1,120 /*software int vec #1 */ /*for 2,3,..15, sub 4,8,.. 56 */ /*from SIVEC1 */ .set BEVEC,128 /*bus error */ .set SYSVEC,172 /*system call (kcall) */ .set PINSTVEC,176 /*privileged instruction fault */ .set ROVEC,180 /*reserved operand fault */ .set RAVEC,184 /*reserved addressing fault */ .set PROTVEC,188 /*access control violation */ .set TRANSVEC,192 /*translation fault vector */ .set KSPVEC,196 /*kernel stack not valid vector */ .set TRACEVEC,200 /*trace vector */ .set BPTVEC,204 /*break point fault */ .set ARITHVEC,208 /*arithmetic trap */ .set ALIGNVEC,212 /*alignment vector */ .set IO14VEC,256 /*io vector, ipl #14 */ .set IO15VEC,320 /*io vector, ipl #15 */ .set IO16VEC,384 /*io vector, ipl #16 */ .set IO17VEC,448 /*io vector, ipl #17 */ /* SPT (system page table) offsets */ .set SCBPTE,8 /*system control block pte offset*/ .set BUFPTE,12 /*buffer pte offset */ .set ISPTE,16 /*interrupt stack page 0 */ .set IS1PTE,20 /*interrupt stack page 1 */ .set SPTPTE,20 /*system page table page 1 */ .set SPT1PTE,20 /*system page table page 2 */ .set IOMAPPTE,24 /*io map */ .set PCBPTE,28 /*process control blocks pte */ .set U0P0PTE,32 /*U0 p0pt pte */ .set U0P1PTE,36 /*U0 p1pt pte */ .set U0P2PTE,40 /*U0 p2pt pte */ .set U1P0PTE,44 .set U1P1PTE,48 .set U1P2PTE,52 .set U2P0PTE,56 .set U2P1PTE,60 .set U2P2PTE,64 .set U3P0PTE,68 .set U3P1PTE,72 .set U3P2PTE,76 .set U4P0PTE,80 .set U4P1PTE,84 .set U4P2PTE,88 .set U5P0PTE,92 .set U5P1PTE,96 .set U5P2PTE,100 .set U6P0PTE,104 .set U6P1PTE,108 .set U6P2PTE,112 .set U7P0PTE,116 /*U7 p0pt pte */ .set U7P1PTE,120 /*U7 p1pt pte */ .set U7P2PTE,124 /*U7 p2pt pte */ .set IOB0PTE,128 /*io buffer 0 pte */ .set IOB1PTE,132 .set IOB2PTE,136 .set IOB3PTE,140 .set IOB4PTE,144 .set IOB5PTE,148 .set IOB6PTE,152 .set IOB7PTE,156 /*io buffer 7 pte */ /* trap.h 4.6 81/03/03 */ .set RESADFLT,0 /* reserved addressing fault */ .set PRIVINFLT,1 /* privileged instruction fault */ .set RESOPFLT,2 /* reserved operand fault */ .set BPTFLT,3 /* bpt instruction fault */ .set ALIGNFLT,4 /* alignment fault */ .set SYSCALL,5 /* kcall instruction (syscall trap) */ .set ARITHTRAP,6 /* arithmetic trap */ .set PROTFLT,7 /* protection fault */ .set TRCTRAP,8 /* trace trap */ .set TRANSFLT,9 /* translation not valid fault */ .set DONE,255 .set CPMDCB,21 .set PDCS,28 .set ISTK,0x10000 .globl _ioboth .set SYSP,0x20000 .set SSP,0x30000 .set CPCONS,0x01 .set CPWRITE,0x01 .set CLOCKVEC,28 /*hard clock vector */ .set RRVEC,48 /*remote receive */ .set RXVEC,52 /*remote transmit */ .set CPRMTE,0x02 .set CPWRITE,0x01 .set CPREAD,0x02 .set RDONE,0x4000 .set TIME,0x0fffffff .set BFSZ,0x01 .set A,0x41 .set a,0x61 .set Z,0x5a .set z,0x7a /* Local and Remote console output test */ _ioboth:movl $0x00,r1 movab bitbl,r0 lvec: movl r0,_scb [r1] addl2 $4,r0 addl2 $1,r1 cmpl $0xff,r1 jneq lvec movb $A,ucase /* load starting value of upper case */ movb $a,lcase /* load starting value of lower case */ mtpr $_scb,$SCBB /* initialize SCBB */ movl $SSP,sp /* initialize system stack pointer */ movab liint,_scb + CRVEC /* addr rx interrupt routine */ movab loint,_scb + CXVEC /* addr tx interrupt routine */ movab riint,_scb + RRVEC /* addr rrx interrupt routine */ movab roint,_scb + RXVEC /* addr rtx interrupt routine */ movab clkint,_scb + CLOCKVEC movab LIDCB,r7 movb $CPCONS,0(r7) /* set up CPDCB for console */ movb $CPREAD,1(r7) movw $BFSZ,2(r7) movb $0,4(r7) mtpr r7,$CPMDCB /* send read interrupt to cp */ ili: mtpr r7,$PDCS movw 0(r7),r8 /* read CP command word */ andw2 $RDONE,r8 /* check buffer read is done */ jeql ili /* not done check again */ movab RIDCB,r7 movb $CPRMTE,0(r7) /* set up CPDCB for remote */ movb $CPREAD,1(r7) movw $BFSZ,2(r7) movb $0,4(r7) mtpr r7,$CPMDCB /* send read interrupt to cp */ iri: mtpr r7,$PDCS movw 0(r7),r8 /* read CP command word */ andw2 $RDONE,r8 /* check buffer read is done */ jeql iri /* not done check again */ movab LODCB,r7 movb $CPCONS,0(r7) /* set up CPDCB for console */ movb $CPWRITE,1(r7) movw $BFSZ,2(r7) movb ucase,4(r7) /* load upper case character to xmit */ mtpr r7,$CPMDCB /* send xmit interrupt to cp */ ilo: mtpr r7,$PDCS movw 0(r7),r8 /* read CP command word */ andw2 $RDONE,r8 /* check buffer read is done */ jeql ilo /* not done check again */ movab RODCB,r7 movb $CPRMTE,0(r7) /* set up CPDCB for remote */ movb $CPWRITE,1(r7) movw $BFSZ,2(r7) movb lcase,4(r7) /* load lower case character to xmit */ mtpr r7,$CPMDCB /* send xmit interrupt to cp */ iro: mtpr r7,$PDCS movw 0(r7),r8 /* read CP command word */ andw2 $RDONE,r8 /* check buffer read is done */ jeql iro /* not done check again */ clrl r6 loop: tstl r6 jneq loopc movl $0x1f,r6 loopc: mtpr r6,$IPL /* lower ipl to allow all interrupts */ decl r6 jmp loop /* jump self to transmit characters */ tdone: movl $0xCAFEBABE,r0 /* good test */ halt liint: mfpr $CPMDCB,r5 mtpr r5,$PDCS movw (r5),r4 /* read CP command word */ andw2 $RDONE,r4 /* check buffer read is done */ jeql liint /* not done check again */ movab LIDCB,r5 movb $CPCONS,(r5) /* set up CPDCB for console */ movb $CPREAD,1(r5) movab 4(r5),r4 mtpr r4,$PDCS movb 4(r5),ucase movb $0,4(r5) movb ucase,r4 /* get character read */ andl2 $127,r4 /* mask parity */ cmpl $4,r4 /* check for control d */ jeql tdone /* yes--all done */ mtpr r5,$CPMDCB /* send read interrupt to cp */ liret: rei loint: mfpr $CPMDCB,r5 mtpr r5,$PDCS movw (r5),r4 /* read CP command word */ andw2 $RDONE,r4 /* check buffer read is done */ jeql loint /* not done check again */ movab LODCB,r5 movb $CPCONS,(r5) /* set up dcb for console */ movb ucase,4(r5) /* load character to xmit */ mtpr r5,$CPMDCB /* issue " go " command */ loret: rei riint: mfpr $CPMDCB,r5 mtpr r5,$PDCS movw (r5),r4 /* read CP command word */ andw2 $RDONE,r4 /* check buffer read is done */ jeql riint /* not done check again */ movab RIDCB,r5 movb $CPRMTE,(r5) /* set up CPDCB for remote */ movb $CPREAD,1(r5) movab 4(r5),r4 mtpr r4,$PDCS movb 4(r5),lcase movb $0,4(r5) mtpr r5,$CPMDCB /* send read interrupt to cp */ movl lcase,r4 /* get character read */ andl2 $127,r4 /* mask parity */ cmpl $4,r4 /* check for control d */ jeql tdone /* yes--all done */ riret: rei roint: mfpr $CPMDCB,r5 mtpr r5,$PDCS movw (r5),r4 /* read CP command word */ andw2 $RDONE,r4 /* check buffer read is done */ jeql roint /* not done check again */ movab RODCB,r5 movb $CPRMTE,(r5) /* set up dcb for console */ movb lcase,4(r5) /* load character to xmit */ mtpr r5,$CPMDCB /* issue " go " command */ roret: rei clkint: rei /* dummy routine to handle clock int */ .data _scb: .space 1024 bitbl: .space 1024 .align 2 LIDCB: .space 20 .align 2 LODCB: .space 20 .align 2 RIDCB: .space 20 .align 2 RODCB: .space 20 .align 2 ucase: .space 4 lcase: .space 4

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