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1.1 root 1:
2: /* privileged registers constants (addresses) */
3:
4:
5:
6: .set SBR,0 /*system base register */
7: .set SLR,1 /*system length reg */
8: .set P0BR,2 /*p0 base reg */
9: .set P0LR,3 /*p0 length reg */
10: .set P1BR,4 /*p1 base reg */
11: .set P1LR,5 /*p1 length reg */
12: .set P2BR,6 /*p2 base reg */
13: .set P2LR,7 /*p2 length reg */
14: .set IPL,8 /*int priority level reg */
15: .set MME,9 /*memory mgmt enable reg */
16: .set TBIA,10 /*trans buf invalidate all */
17: /*entries */
18: .set TBIS,11 /*trans buf invalidate single */
19: /*entry */
20: .set DCK,12 /*data cache key */
21: .set CCK,13 /*code cache key */
22: .set PCBB,14 /*process control block base */
23: .set ISP,15 /*interrupt stack pointer */
24: .set PSL,22 /* program status longword */
25: .set SIRR,16 /*software int request reg */
26: .set SISR,17 /*software int summary reg */
27: .set SCBB,18 /*system control block base reg */
28: .set KSP,19 /*kernel stack pointer reg */
29: .set USP,20 /*user stack pointer */
30: .set P1CC,21 /*purge (invalidate) one page */
31: /*of code cache */
32: .set PACC,23 /*purge (invalidate) all pages */
33: /*of process in code cache */
34: .set P1DC,24 /*purge one page of data cache */
35: .set PADC,25 /*purge all the pages of */
36: /*process in data cache */
37: .set HISR,26 /* Hardware interrupt summary reg */
38:
39:
40:
41: .set PSL_C,0x00000001 /* carry bit */
42: .set PSL_V,0x00000002 /* overflow bit */
43: .set PSL_Z,0x00000004 /* zero bit */
44: .set Z,0x00000004
45: .set PSL_N,0x00000008 /* negative bit */
46: .set PSL_T,0x00000010 /* trace enable bit */
47: .set PSL_I,0x00000020 /* integer overflow enable bit */
48: .set PSL_IPL,0x001f0000 /* interrupt priority level */
49: .set PSL_MOD,0x01000000 /* mode = 1 means user*/
50: .set PSL_IS,0x04000000 /* interrupt stack */
51: .set PSL_TP,0x40000000 /* trace pending */
52:
53: .set PG_V,0x80000000
54: .set PG_PROT,0x78000000
55: .set PG_M,0x04000000
56: .set PG_USED,0x02000000
57: .set PG_NC,0x01000000
58: .set PG_PFNUM,0x003fffff
59:
60: .set PG_NOACC,0
61: .set PG_KR,0x40000000
62: .set PG_KW,0x60000000
63: .set PG_URKR,0x50000000
64: .set PG_URKW,0x70000000
65: .set PG_UW,0x78000000
66:
67: /* PCB offsets & diagnostic extension to pcb */
68:
69:
70: .set PCB_KSP, 0
71: .set PCB_USP, 4
72: .set PCB_R0, 8
73: .set PCB_R1, 12
74: .set PCB_R2, 16
75: .set PCB_R3, 20
76: .set PCB_R4, 24
77: .set PCB_R5, 28
78: .set PCB_R6, 32
79: .set PCB_R7, 36
80: .set PCB_R8, 40
81: .set PCB_R9, 44
82: .set PCB_R10, 48
83: .set PCB_R11, 52
84: .set PCB_R12, 56
85: .set PCB_R13, 60
86: .set PCB_PC, 64
87: .set PCB_PSL, 68
88: .set PCB_P0BR, 72
89: .set PCB_P0LR, 76
90: .set PCB_P1BR, 80
91: .set PCB_P1LR, 84
92: .set PCB_P2BR, 88
93: .set PCB_P2LR, 92
94: .set PCB_STAT, 96 /*process status,statistics,id,etc*/
95:
96:
97:
98: /* fundamental constants */
99:
100:
101: .set NBPG,1024
102: .set PGOFSET,(NBPG-1) /* byte offset into page */
103: .set PGSHIFT,10 /* LOG2(NBPG) */
104: .set HIGH,0x1f
105: .set PAGE,1024
106:
107:
108: /* SCB offsets */
109:
110: .set PFVEC,4 /*power fail */
111: .set CLOCKVEC,28 /*hard clock vector */
112: .set CRVEC,40 /*console receive */
113: .set CXVEC,44 /*console transmit */
114: .set SIVEC1,120 /*software int vec #1 */
115: /*for 2,3,..15, sub 4,8,.. 56 */
116: /*from SIVEC1 */
117: .set BEVEC,128 /*bus error */
118: .set SYSVEC,172 /*system call (kcall) */
119: .set PINSTVEC,176 /*privileged instruction fault */
120: .set ROVEC,180 /*reserved operand fault */
121: .set RAVEC,184 /*reserved addressing fault */
122: .set PROTVEC,188 /*access control violation */
123: .set TRANSVEC,192 /*translation fault vector */
124: .set KSPVEC,196 /*kernel stack not valid vector */
125: .set TRACEVEC,200 /*trace vector */
126: .set BPTVEC,204 /*break point fault */
127: .set ARITHVEC,208 /*arithmetic trap */
128: .set ALIGNVEC,212 /*alignment vector */
129: .set IO14VEC,256 /*io vector, ipl #14 */
130: .set IO15VEC,320 /*io vector, ipl #15 */
131: .set IO16VEC,384 /*io vector, ipl #16 */
132: .set IO17VEC,448 /*io vector, ipl #17 */
133:
134: /* SPT (system page table) offsets */
135:
136: .set SCBPTE,8 /*system control block pte offset*/
137: .set BUFPTE,12 /*buffer pte offset */
138: .set ISPTE,16 /*interrupt stack page 0 */
139: .set IS1PTE,20 /*interrupt stack page 1 */
140: .set SPTPTE,20 /*system page table page 1 */
141: .set SPT1PTE,20 /*system page table page 2 */
142: .set IOMAPPTE,24 /*io map */
143: .set PCBPTE,28 /*process control blocks pte */
144: .set U0P0PTE,32 /*U0 p0pt pte */
145: .set U0P1PTE,36 /*U0 p1pt pte */
146: .set U0P2PTE,40 /*U0 p2pt pte */
147: .set U1P0PTE,44
148: .set U1P1PTE,48
149: .set U1P2PTE,52
150: .set U2P0PTE,56
151: .set U2P1PTE,60
152: .set U2P2PTE,64
153: .set U3P0PTE,68
154: .set U3P1PTE,72
155: .set U3P2PTE,76
156: .set U4P0PTE,80
157: .set U4P1PTE,84
158: .set U4P2PTE,88
159: .set U5P0PTE,92
160: .set U5P1PTE,96
161: .set U5P2PTE,100
162: .set U6P0PTE,104
163: .set U6P1PTE,108
164: .set U6P2PTE,112
165: .set U7P0PTE,116 /*U7 p0pt pte */
166: .set U7P1PTE,120 /*U7 p1pt pte */
167: .set U7P2PTE,124 /*U7 p2pt pte */
168: .set IOB0PTE,128 /*io buffer 0 pte */
169: .set IOB1PTE,132
170: .set IOB2PTE,136
171: .set IOB3PTE,140
172: .set IOB4PTE,144
173: .set IOB5PTE,148
174: .set IOB6PTE,152
175: .set IOB7PTE,156 /*io buffer 7 pte */
176:
177:
178: /* trap.h 4.6 81/03/03 */
179:
180:
181: .set RESADFLT,0 /* reserved addressing fault */
182: .set PRIVINFLT,1 /* privileged instruction fault */
183: .set RESOPFLT,2 /* reserved operand fault */
184: .set BPTFLT,3 /* bpt instruction fault */
185: .set ALIGNFLT,4 /* alignment fault */
186: .set SYSCALL,5 /* kcall instruction (syscall trap) */
187: .set ARITHTRAP,6 /* arithmetic trap */
188: .set PROTFLT,7 /* protection fault */
189: .set TRCTRAP,8 /* trace trap */
190: .set TRANSFLT,9 /* translation not valid fault */
191: .set DONE,255
192: .set CPMDCB,21
193: .set ISTK,0x10000
194: .globl _rtclk
195: .set SYSP,0x20000
196: .set SSP,0x30000
197: .set CPCONS,0x01
198: .set CPWRITE,0x01
199: .set CPREAD,0x02
200: .set INTMR,0x04
201: .set BFSZ,0x02
202: .set CNT,0xfffffff
203: .set CLKCNT,0x05020
204:
205:
206: /* Console interval timer test */
207:
208:
209: _rtclk: movl $0x00,r1
210: movab bitbl,r0
211: lvec: movl r0,_scb[r1]
212: movl r1,bitbl[r1]
213: addl2 $4,r0
214: addl2 $1,r1
215: cmpl $0xff,r1
216: jneq lvec
217: movl $60,msgcnt /* load message count of sixty */
218: movl $0,tikcnt /* clear tick counter */
219: mtpr $0,$PSL /* setup for user stack */
220: mtpr $_scb,$SCBB /* initialize SCBB */
221: mtpr $ISTK,$ISP /* initialize interrupt stack pointer */
222: movl $ISTK,sp /* initialize s ystem stack pointer */
223: movab bdint,_scb + CLOCKVEC /* trap for unexpected interrupt */
224: mtpr $0x18,$IPL /* lower the ipl allow random interrupts */
225: movb $INTMR,CPDCB /* set up cpdcb to program interval timer */
226: movb $CPWRITE,CPDCB + 1
227: movw $CLKCNT,CPDCB + 2
228: movl $CNT,r2 /* load count value for timeout */
229: movl $CPDCB,r10 /* load address of device control block */
230: andl2 $0xffffff,r10 /* mask off garbage */
231: movab gdint,_scb + CLOCKVEC /* address of good interrupt handler */
232: movab txvec,_scb + CXVEC /* handle transmit interrupts */
233: mtpr r10,$CPMDCB /* send xmit interrupt to cp */
234: mtpr $0x17,$IPL /* lower the ipl allow clock interrupts */
235: loop: cmpl $30,tikcnt /* check its time to transmit mesg */
236: jgtr loop2 /* not ready continue */
237: mtpr $0x18,$IPL /* do not allow ticks during transmit */
238: cmpl $60,msgcnt
239: jneq nfirst /* skip if not the first message */
240: pushab nl /* start on a new line */
241: callf $8,_writes /* call print function */
242: nfirst: andl3 $1,msgcnt,r0 /* check for tick or tock */
243: jneq ptock /* generate tock */
244: pushab tick
245: jmp pmesg
246: ptock: pushab tock
247: pmesg: callf $8,_writes /* call print function */
248: movl $0,tikcnt /* clear tick counter */
249: movl $CNT,r2 /* reload rescue timer */
250: decl msgcnt /* decrement message counter */
251: jeql gdhlt
252: cmpl $0x32,msgcnt /* check half done */
253: jgtr lower /* if yes drop IPL to 0x13 */
254: mtpr $0x17,$IPL /* lower IPL allow another tick */
255: jmp loop2 /* continue */
256: lower: mtpr $0x13,$IPL /* lower IPL to 0x13 */
257: loop2: decl r2 /* decrement count register */
258: jneq loop /* not zero then loop */
259: movl $0x02,r0 /* error - expected interrupt did not occur */
260: halt
261:
262: bdint: movl $0x01,r0 /* error - unexpected interrupt occurred */
263: halt
264: txvec: rei
265: gdint: mtpr $CPDCB,$PDCS /* check done bit */
266: movw CPDCB,r1 /* check done bit */
267: andl2 $0x08000,r1 /* mask off don't care bits */
268: jneq gd1 /* not zero jmp */
269: movl $0x03,r0 /* error code done bit not set */
270: halt
271: gd1: mfpr $IPL,r1 /* read current ipl */
272: movl $0x18,r2 /* expected value */
273: cmpl r1,r2
274: jeql gd2
275: movl $0x04,r0 /* error code wrong ipl */
276: halt
277: gd2: movpsl r1 /* get current psl */
278: andl2 $0x0fffff00,r1 /* mask off don't cares */
279: movl $0x04180000,r2 /* expected value */
280: cmpl r1,r2
281: jeql gd3 /* if correct jump */
282: movl $0x05,r0 /* error code wrong psl */
283: halt
284: gd3: movab (sp),r1 /* current stack pointer address */
285: movl $ISTK - 8,r2
286: cmpl r1,r2
287: jeql gd4
288: movl $0x06,r0 /* error code wrong stack address */
289: halt
290: gd4: incl tikcnt /* increment tick counter */
291: rei /* return from interrupt */
292: gdhlt: pushab boom
293: callf $8,_writes /* call print function */
294: movl $0xcafebabe,r0 /* good halt - CAFEBABE ! */
295: halt
296:
297: .data
298:
299: _scb:
300: .space 1024
301:
302: bitbl:
303: .space 1024
304:
305:
306: .align 2
307:
308: CPDCB:
309:
310: .space 20
311:
312: .align 2
313:
314:
315: tikcnt:
316: .space 4
317:
318: msgcnt:
319: .space 4
320:
321: nl: .ascii "\n\0"
322: tick: .ascii "Tick \0"
323: tock: .ascii "Tock \0"
324: boom: .ascii "Boom!\n\0"
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