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Power 6/32 Unix version 1.2b

/*		PROCESSOR STORAGE
	*
	*This is the first two K bytes of physical main memory to
	*be used by hardware/firmware. Software should never use
	*this area.
	*physical locations = 0x00000000 to 0x000007ff
	*virtual locations =  0xc0000000 to 0xc00007ff
	*physical = virtual; kernel read/write access
	*
	*divided into three areas:
	*(1) WCS load area (0x00000000 - 0x000003fc)
	     label = _pstore:
	*(2) Architecturally defined privileged registers (not
	     label = _pstore1:	
	*    provided in CPU hardware (0x00000400 - 0x000005fc)
	*(3) Temporary area for firmware (0x00000600 - 0x00007fc)
	     label = _pstemp: = _tr0:	
	*
*/
/*	.org	0xc00000000		*/
_pstore:
	.globl	_pstore
	.space	NBPG			/*Reserved for WCS loading	*/

_pstore1:				/*architecturally defined	*/
	.globl	_pstore1		/*privileged registers area	*/

_pcbb:	.space	4			/*process control block base reg*/
_isp:	.space	4			/*interrupt stack pointer	*/
_sirr:	.space	4			/*software interrupt request reg*/
_sisr:	.space	4			/*software interrupt summary reg*/
	
	.space	4			/*RESERVED*/
	.space	4
	.space	4

_cpmdcb: .space	4			/*console processor registers	*/
_cpfdcb: .space	4
_cpcdcb: .space	4
_cpidcb: .space	4
_cpstat: .space	4
_cpctl:  .space	4

_hisr:	.space	4			/*hardware interrupt summary reg*/
_dcr:	.space	4			/*diagnostic control register	*/

	.space	4*48			/*RESERVED - 48 unused longwords*/

_pstemp:
	.globl	_pstemp			/*temporary storage area for	*/
					/*firmware			*/
_tr0:	.space	16			/*temporary storage for general	*/
					/*registers 0 thru 15		*/
_tpc:	.space	4			/*program counter		*/
_tpsl:	.space	4			/*program status long word	*/
_tsp:	.space	4			/*stack pointer			*/
_tksp:	.space	4			/*kernel stack pointer		*/
_tusp:	.space	4			/*user stack pointer		*/
_tcck:	.space	4			/*code cache key		*/
_tdck:	.space	4			/*data cache key		*/
_ttbk:	.space	4			/*translation buffer key	*/
_tsbr:	.space	4			/*system base register		*/
_tslr:	.space	4			/*system length register	*/
_tp0br:	.space	4			/*p0 base register		*/
_tp0lr:	.space	4			/*p0 length register		*/
_tp1br:	.space	4			/*p1 base register		*/
_tp1lr:	.space	4			/*p1 length register		*/
_tp2br:	.space	4			/*p2 base register		*/
_tp2lr:	.space	4			/*p2 length register		*/
_tipl:	.space	4			/*interrupt priority level	*/
_tmme:	.space	4			/*memory mgmt enable		*/
_ttbia:	.space	4			/*trans buffer invalidate all	*/
_ttbis:	.space	4			/*trans buffer invalidate single*/
					/*the last two probably will	*/
					/*never be used			*/
_tpcbb:	.space	4			/*process control block base	*/
_tisp:	.space	4			/*interrupt stack pointer	*/
_tsirr:	.space	4			/*software int request reg	*/
_tsisr:	.space	4			/*software int summary reg	*/
_tscbb:	.space	4			/*system control block base	*/
_tp1cc:	.space	4			/*invalidate 1 page of process	*/
					/*code cache			*/
_tpacc:	.space	4			/*invalidate all process pages	*/
					/*in code cache			*/
_tp1dc:	.space	4			/*inval. 1 pg of proc data cache*/
_tpadc:	.space	4			/*inval. all pgs of proc data ch*/
_tcpmdcb:
	.space	4			/*temporary area for cp regs	*/
_tcpfdcb:
	.space	4
_tcpcdcb:
	.space	4
_tcpidcb:
	.space	4
_tcpstat:
	.space	4
_tcpctl:
	.space	4

_probflag:
	.space	4			/*flag for probe instr		*/
_inexcflg:
	.space	4			/*in exception flag		*/

	.space	4*10			/*RESERVED - unused		*/
_psend:	.globl	_psend			/* End of processor storage area*/
	.set    MM,(_psend - _pstore1)
	.space  1024 - MM

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