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Power 6/32 Unix version 1.2b

/*
 *	Definitions for UDC CONTROLLER operations
 *
*/

#define RETRY		200
#define DELAY(n)	{ register N = 3*(n); while (--N > 0 ); }

/*	*****************
	Device parameters
	*****************
*/

#define UDC_BLKLEN	256	/* Block length on UDC */
#define SECTSIZ 	256	/* sector size */
#define BLKSIZ		1024	/* Logical block size */

/* Last block no on floppy <300k> */
#define F_MXBLK		(long)(300)	

/* Last block no on SMD <300Meg>   */
#define S_MXBLK		(long)(300000)	

/* Last block no on CMD, fixed <16meg> */
#define CF_MXBLK	(long)16000	

/* Last block no on CMD, removable <16meg>  */
#define CR_MXBLK	(long)16000	

/* 	******************
	IPC command macros
	******************
*/
#define IPC_RESET	*(char *)(IObase+0xf) = (char)0x00
#define IPC_INT		*(char *)(IObase+0xd) = (char)0x00
#define RD_MCSENT	(*(char *)(IObase+0x101))
#define WR_MCSENT(x)	(*(char *)(IObase+0x101))=(char)x
#define WR_IPCACK(x)	(*(char *)(IObase+0x183))=(char)x
#define RD_IPCACK	(*(char *)(IObase+0x183))
#define RD_IPCSENT	(*(char *)(IObase+0x181))
#define WR_IPCSENT(x)	(*(char *)(IObase+0x181))=(char)x
#define WR_MCACK(x)	(*(char *)(IObase+0x103))=(char)x

/*	*********************
	UDC packet structures
	*********************
*/

struct UDPAC {		/* UDC command packet : 21 bytes */
	char stx  ;
	char pkid ;
	char pksiz ;	/* 21  bytes */
	char pkdev ;	/* device # */	
	char pkcmd ;	/* Command type */
	char pkfnc ;	/* Function type */
	short pkcnt ;	/* # of data blocks (1/4K each) */
	short pbsiz ;	/* Block length size (0x100 = 1/4K) */
	short pkmem[2];	/* Starting memory address  */
	short pcksm ;	/* Checksum (unused) */
	short psecno[2];	/* Starting sector # */
	char etx ;
};

struct UDTPAC {		/* UDC test packet : 15 bytes */
	char stx  ;
	char pkid ;
	char pksiz ;	/* 15 bytes */
	char pkdev ;	/* device # */	
	char pkcmd ;	/* Command type */
	char pkfnc ;	/* Function type */
	short pkcnt ;	/* # of data blocks (1/4K each) */
	short pbsiz ;	/* Block length size (0x100 = 1/4K) */
	long psno ;	/* Starting sector # */
	char endt ;
};
 
struct UDSPAC {		/* UDC status packet : 9_byte format */
	char stx;
	char id;
	char siz;	/* 9 bytes */
	char dev;	/* device # */	
	char scmd;	/* Command type */
	char stype ;	/* Status type */
	short stat ;	/* Status code */
	char etxt ;
}; 


#define IPC_PCK		(IObase+0x185)	/* Base address of IPC packet */
#define MC_PCK		(IObase+0x105)	/* Base address of CPU2 packet */

#define READY	0
#define NUNIT	8		/* number of units per controller */
#define NUDDRV	5		/* number of drive types supported */
#define	DK_N	1		/* Monitoring device bit */

#define	PKID  0x187		/* packet id */
#define	PKLEN 0x189		/* packet length */
#define	PKDEV 0x18b		/* device # */
#define	PKCMD 0x18d		/* command type */
#define	PKSTT 0x18f		/* status type */
#define STAT1 0x191		/* i/o status result offset */
#define STAT2 0x193
#define DEVSTAT1 0x195
#define DEVSTAT2 0x197

#define UDREAD 		(char)0x10
#define UDWTRY 		(char)0x01	/* read with retry */

#define UDWRITE 	(char)0x20
#define UDWCRC  	(char)0x01	/* write sectors and check CRC */
#define UDWSECT 	(char)0x02	/* write sectors */
#define UDWCMP  	(char)0x03	/* write with compare */

#define UDCTL		(char)0x40	/* UDC Control command */
#define	FORMAT		(char)0x07	/* Format with retry */

#define UDTEST  	(char)0x30
#define UDSTAT  	(char)0x02	/* Test status */
#define UDSTST  	(char)0xff	/* self test  */

#define DEVRDY 0x80	/* device ready bit in status byte */

#define RETRANS		(char)0x15	/* Retransmit packet */
#define PCK_OK		(char)0x6	/* Packet O.K	*/

struct dev_parblk {
	char devno;
	short secsiz;
	long maxblk;
	short from;
	short to;
	};

#define CACHE_SZ	8
struct cache {
	short hdr;
	short s_blk;
	short e_blk;
	char buf[1024*CACHE_SZ];
	};


/*
	*************************
	UDC CONTROLLER PARAMETERS
	*************************
*/
#define IOBASE		0xff000000
#define UBASE		0x00ff0000	/* Base of share memory */
#define UDCVEC		0xff		/* Vector no. of UDC */

#define SMD		7
#define CMD_F		0		/* Fixed head portion */
#define CMD_R		1		/* Cartrige portion */
#define FLOPPY0		4		/* Just guess !! */
#define FLOPPY1		5		/* Just guess !! */

#define	INVL_CMD	writes("\ninvalid command\n")
#define NO_DRIVES	5
#define READ		1
#define WRITE		2

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