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Power 6/32 Unix version 1.21
#include "fpp_defs.h"
/*****************************************************************************
*
* ADDF - SINGLE PRECISION FLOATING POINT ADD TEST
*
*****************************************************************************/
addf()
{
asm(".globl _addf_t");
asm("_addf_t:"); /* entry address */
if( ( cycle == 1 ) && ( prt_hdrs ) ) /* print headers on 1st cycle */
writes(" ADDF");
addf_1(); /* add through a register */
addf_2(); /* add through the cache */
addf_3(); /* wait 3 NOPs */
addf_4(); /* wait 2 NOPs */
addf_5(); /* wait 1 NOP before storing */
addf_6(); /* register stability test */
addf_7(); /* PSL stability test */
addf_8(); /* piped entry test */
asm("jmp *return"); /* return to the test monitor */
}
/************************************************************************
*
* SUBTEST 1 - add through a register
*
************************************************************************/
addf_1()
{
force_loop = FALSE;
subtest = 1;
for( index = 0; index < max_addf_1_index; index++ ) {
sgl_ld_acc = addf_1_data[index].op_1; /* get operand 1 */
sgl_value_1 = addf_1_data[index].op_2; /* get operand 2 */
sgl_expected = addf_1_data[index].exp; /* get expected result */
/*
* If LOOP ON ERROR is set, this is the loop for this subtest.
* The force loop flag is set after the first error.
*/
asm("_addf_1_lp1:");
asm("movl _sgl_ld_acc,r3"); /* move the 1st data to r3 */
asm("movl _sgl_value_1,r4"); /* move the 2nd data to r4 */
asm("ldf r3"); /* load the 1st operand */
asm("addf r4"); /* add the 2nd operand */
asm("stf _sgl_st_acc"); /* store the result */
if( force_loop )
asm("brb _addf_1_lp1");; /* loop on the error */
/*
* end error loop - test the results
*/
if( sgl_st_acc != sgl_expected ) { /* COMPARE the values */
errcnt++; /* bump the error count */
if( prt_error ) {
print_addf_er_hdr();
writes(" (Reg. Data) - BAD FINAL ACC\n");
print_addf_data();
}
if( halt_flg )
addf_er_halt( BAD_ACC_HLT ); /* halt on the error */
if( loop_on_err ) {
force_loop = TRUE; /* set the force loop flag */
asm("brw _addf_1_lp1");; /* and loop on the error */
} /* end of loop on error */
} /* end of compare error */
} /* end of WHILE loop */
} /* end of subtest 1 */
/************************************************************************
*
* SUBTEST 2 - add through memory
*
************************************************************************/
addf_2()
{
force_loop = FALSE;
subtest = 2;
for( index = 0; index < max_addf_1_index; index++ ) {
sgl_ld_acc = addf_1_data[index].op_1; /* get operand 1 */
sgl_value_1 = addf_1_data[index].op_2; /* get operand 2 */
sgl_expected = addf_1_data[index].exp; /* get expected result */
/*
* If LOOP ON ERROR is set, this is the loop for this subtest.
* The force loop flag is set after the first error.
*/
asm("_addf_2_lp1:");
asm("ldf _sgl_ld_acc"); /* load the 1st operand */
asm("addf _sgl_value_1"); /* add the 2nd operand */
asm("stf _sgl_st_acc"); /* store the result */
if( force_loop )
asm("brb _addf_2_lp1");; /* loop on the error */
/*
* end error loop - test the results
*/
if( sgl_st_acc != sgl_expected ) { /* COMPARE the values */
errcnt++; /* bump the error count */
if( prt_error ) {
print_addf_er_hdr();
writes(" (Cache Data) - BAD FINAL ACC\n");
print_addf_data();
}
if( halt_flg )
addf_er_halt( BAD_ACC_HLT ); /* halt on the error */
if( loop_on_err ) {
force_loop = TRUE; /* set the force loop flag */
asm("brw _addf_2_lp1");; /* and loop on the error */
} /* end of loop on error */
} /* end of compare error */
} /* end of WHILE loop */
} /* end of subtest 2 */
/************************************************************************
*
* SUBTEST 3 - Wait 3 NOPs before storing the results
*
************************************************************************/
addf_3()
{
force_loop = FALSE;
subtest = 3;
for( index = 0; index < max_addf_1_index; index++ ) {
sgl_ld_acc = addf_1_data[index].op_1; /* get operand 1 */
sgl_value_1 = addf_1_data[index].op_2; /* get operand 2 */
sgl_expected = addf_1_data[index].exp; /* get expected result */
/*
* If LOOP ON ERROR is set, this is the loop for this subtest.
* The force loop flag is set after the first error.
*/
asm("_addf_3_lp1:");
asm("ldf _sgl_ld_acc"); /* load the 1st operand */
asm("nop"); /* delay */
asm("addf _sgl_value_1"); /* add the 2nd operand */
asm("nop"); /* delay before ... */
asm("nop");
asm("nop"); /* ... storing the result */
asm("stf _sgl_st_acc"); /* store the result */
if( force_loop )
asm("brb _addf_3_lp1");; /* loop on the error */
/*
* end error loop - test the results
*/
if( sgl_st_acc != sgl_expected ) { /* COMPARE the values */
errcnt++; /* bump the error count */
if( prt_error ) {
print_addf_er_hdr();
writes(" (Cache Data - 3 NOPS) - BAD FINAL ACC\n");
print_addf_data();
}
if( halt_flg )
addf_er_halt( BAD_ACC_HLT ); /* halt on the error */
if( loop_on_err ) {
force_loop = TRUE; /* set the force loop flag */
asm("brw _addf_3_lp1");; /* and loop on the error */
} /* end of loop on error */
} /* end of compare error */
} /* end of WHILE loop */
} /* end of subtest 3 */
/************************************************************************
*
* SUBTEST 4 - Wait 2 NOPs before storing the results
*
************************************************************************/
addf_4()
{
force_loop = FALSE;
subtest = 4;
for( index = 0; index < max_addf_1_index; index++ ) {
sgl_ld_acc = addf_1_data[index].op_1; /* get operand 1 */
sgl_value_1 = addf_1_data[index].op_2; /* get operand 2 */
sgl_expected = addf_1_data[index].exp; /* get expected result */
/*
* If LOOP ON ERROR is set, this is the loop for this subtest.
* The force loop flag is set after the first error.
*/
asm("_addf_4_lp1:");
asm("ldf _sgl_ld_acc"); /* load the 1st operand */
asm("nop"); /* delay */
asm("addf _sgl_value_1"); /* add the 2nd operand */
asm("nop"); /* delay before ... */
asm("nop"); /* ... storing the result */
asm("stf _sgl_st_acc"); /* store the result */
if( force_loop )
asm("brb _addf_4_lp1");; /* loop on the error */
/*
* end error loop - test the results
*/
if( sgl_st_acc != sgl_expected ) { /* COMPARE the values */
errcnt++; /* bump the error count */
if( prt_error ) {
print_addf_er_hdr();
writes(" (Cache Data - 2 NOPS) - BAD FINAL ACC\n");
print_addf_data();
}
if( halt_flg )
addf_er_halt( BAD_ACC_HLT ); /* halt on the error */
if( loop_on_err ) {
force_loop = TRUE; /* set the force loop flag */
asm("brw _addf_4_lp1");; /* and loop on the error */
} /* end of loop on error */
} /* end of compare error */
} /* end of WHILE loop */
} /* end of subtest 4 */
/************************************************************************
*
* SUBTEST 5 - Wait 1 NOP before storing the results
*
************************************************************************/
addf_5()
{
force_loop = FALSE;
subtest = 5;
for( index = 0; index < max_addf_1_index; index++ ) {
sgl_ld_acc = addf_1_data[index].op_1; /* get operand 1 */
sgl_value_1 = addf_1_data[index].op_2; /* get operand 2 */
sgl_expected = addf_1_data[index].exp; /* get expected result */
/*
* If LOOP ON ERROR is set, this is the loop for this subtest.
* The force loop flag is set after the first error.
*/
asm("_addf_5_lp1:");
asm("ldf _sgl_ld_acc"); /* load the 1st operand */
asm("nop"); /* delay */
asm("addf _sgl_value_1"); /* add the 2nd operand */
asm("nop"); /* delay before storing */
asm("stf _sgl_st_acc"); /* store the result */
if( force_loop )
asm("brb _addf_5_lp1");; /* loop on the error */
/*
* end error loop - test the results
*/
if( sgl_st_acc != sgl_expected ) { /* COMPARE the values */
errcnt++; /* bump the error count */
if( prt_error ) {
print_addf_er_hdr();
writes(" (Cache Data - 1 NOP) - BAD FINAL ACC\n");
print_addf_data();
}
if( halt_flg )
addf_er_halt( BAD_ACC_HLT ); /* halt on the error */
if( loop_on_err ) {
force_loop = TRUE; /* set the force loop flag */
asm("brw _addf_5_lp1");; /* and loop on the error */
} /* end of loop on error */
} /* end of compare error */
} /* end of WHILE loop */
} /* end of subtest 5 */
/************************************************************************
*
* SUBTEST 6 - Check for register corruption
*
************************************************************************/
addf_6()
{
force_loop = FALSE; /* clear force_loop flg */
subtest = 6;
fill_reg_buf( load_regs ); /* get patterns for regs */
index = 0;
sgl_ld_acc = addf_1_data[0].op_1; /* get operand 1 */
sgl_value_1 = addf_1_data[0].op_2; /* get operand 2 */
sgl_expected = addf_1_data[0].exp; /* get expected result */
/*
* If LOOP ON ERROR is set, this is the loop for this subtest.
* The force loop flag is set after the first error.
*/
asm("_addf_6_lp1:");
asm("ldf _sgl_ld_acc"); /* LOAD the accumulator */
asm("nop");
asm("loadr $0x1fff,_load_regs"); /* load regs 0 - 12 */
asm("nop");
asm("addf _sgl_value_1"); /* do the add */
asm("nop");
asm("storer $0x1fff,_store_regs"); /* store regs 0 - 12 */
asm("stf _sgl_st_acc"); /* save the accumulator */
if( force_loop )
asm("brb _addf_6_lp1");; /* loop on the error */
/*
* Now compare the stored register values to those that were loaded
*/
index2 = 0;
while( (load_regs[index2] == store_regs[index2]) && (index2 < 13) )
index2++; /* check reg values */
if( index2 < 13 ) { /* error if index2 < 13 */
errcnt++; /* bump the error count */
if( prt_error ) {
print_addf_er_hdr();
writes(" - A REGISTER WAS MODIFIED\n");
print_addf_data();
writes("register "); /* print the information */
writed( index2 ); /* about the corrupted */
writes(" = "); /* register */
write32h( store_regs[index2] );
writes(", should be = ");
write32h( load_regs[index2] );
writes("\n");
}
if( halt_flg )
addf_er_halt( BAD_REG_HLT ); /* halt on the error */
if( loop_on_err ) {
force_loop = TRUE; /* set the force loop flag */
asm("brw _addf_6_lp1");; /* and loop on the error */
} /* end of loop on error */
} /* end of register corruption error */
} /* end of subtest 6 */
/************************************************************************
*
* SUBTEST 7 - Check for PSL corruption
*
************************************************************************/
addf_7()
{
force_loop = FALSE; /* clear force_loop flg */
subtest = 7;
fill_reg_buf( load_regs ); /* get patterns for regs */
for( index = 0; index < 3; index++ ) {
sgl_ld_acc = addf_1_data[index].op_1; /* get operand 1 */
sgl_value_1 = addf_1_data[index].op_2; /* get operand 2 */
sgl_expected = addf_1_data[index].exp; /* get expected */
sgl_dummy1 = status_array[index]; /* status = +, -, 0 */
/*
* If LOOP ON ERROR is set, this is the loop for this subtest.
* The force loop flag is set after the first error.
*/
asm("_addf_7_lp1:");
asm("ldf _sgl_ld_acc"); /* LOAD the accumulator */
asm("nop");
asm("tstl _sgl_dummy1"); /* set the PSL status */
asm("movpsl _init_psl"); /* save the initial PSL */
asm("addf _sgl_value_1"); /* do the add */
asm("nop");
asm("movpsl _psl_val"); /* save the final PSL */
asm("stf _sgl_st_acc"); /* save the accumulator */
if( force_loop )
asm("brb _addf_7_lp1");; /* loop on the error */
/*
* Now compare the final PSL to the initial PSL -they should be the same
*/
exp_psl = init_psl;
if( psl_val != exp_psl ) {
errcnt++; /* bump the error count */
if( prt_error ) {
print_addf_er_hdr();
writes(" - INCORRECT FINAL PSL\n");
print_addf_data();
writes("initial PSL = ");
write32h( init_psl );
writes(", final PSL = ");
write32h( psl_val );
writes(", expected PSL = ");
write32h( exp_psl );
writes("\n");
}
if( halt_flg )
addf_er_halt( BAD_PSL_HLT ); /* halt on the error */
if( loop_on_err ) {
force_loop = TRUE; /* set the force loop flag */
asm("brw _addf_7_lp1");; /* and loop on the error */
} /* end of loop on error */
} /* end of PSL corruption error */
} /* end of data WHILE loop */
} /* end of subtest 7 */
/************************************************************************
*
* SUBTEST 8 - pipelined entry test
*
************************************************************************/
addf_8()
{
force_loop = FALSE;
subtest = 8;
for( index = 0; index < max_addf_1_index; index++ ) {
sgl_ld_acc = addf_1_data[index].op_1; /* get operand 1 */
sgl_value_1 = addf_1_data[index].op_2; /* get operand 2 */
sgl_expected = addf_1_data[index].exp; /* get expected result */
/*
* If LOOP ON ERROR is set, this is the loop for this subtest.
* The force loop flag is set after the first error.
*/
asm("_addf_8_lp1:");
asm("movl $0,r0"); /* clear r0 */
asm("ldf r0"); /* load the Acc. with 0.0 */
asm("addf _sgl_ld_acc"); /* add the 1st operand */
asm("addf _sgl_value_1"); /* add the 2nd operand */
asm("stf _sgl_st_acc"); /* store the result */
if( force_loop )
asm("brb _addf_8_lp1");; /* loop on the error */
/*
* end error loop - test the results
*/
if( sgl_st_acc != sgl_expected ) { /* COMPARE the values */
errcnt++; /* bump the error count */
if( prt_error ) {
print_addf_er_hdr();
writes(" (Piped Entry) - BAD FINAL ACC\n");
print_addf_data();
}
if( halt_flg )
addf_er_halt( BAD_ACC_HLT ); /* halt on the error */
if( loop_on_err ) {
force_loop = TRUE; /* set the force loop flag */
asm("brw _addf_8_lp1"); /* and loop on the error */
} /* end of loop on error */
} /* end of compare error */
} /* end of data While loop */
} /* end of subtest 8 */
/**************************************************************************
*
* PRINT THE ERROR HEADER
*
**************************************************************************/
print_addf_er_hdr()
{
writes(" \n"); /* start a new print line */
writes("cycle: "); /* print the cycle count */
writed( cycle );
writes(" ADDF test "); /* print the test number */
writed( test_no );
writes(", subtest "); /* print the subtest no. */
writed( subtest );
}
/**************************************************************************
*
* PRINT THE DATA AND STORE RESULTS
*
* initial Acc = xxxxxxxx, stored = xxxxxxxx, data index = xx
* operand = xxxxxxxx, expected = xxxxxxxx
**************************************************************************/
print_addf_data()
{
writes("initial Acc = ");
write32h( sgl_ld_acc );
writes(", stored = ");
write32h( sgl_st_acc );
writes(", data index = ");
writed( index );
writec('\n');
writes(" operand = ");
write32h( sgl_value_1 );
writes(", expected = ");
write32h( sgl_expected );
writec('\n');
}
/**************************************************************************
*
* HALT ON ERROR ROUTINE
*
**************************************************************************/
addf_er_halt( halt_code )
int halt_code;
{
sgl_dummy1 = halt_code; /* get the error type */
asm("movl _test_no,r0"); /* r0 = test number */
asm("movl _subtest,r1"); /* r1 = subtest number */
asm("movl _sgl_dummy1,r2"); /* r2 = error code */
asm("movl _cycle,r3"); /* r3 = cycle count */
asm("movl _sgl_ld_acc,r4"); /* r4 = initial data */
asm("movl _sgl_value_1,r5"); /* r5 = data added */
asm("movl _sgl_st_acc,r6"); /* r6 = data stored */
if( halt_code == BAD_ACC_HLT ) {
asm("movl _sgl_expected,r7"); /* r7 = data expected */
asm("movl _index,r8"); /* r8 = data index */
} else
if( halt_code == BAD_REG_HLT ) {
sgl_dummy1 = load_regs[index2];
sgl_dummy2 = store_regs[index2];
asm("movl _index2,r7"); /* r7 = bad register # */
asm("movl _sgl_dummy2,r8"); /* r8 = actual value */
asm("movl _sgl_dummy1,r9"); /* r9 = expected value */
} else
if( halt_code == BAD_PSL_HLT ) {
asm("movl _init_psl,r7"); /* r7 = initial PSL */
asm("movl _psl_val,r8"); /* r8 = final PSL */
asm("movl _exp_psl,r9"); /* r9 = expected PSL */
};
asm("halt"); /* HALT ... */
}
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