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Up to [Power 6/32 Unix Tahoe 4.2BSD] / cci / d / macro4|
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Power 6/32 Unix version 1.21
#include "fpp_defs.h"
/***************************************************************************
*
* CMPD2 -COMPARE 2 DBL OPERANDS TO EACH OTHER -IGNORE THE ACCUMULATOR
*
*****************************************************************************/
cmpd2()
{
asm(".globl _cmpd2_t");
asm("_cmpd2_t:"); /* entry address */
if( ( cycle == 1 ) && ( prt_hdrs ) ) /* print headers on 1st pass */
writes(" CMPD2");
cmpd2_1(); /* register / register data */
cmpd2_2(); /* cache / cache data */
cmpd2_3(); /* cache / register data */
cmpd2_4(); /* register / cache data */
cmpd2_5(); /* acc. corruption test */
cmpd2_6(); /* register corruption test */
asm("jmp *return"); /* return to the test monitor */
}
/****************************************************************************
*
* SUBTEST 1 - CMPD2 test -register / register data
*
****************************************************************************/
cmpd2_1()
{
force_loop = FALSE;
subtest = 1;
index = 0;
do
{
dbl_value_1 = cmpd_1_data[index].one; /* get the data operands */
dbl_value_2 = cmpd_1_data[index].two;
sgl_expected = cmpd_1_data[index].flag; /* get expected results */
sgl_value_1 = dbl_value_1.m;
sgl_value_2 = dbl_value_1.l;
sgl_value_3 = dbl_value_2.m;
sgl_value_4 = dbl_value_2.l;
index2 = 0; /* clear Acc. data index */
do
{
dbl_ld_acc = ldd_1_data[index2].ld; /* get the Accumulator data */
asm("ldd _dbl_ld_acc"); /* load the accumulator */
status_index = 0; /* clear the status index */
do
{
sgl_dummy1 = status_array[status_index]; /* array = +, -, 0 */
/*
* If LOOP ON ERROR is set, this is the loop for this subtest.
* The force loop flag is set after the first error.
*/
asm("_cmpd2_1_lp1:");
asm("movl _sgl_value_1,r4"); /* r4 = operand #1's MSW */
asm("movl _sgl_value_2,r5"); /* r5 = operand #1's LSW */
asm("movl _sgl_value_3,r6"); /* r6 = operand #2's MSW */
asm("movl _sgl_value_4,r7"); /* r7 = operand #2's LSW */
asm("nop");
asm("tstl _sgl_dummy1"); /* generate initial status */
asm("movpsl _init_psl"); /* save the initial status */
asm("cmpd2 r4,r6"); /* compare the operands */
asm("movpsl _psl_val"); /* save the final status */
asm("std _dbl_st_acc"); /* save the acc */
if( force_loop ) /* loop? */
asm("brb _cmpd2_1_lp1");; /* run the loop again */
exp_psl = init_psl; /* get the initial PSL */
exp_psl &= 0xfffffff3; /* clear ZERO, NEGATIVE */
if( sgl_expected == ZERO )
exp_psl |= PSL_Z; /* expect the ZERO bit set */
if( sgl_expected == NEGATIVE )
exp_psl |= PSL_N; /* expect the NEG bit set */
if( psl_val != exp_psl ) { /* COMPARE the values */
errcnt++; /* bump the error count */
if ( prt_error ) {
writes(" \n"); /* start a new print line */
writes("cycle: ");
writed( cycle );
writes(" CMPD2 test ");
writed( test_no );
writes(", subtest 1 (Reg./Reg. Data) - BAD FINAL PSL\n");
print_cmpd2_data();
writes(", index = ");
writed( index );
writec('\n');
writes(" final Acc = ");
write32h( dbl_st_acc.m );
writec(' ');
write32h( dbl_st_acc.l );
writes(", operand 2 = ");
write32h( sgl_value_3);
writec(' ');
write32h( sgl_value_4);
writec('\n');
writes(" initial PSL = ");
write32h( init_psl );
writes(", final PSL = ");
write32h( psl_val );
writes(", expected PSL = ");
write32h( exp_psl );
writes(" \n");
}
if ( halt_flg )
cmpd2_er_halt( BAD_PSL_HLT ); /* halt on the error */
if ( loop_on_err ) {
force_loop = TRUE; /* set the force loop flag */
asm("brw _cmpd2_1_lp1"); /* and loop */
}; /* end of loop-on-error */
} /* end of compare error */
} while( ++status_index < 3 );
index2++;
} while( (index2 < 10) && (index2 < max_ldf_1_index) );
} while( index++ < max_cmpd_1_index );
} /* end of subtest 1 */
/****************************************************************************
*
* SUBTEST 2 - CMPD2 test - cache / cache data
*
****************************************************************************/
cmpd2_2()
{
force_loop = FALSE;
subtest = 2;
index = 0;
do
{
dbl_value_1 = cmpd_1_data[index].one; /* get the data operands */
dbl_value_2 = cmpd_1_data[index].two;
sgl_value_1 = dbl_value_1.m;
sgl_value_2 = dbl_value_1.l;
sgl_value_3 = dbl_value_2.m;
sgl_value_4 = dbl_value_2.l;
sgl_expected = cmpd_1_data[index].flag; /* get expected results */
index2 = 0; /* clear Acc. data index */
do
{
dbl_ld_acc = ldd_1_data[index2].ld; /* get the Accumulator data */
asm("ldd _dbl_ld_acc"); /* load the accumulator */
status_index = 0; /* clear the status index */
do
{
sgl_dummy1 = status_array[status_index]; /* array = +, -, 0 */
/*
* If LOOP ON ERROR is set, this is the loop for this subtest.
* The force loop flag is set after the first error.
*/
asm("_cmpd2_2_lp1:");
asm("tstl _sgl_dummy1"); /* generate initial status */
asm("movpsl _init_psl"); /* save the initial status */
asm("nop");
asm("cmpd2 _dbl_value_1,_dbl_value_2"); /* compare the data */
asm("nop");
asm("movpsl _psl_val"); /* save the final status */
asm("std _dbl_st_acc"); /* save the acc */
if( force_loop ) /* loop? */
asm("brb _cmpd2_2_lp1");; /* run the loop again */
exp_psl = init_psl; /* get the initial PSL */
exp_psl &= 0xfffffff3; /* clear ZERO, NEGATIVE */
if( sgl_expected == ZERO )
exp_psl |= PSL_Z; /* expect the ZERO bit set */
if( sgl_expected == NEGATIVE )
exp_psl |= PSL_N; /* expect the NEG bit set */
if( psl_val != exp_psl ) { /* COMPARE the values */
errcnt++; /* bump the error count */
if ( prt_error ) {
writes(" \n"); /* start a new print line */
writes("cycle: ");
writed( cycle );
writes(" CMPD2 test ");
writed( test_no );
writes(", subtest 2 (Cache/Cache Data) - BAD FINAL PSL\n");
print_cmpd2_data();
writes(", index = ");
writed( index );
writec('\n');
writes(" final Acc = ");
write32h( dbl_st_acc.m );
writec(' ');
write32h( dbl_st_acc.l );
writes(", operand 2 = ");
write32h( sgl_value_3);
writec(' ');
write32h( sgl_value_4);
writec('\n');
writes(" initial PSL = ");
write32h( init_psl );
writes(", final PSL = ");
write32h( psl_val );
writes(", expected PSL = ");
write32h( exp_psl );
writes(" \n");
}
if ( halt_flg )
cmpd2_er_halt( BAD_PSL_HLT ); /* halt on the error */
if ( loop_on_err )
{
force_loop = TRUE; /* set the force loop flag */
asm("brw _cmpd2_2_lp1"); /* and loop */
}; /* end of loop-on-error */
} /* end of compare error */
} while( ++status_index < 3 );
index2++;
} while( (index2 < 10) && (index2 < max_ldf_1_index) );
} while( index++ < max_cmpd_1_index );
} /* end of subtest 2 */
/****************************************************************************
*
* SUBTEST 3 - CMPD2 test - cache / register data
*
****************************************************************************/
cmpd2_3()
{
force_loop = FALSE;
subtest = 3;
index = 0;
do
{
dbl_value_1 = cmpd_1_data[index].one; /* get the data operands */
dbl_value_2 = cmpd_1_data[index].two;
sgl_value_1 = dbl_value_1.m;
sgl_value_2 = dbl_value_1.l;
sgl_value_3 = dbl_value_2.m;
sgl_value_4 = dbl_value_2.l;
sgl_expected = cmpd_1_data[index].flag; /* get expected results */
index2 = 0; /* clear Acc. data index */
do
{
dbl_ld_acc = ldd_1_data[index2].ld; /* get the Accumulator data */
asm("ldd _dbl_ld_acc"); /* load the accumulator */
status_index = 0; /* clear the status index */
do
{
sgl_dummy1 = status_array[status_index]; /* array = +, -, 0 */
/*
* If LOOP ON ERROR is set, this is the loop for this subtest.
* The force loop flag is set after the first error.
*/
asm("_cmpd2_3_lp1:");
asm("movl _sgl_value_3,r4"); /* move operand #2's MSW,r4 */
asm("movl _sgl_value_4,r5"); /* move operand #2's LSW,r5 */
asm("tstl _sgl_dummy1"); /* generate initial status */
asm("movpsl _init_psl"); /* save the initial status */
asm("nop");
asm("cmpd2 _dbl_value_1,r4"); /* compare the data */
asm("nop");
asm("movpsl _psl_val"); /* save the final status */
asm("std _sgl_st_acc"); /* save the acc */
if( force_loop ) /* loop? */
asm("brb _cmpd2_3_lp1");; /* run the loop again */
exp_psl = init_psl; /* get the initial PSL */
exp_psl &= 0xfffffff3; /* clear ZERO, NEGATIVE */
if( sgl_expected == ZERO )
exp_psl |= PSL_Z; /* expect the ZERO bit set */
if( sgl_expected == NEGATIVE )
exp_psl |= PSL_N; /* expect the NEG bit set */
if( psl_val != exp_psl ) { /* COMPARE the values */
errcnt++; /* bump the error count */
if ( prt_error ) {
writes(" \n"); /* start a new print line */
writes("cycle: ");
writed( cycle );
writes(" CMPD2 test ");
writed( test_no );
writes(", subtest 3 (Cache/Reg. Data) - BAD FINAL PSL\n");
print_cmpd2_data();
writes(", index = ");
writed( index );
writec('\n');
writes(" final Acc = ");
write32h( dbl_st_acc.m );
writec(' ');
write32h( dbl_st_acc.l );
writes(", operand 2 = ");
write32h( sgl_value_3);
writec(' ');
write32h( sgl_value_4);
writec('\n');
writes(" initial PSL = ");
write32h( init_psl );
writes(", final PSL = ");
write32h( psl_val );
writes(", expected PSL = ");
write32h( exp_psl );
writes(" \n");
}
if ( halt_flg )
cmpd2_er_halt( BAD_PSL_HLT ); /* halt on the error */
if ( loop_on_err )
{
force_loop = TRUE; /* set the force loop flag */
asm("brw _cmpd2_3_lp1"); /* and loop */
}; /* end of loop-on-error */
} /* end of compare error */
} while( ++status_index < 3 );
index2++;
} while( (index2 < 10) && (index2 < max_ldf_1_index) );
} while( index++ < max_cmpd_1_index );
} /* end of subtest 3 */
/****************************************************************************
*
* SUBTEST 4 - CMPD2 test - register / cache data
*
****************************************************************************/
cmpd2_4()
{
force_loop = FALSE;
subtest = 4;
index = 0;
do
{
dbl_value_1 = cmpd_1_data[index].one; /* get the data operands */
dbl_value_2 = cmpd_1_data[index].two;
sgl_value_1 = dbl_value_1.m;
sgl_value_2 = dbl_value_1.l;
sgl_value_3 = dbl_value_2.m;
sgl_value_4 = dbl_value_2.l;
sgl_expected = cmpd_1_data[index].flag; /* get expected results */
index2 = 0; /* clear Acc. data index */
do
{
dbl_ld_acc = ldd_1_data[index2].ld; /* get the Accumulator data */
asm("ldd _dbl_ld_acc"); /* load the accumulator */
status_index = 0; /* clear the status index */
do
{
sgl_dummy1 = status_array[status_index]; /* array = +, -, 0 */
/*
* If LOOP ON ERROR is set, this is the loop for this subtest.
* The force loop flag is set after the first error.
*/
asm("_cmpd2_4_lp1:");
asm("movl _sgl_value_1,r2"); /* move operand #1,s MSW,r2 */
asm("movl _sgl_value_2,r3"); /* move operand #1's LSW,r3 */
asm("tstl _sgl_dummy1"); /* generate initial status */
asm("movpsl _init_psl"); /* save the initial status */
asm("nop");
asm("cmpd2 r2,_dbl_value_2"); /* compare the data */
asm("nop");
asm("movpsl _psl_val"); /* save the final status */
asm("std _dbl_st_acc"); /* save the acc */
if( force_loop ) /* loop? */
asm("brb _cmpd2_4_lp1");; /* run the loop again */
exp_psl = init_psl; /* get the initial PSL */
exp_psl &= 0xfffffff3; /* clear ZERO, NEGATIVE */
if( sgl_expected == ZERO )
exp_psl |= PSL_Z; /* expect the ZERO bit set */
if( sgl_expected == NEGATIVE )
exp_psl |= PSL_N; /* expect the NEG bit set */
if( psl_val != exp_psl ) { /* COMPARE the values */
errcnt++; /* bump the error count */
if ( prt_error ) {
writes(" \n"); /* start a new print line */
writes("cycle: ");
writed( cycle );
writes(" CMPD2 test ");
writed( test_no );
writes(", subtest 4 (Reg./Cache Data) - BAD FINAL PSL\n");
print_cmpd2_data();
writes(", index = ");
writed( index );
writec('\n');
writes(" final Acc = ");
write32h( dbl_st_acc.m );
writec(' ');
write32h( dbl_st_acc.l );
writes(", operand 2 = ");
write32h( sgl_value_3);
writec(' ');
write32h( sgl_value_4);
writec('\n');
writes(" initial PSL = ");
write32h( init_psl );
writes(", final PSL = ");
write32h( psl_val );
writes(", expected PSL = ");
write32h( exp_psl );
writes(" \n");
}
if ( halt_flg )
cmpd2_er_halt( BAD_PSL_HLT ); /* halt on the error */
if ( loop_on_err )
{
force_loop = TRUE; /* set the force loop flag */
asm("jmp _cmpd2_4_lp1"); /* and loop */
} /* end of loop-on-error */
} /* end of compare error */
} while( ++status_index < 3 ); /* end of status loop */
index2++;
} while( (index2 < 10) && (index2 < max_ldf_1_index) );
} while( index++ < max_cmpd_1_index );
} /* end of subtest 4 */
/************************************************************************
*
* SUBTEST 5 - Check for register corruption
*
************************************************************************/
cmpd2_5()
{
force_loop = FALSE; /* clear force_loop flg */
subtest = 5;
fill_reg_buf( load_regs ); /* get pattern for regs */
index = 0;
do
{
dbl_value_1 = cmpd_1_data[index].one; /* data to load */
dbl_value_2 = cmpd_1_data[index].two; /* data to compare */
dbl_ld_acc.m = 0x40800000; /* get acc data */
dbl_ld_acc.l = 0x10101010; /* get acc data */
sgl_value_1 = dbl_value_1.m;
sgl_value_2 = dbl_value_1.l;
sgl_value_3 = dbl_value_2.m;
sgl_value_4 = dbl_value_2.l;
asm("ldd _dbl_ld_acc"); /* load the acc */
/*
* If LOOP ON ERROR is set, this is the loop for this subtest.
* The force loop flag is set after the first error.
*/
asm("_cmpd2_5_lp1:");
asm("loadr $0x1fff,_load_regs"); /* load regs 0 - 12 */
asm("nop");
asm("cmpd2 _dbl_value_1,_dbl_value_2"); /* compare the data */
asm("nop");
asm("storer $0x1fff,_store_regs"); /* store regs 0 - 12 */
asm("std _dbl_st_acc"); /* save the acc */
if( force_loop ) /* loop? */
asm("brb _cmpd2_5_lp1");; /* run the loop again */
/*
* Now compare the stored register values to those that were loaded
*/
index2 = 0;
while( (load_regs[index2] == store_regs[index2]) && (index2 < 13) )
index2++; /* check reg values */
if( index2 < 13 ) { /* error if index2 < 13 */
errcnt++; /* bump the error count */
if ( prt_error ) {
writes(" \n"); /* start a new print line */
writes("cycle: ");
writed( cycle );
writes(", CMPD2 test ");
writed( test_no );
writes(", subtest 5 - A REGISTER WAS MODIFIED\n");
print_cmpd2_data();
writec('\n');
writes(" final Acc = ");
write32h( dbl_st_acc.m );
writec(' ');
write32h( dbl_st_acc.l );
writes(", operand 2 = ");
write32h( sgl_value_3);
writec(' ');
write32h( sgl_value_4);
writec('\n');
writes("register ");
writed( index2 );
writes(" = ");
write32h( store_regs[ index2 ] );
writes(", should be = ");
write32h( load_regs[ index2 ] );
writes("\n");
}
if ( halt_flg )
cmpd2_er_halt( BAD_REG_HLT ); /* halt on the error */
if ( loop_on_err )
{
force_loop = TRUE; /* set the force loop flag */
asm("jmp _cmpd2_5_lp1"); /* and loop */
}; /* end of loop-on-error */
} /* end of compare error */
} while( index++ < max_cmpd_1_index );
} /* end of subtest 5 */
/****************************************************************************
*
* SUBTEST 6 - CMPD2 test Accumulator stability test
*
****************************************************************************/
cmpd2_6()
{
force_loop = FALSE;
subtest = 6;
index = 0;
do
{
dbl_value_1 = cmpd_1_data[index].one; /* get the data operands */
dbl_value_2 = cmpd_1_data[index].two;
sgl_value_1 = dbl_value_1.m;
sgl_value_2 = dbl_value_1.l;
sgl_value_3 = dbl_value_2.m;
sgl_value_4 = dbl_value_2.l;
index2 = 0; /* clear Acc. data index */
do
{
dbl_ld_acc = ldd_1_data[index2].ld; /* get the Accumulator data */
if( !(dbl_ld_acc.m & 0x7f800000 ) ) {
dbl_expected.m = 0; /* expect a '0' stored */
dbl_expected.l = 0;
} else
dbl_expected = dbl_ld_acc;
asm("ldd _dbl_ld_acc"); /* load the acc */
/*
* If LOOP ON ERROR is set, this is the loop for this subtest.
* The force loop flag is set after the first error.
*/
asm("_cmpd2_6_lp1:");
asm("nop");
asm("cmpd2 _dbl_value_1,_dbl_value_2");/* compare the operands */
asm("nop");
asm("std _dbl_st_acc"); /* store the accumulator */
if( force_loop ) /* loop? */
asm("brb _cmpd2_6_lp1");; /* run the loop again */
if( (dbl_st_acc.m != dbl_expected.m) || /* compare the final */
(dbl_st_acc.l != dbl_expected.l) ) { /* results */
errcnt++; /* bump the error count */
if ( prt_error ) {
writes(" \n"); /* start a new print line */
writes("cycle: ");
writed( cycle );
writes(" CMPD2 test ");
writed( test_no );
writes(", subtest 6 - BAD FINAL ACC\n");
print_cmpd2_data();
writes(", index = ");
writed( index );
writec('\n');
writes(" final Acc = ");
write32h( dbl_st_acc.m );
writec(' ');
write32h( dbl_st_acc.l );
writes(", operand 2 = ");
write32h( sgl_value_3);
writec(' ');
write32h( sgl_value_4);
writec('\n');
writes("expected Acc = ");
write32h( dbl_expected.m );
writec(' ');
write32h( dbl_expected.l );
writec('\n');
}
if ( halt_flg ) /* halt on error? */
cmpd2_er_halt( BAD_ACC_HLT );
if ( loop_on_err )
{
force_loop = TRUE; /* set the force loop flag */
asm("jmp _cmpd2_6_lp1"); /* and loop */
}; /* end of loop-on-error */
} /* end of compare error */
index2++;
} while( (index2 < 10) && (index2 < max_ldf_1_index) );
} while( index++ < max_cmpd_1_index );
} /* end of subtest 6 */
/**************************************************************************
*
* PRINT THE DATA AND STORE RESULTS
*
* initial Acc = xxxxxxxx xxxxxxxx, operand 1 = xxxxxxxx xxxxxxxx
**************************************************************************/
print_cmpd2_data()
{
writes(" initial Acc = ");
write32h( dbl_ld_acc.m );
writec(' ');
write32h( dbl_ld_acc.l );
writes(", operand 1 = ");
write32h( sgl_value_1 );
writec(' ');
write32h( sgl_value_2 );
}
/**************************************************************************
*
* HALT ON ERROR ROUTINE
*
**************************************************************************/
cmpd2_er_halt( halt_code )
int halt_code;
{
sgl_value_1 = dbl_value_1.m;
sgl_value_2 = dbl_value_1.l;
sgl_value_3 = dbl_value_2.m;
sgl_value_4 = dbl_value_2.l;
sgl_value_5 = dbl_ld_acc.m;
sgl_value_6 = dbl_ld_acc.l;
sgl_value_7 = dbl_st_acc.m;
sgl_value_8 = dbl_st_acc.l;
sgl_dummy1 = halt_code; /* get the error type */
asm("movl _test_no,r0"); /* r0 = test number */
asm("movl _subtest,r1"); /* r1 = subtest number */
asm("movl _sgl_dummy1,r2"); /* r2 = error code */
asm("movl _cycle,r3"); /* r3 = cycle count */
asm("movl _sgl_value_5,r4"); /* r4 = MS acc loaded */
asm("movl _sgl_value_6,r5"); /* r5 = LS acc loaded */
asm("movl _sgl_value_1,r6"); /* r6 = MS operand 1 */
asm("movl _sgl_value_2,r7"); /* r7 = MS operand 1 */
asm("movl _sgl_value_3,r8"); /* r8 = MS operand 2 */
asm("movl _sgl_value_4,r9"); /* r9 = MS operand 2 */
asm("movl _psl_val,r10"); /* r10 = actual PSL */
if( halt_code == BAD_ACC_HLT ) {
sgl_value_1 = dbl_expected.m;
sgl_value_2 = dbl_expected.l;
asm("movl _sgl_value_7,r11"); /* r11 = MS stored */
asm("movl _sgl_value_8,r12"); /* r12 = LS stored */
asm("movl _sgl_value_1,r13"); /* r13 = MS expected */
asm("movl _sgl_value_2,r14"); /* r14 = LS expected */
} else
if( halt_code == BAD_REG_HLT ) {
sgl_dummy1 = load_regs[index2];
sgl_dummy2 = store_regs[index2];
asm("movl _index2,r11"); /* r11 = bad register # */
asm("movl _sgl_dummy2,r12"); /* r12 = actual value */
asm("movl _sgl_dummy1,r13"); /* r13 = expected value */
} else
if( halt_code == BAD_PSL_HLT ) {
asm("movl _exp_psl,r11"); /* r11 = expected PSL */
asm("movl _index,r12"); /* r12 = data index */
};
asm("halt"); /* HALT ... */
}
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