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1.1 ! root 1: ! 2: #include "fpp_defs.h" ! 3: ! 4: ! 5: /***************************************************************************** ! 6: * ! 7: * CVDF - SINGLE PRECISION FLOATING POINT CONVERT LONG TO FLOAT TEST ! 8: * ! 9: *****************************************************************************/ ! 10: cvdf() ! 11: { ! 12: asm(".globl _cvdf_t"); ! 13: asm("_cvdf_t:"); /* entry address */ ! 14: if( ( cycle == 1 ) && ( prt_hdrs ) ) /* print headers on 1st pass */ ! 15: writes("\n CVDF"); ! 16: cvdf_1(); /* load through a register */ ! 17: cvdf_2(); /* register stability */ ! 18: cvdf_3(); /* PSL stability test */ ! 19: asm("jmp *return"); /* return to the test monitor */ ! 20: } ! 21: ! 22: ! 23: ! 24: /************************************************************************ ! 25: * ! 26: * SUBTEST 1 ! 27: * ! 28: ************************************************************************/ ! 29: cvdf_1() ! 30: { ! 31: force_loop = FALSE; ! 32: subtest = 1; ! 33: index = 0; ! 34: do { ! 35: dbl_ld_acc = cvdf_1_data[index].ld; /* get the operand */ ! 36: sgl_expected = cvdf_1_data[index].exp; /* get expected result */ ! 37: if( (dbl_ld_acc.m & 0x7f800000) ) { ! 38: sgl_expected = dbl_ld_acc.m; ! 39: if( dbl_ld_acc.l & 0x80000000) ! 40: sgl_expected++; ! 41: } ! 42: /* ! 43: * If LOOP ON ERROR is set, this is the loop for this subtest. ! 44: * The force loop flag is set after the first error. ! 45: */ ! 46: asm("_cvdf_1_lp1:"); ! 47: asm("movl _dbl_ld_acc,r4"); /* get the value to convert */ ! 48: asm("movl _dbl_ld_acc+4,r5"); ! 49: asm("ldd r4"); /* load the data */ ! 50: asm("cvdf"); /* convert the value */ ! 51: asm("stf r8"); /* store the result */ ! 52: if( force_loop ) ! 53: asm("brb _cvdf_1_lp1");; /* loop on the error */ ! 54: /* ! 55: * end error loop - test the results ! 56: */ ! 57: asm("movl r8,_sgl_st_acc"); /* move result to cache */ ! 58: if( sgl_st_acc != sgl_expected ) { /* COMPARE the values */ ! 59: errcnt++; /* bump the error count */ ! 60: if( prt_error ) { ! 61: writes(" \n"); /* start a new print line */ ! 62: writes("cycle: "); ! 63: writed( cycle ); ! 64: writes(" CVDF test "); ! 65: writed( test_no ); ! 66: writes(", subtest 1 (Reg. Data) - BAD FINAL ACC\n"); ! 67: print_cvdf_data(); ! 68: writes(" Acc expected = "); ! 69: write32h( sgl_expected ); ! 70: writec('\n'); ! 71: } ! 72: if( halt_flg ) ! 73: cvdf_er_halt( BAD_ACC_HLT ); /* halt on the error */ ! 74: if( loop_on_err ) { ! 75: force_loop = TRUE; /* set the force loop flag */ ! 76: asm("brw _cvdf_1_lp1");; /* and loop on the error */ ! 77: } /* end of loop on error */ ! 78: } /* end of compare error */ ! 79: } while( index++ < max_cvdf_1_index ); /* end of WHILE loop */ ! 80: } /* end of subtest 1 */ ! 81: ! 82: ! 83: ! 84: /************************************************************************ ! 85: * ! 86: * SUBTEST 2 - Check for register corruption ! 87: * ! 88: ************************************************************************/ ! 89: cvdf_2() ! 90: { ! 91: force_loop = FALSE; /* clear force_loop flg */ ! 92: subtest = 2; ! 93: fill_reg_buf( load_regs ); /* get patterns for regs */ ! 94: index = 0; ! 95: dbl_ld_acc = cvdf_1_data[index].ld; /* get the operand */ ! 96: sgl_expected = cvdf_1_data[index].exp; /* get expected result */ ! 97: /* ! 98: * If LOOP ON ERROR is set, this is the loop for this subtest. ! 99: * The force loop flag is set after the first error. ! 100: */ ! 101: asm("_cvdf_2_lp1:"); ! 102: asm("ldd _dbl_ld_acc"); /* load the data */ ! 103: asm("loadr $0x1fff,_load_regs"); /* load regs 0 - 12 */ ! 104: asm("nop"); ! 105: asm("cvdf"); /* convert the value */ ! 106: asm("nop"); ! 107: asm("storer $0x1fff,_store_regs"); /* store regs 0 - 12 */ ! 108: if( force_loop ) ! 109: asm("brb _cvdf_2_lp1");; /* loop on the error */ ! 110: /* ! 111: * Now compare the stored register values to those that were loaded ! 112: */ ! 113: index2 = 0; ! 114: while( (load_regs[index2] == store_regs[index2]) && (index2 < 13) ) ! 115: index2++; /* check reg values */ ! 116: if( index2 < 13 ) { /* error if index2 < 13 */ ! 117: errcnt++; /* bump the error count */ ! 118: if( prt_error ) { ! 119: writes(" \n"); /* start a new print line */ ! 120: writes("cycle: "); ! 121: writed( cycle ); ! 122: writes(" CVDF test "); ! 123: writed( test_no ); ! 124: writes(", subtest 2 - A REGISTER WAS MODIFIED\n"); ! 125: print_cvdf_data(); /* print the operands */ ! 126: writes("register "); /* print the information */ ! 127: writed( index2 ); /* about the corrupted */ ! 128: writes(" = "); /* register */ ! 129: write32h( store_regs[index2] ); ! 130: writes(", should be = "); ! 131: write32h( load_regs[index2] ); ! 132: writes("\n"); ! 133: } ! 134: if( halt_flg ) ! 135: cvdf_er_halt( BAD_REG_HLT ); /* halt on the error */ ! 136: if( loop_on_err ) { ! 137: force_loop = TRUE; /* set the force loop flag */ ! 138: asm("brw _cvdf_2_lp1");; /* and loop on the error */ ! 139: } /* end of loop on error */ ! 140: } while( index++ < max_cvdf_1_index ); /* end of reg corruption error */ ! 141: } /* end of subtest 2 */ ! 142: ! 143: ! 144: ! 145: /************************************************************************ ! 146: * ! 147: * SUBTEST 3 - Check for PSL corruption ! 148: * ! 149: ************************************************************************/ ! 150: cvdf_3() ! 151: { ! 152: force_loop = FALSE; /* clear force_loop flg */ ! 153: subtest = 3; ! 154: fill_reg_buf( load_regs ); /* get patterns for regs */ ! 155: for( index = 0; index < 3; index++ ) { ! 156: dbl_ld_acc = cvdf_1_data[index].ld; /* get the operand */ ! 157: sgl_expected = cvdf_1_data[index].exp; /* get expected result */ ! 158: status_index = 0; ! 159: do { ! 160: sgl_dummy1 = status_array[status_index]; /* +, -, 0 status */ ! 161: /* ! 162: * If LOOP ON ERROR is set, this is the loop for this subtest. ! 163: * The force loop flag is set after the first error. ! 164: */ ! 165: asm("_cvdf_3_lp1:"); ! 166: asm("ldd _dbl_ld_acc"); /* load the data */ ! 167: asm("tstl _sgl_dummy1"); /* set the PSL status */ ! 168: asm("movpsl _init_psl"); /* save the initial PSL */ ! 169: asm("nop"); ! 170: asm("cvdf"); /* convert the value */ ! 171: asm("nop"); ! 172: asm("movpsl _psl_val"); /* save the final PSL */ ! 173: if( force_loop ) ! 174: asm("brb _cvdf_3_lp1");; /* loop on the error */ ! 175: /* ! 176: * Now compare the final PSL to the initial PSL -they should be the same ! 177: */ ! 178: exp_psl = init_psl; ! 179: exp_psl &= 0xffffff7f; ! 180: if( psl_val != exp_psl ) { ! 181: errcnt++; /* bump the error count */ ! 182: if( prt_error ) { ! 183: writes(" \n"); /* start a new line */ ! 184: writes("cycle: "); ! 185: writed( cycle ); ! 186: writes(" CVDF test "); ! 187: writed( test_no ); ! 188: writes(", subtest 3 - INCORRECT FINAL PSL\n"); ! 189: print_cvdf_data(); /* print the operands */ ! 190: writes("initial PSL = "); ! 191: write32h( init_psl ); ! 192: writes(", final PSL = "); ! 193: write32h( psl_val ); ! 194: writes(", expected PSL = "); ! 195: write32h( exp_psl ); ! 196: writes("\n"); ! 197: } ! 198: if( halt_flg ) ! 199: cvdf_er_halt( BAD_PSL_HLT ); /* halt on error */ ! 200: if( loop_on_err ) { ! 201: force_loop = TRUE; /* set force loop flag */ ! 202: asm("brw _cvdf_3_lp1");; /* and loop */ ! 203: } /* end of loop on error */ ! 204: } /* end of PSL corruption error */ ! 205: } while( ++status_index < 3 ); /* end of status loop */ ! 206: } while( index++ < max_cvdf_1_index ); /* end of WHILE loop */ ! 207: } /* end of subtest 3 */ ! 208: ! 209: ! 210: ! 211: /************************************************************************** ! 212: * ! 213: * PRINT THE DATA AND STORE RESULTS ! 214: * ! 215: * initial Acc = xxxxxxxx xxxxxxxx, stored = xxxxxxxx xxxxxxxx, index = xx ! 216: **************************************************************************/ ! 217: print_cvdf_data() ! 218: { ! 219: writes("initial Acc = "); ! 220: write32h( dbl_ld_acc.m ); ! 221: writec(' '); ! 222: write32h( dbl_ld_acc.l ); ! 223: writes(", final Acc = "); ! 224: write32h( sgl_st_acc ); ! 225: writes(", index = "); ! 226: writed( index ); ! 227: writec('\n'); ! 228: } ! 229: ! 230: ! 231: ! 232: /************************************************************************** ! 233: * ! 234: * HALT ON ERROR ROUTINE ! 235: * ! 236: **************************************************************************/ ! 237: cvdf_er_halt( halt_code ) ! 238: int halt_code; ! 239: { ! 240: sgl_value_1 = dbl_ld_acc.m; ! 241: sgl_value_2 = dbl_ld_acc.l; ! 242: sgl_value_3 = sgl_st_acc; ! 243: sgl_dummy1 = halt_code; /* get the error type */ ! 244: asm("movl _test_no,r0"); /* r0 = test number */ ! 245: asm("movl _subtest,r1"); /* r1 = subtest number */ ! 246: asm("movl _sgl_dummy1,r2"); /* r2 = error code */ ! 247: asm("movl _cycle,r3"); /* r3 = cycle count */ ! 248: asm("movl _sgl_value_1,r4"); /* r4 = MS accumulator */ ! 249: asm("movl _sgl_value_2,r5"); /* r5 = LS accumulator */ ! 250: asm("movl _sgl_value_3,r6"); /* r6 = final acc */ ! 251: if( halt_code == BAD_ACC_HLT ) { ! 252: sgl_value_1 = sgl_expected; ! 253: asm("movl _sgl_value_1,r7"); /* r7 = expected acc */ ! 254: asm("movl _index,r8"); /* r8 = data index */ ! 255: } else ! 256: if( halt_code == BAD_REG_HLT ) { ! 257: sgl_dummy1 = load_regs[index2]; ! 258: sgl_dummy2 = store_regs[index2]; ! 259: asm("movl _index2,r7"); /* r7 = bad register # */ ! 260: asm("movl _sgl_dummy2,r8"); /* r8 = actual value */ ! 261: asm("movl _sgl_dummy1,r9"); /* r9 = expected value */ ! 262: } else ! 263: if( halt_code == BAD_PSL_HLT ) { ! 264: asm("movl _init_psl,r7"); /* r7 = initial PSL */ ! 265: asm("movl _psl_val,r8"); /* r8 = final PSL */ ! 266: asm("movl _exp_psl,r9"); /* r9 = expected PSL */ ! 267: }; ! 268: asm("halt"); /* HALT ... */ ! 269: }
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