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Power 6/32 Unix version 1.21
#include "fpp_defs.h"
/*****************************************************************************
*
* CVDF - SINGLE PRECISION FLOATING POINT CONVERT LONG TO FLOAT TEST
*
*****************************************************************************/
cvdf()
{
asm(".globl _cvdf_t");
asm("_cvdf_t:"); /* entry address */
if( ( cycle == 1 ) && ( prt_hdrs ) ) /* print headers on 1st pass */
writes("\n CVDF");
cvdf_1(); /* load through a register */
cvdf_2(); /* register stability */
cvdf_3(); /* PSL stability test */
asm("jmp *return"); /* return to the test monitor */
}
/************************************************************************
*
* SUBTEST 1
*
************************************************************************/
cvdf_1()
{
force_loop = FALSE;
subtest = 1;
index = 0;
do {
dbl_ld_acc = cvdf_1_data[index].ld; /* get the operand */
sgl_expected = cvdf_1_data[index].exp; /* get expected result */
if( (dbl_ld_acc.m & 0x7f800000) ) {
sgl_expected = dbl_ld_acc.m;
if( dbl_ld_acc.l & 0x80000000)
sgl_expected++;
}
/*
* If LOOP ON ERROR is set, this is the loop for this subtest.
* The force loop flag is set after the first error.
*/
asm("_cvdf_1_lp1:");
asm("movl _dbl_ld_acc,r4"); /* get the value to convert */
asm("movl _dbl_ld_acc+4,r5");
asm("ldd r4"); /* load the data */
asm("cvdf"); /* convert the value */
asm("stf r8"); /* store the result */
if( force_loop )
asm("brb _cvdf_1_lp1");; /* loop on the error */
/*
* end error loop - test the results
*/
asm("movl r8,_sgl_st_acc"); /* move result to cache */
if( sgl_st_acc != sgl_expected ) { /* COMPARE the values */
errcnt++; /* bump the error count */
if( prt_error ) {
writes(" \n"); /* start a new print line */
writes("cycle: ");
writed( cycle );
writes(" CVDF test ");
writed( test_no );
writes(", subtest 1 (Reg. Data) - BAD FINAL ACC\n");
print_cvdf_data();
writes(" Acc expected = ");
write32h( sgl_expected );
writec('\n');
}
if( halt_flg )
cvdf_er_halt( BAD_ACC_HLT ); /* halt on the error */
if( loop_on_err ) {
force_loop = TRUE; /* set the force loop flag */
asm("brw _cvdf_1_lp1");; /* and loop on the error */
} /* end of loop on error */
} /* end of compare error */
} while( index++ < max_cvdf_1_index ); /* end of WHILE loop */
} /* end of subtest 1 */
/************************************************************************
*
* SUBTEST 2 - Check for register corruption
*
************************************************************************/
cvdf_2()
{
force_loop = FALSE; /* clear force_loop flg */
subtest = 2;
fill_reg_buf( load_regs ); /* get patterns for regs */
index = 0;
dbl_ld_acc = cvdf_1_data[index].ld; /* get the operand */
sgl_expected = cvdf_1_data[index].exp; /* get expected result */
/*
* If LOOP ON ERROR is set, this is the loop for this subtest.
* The force loop flag is set after the first error.
*/
asm("_cvdf_2_lp1:");
asm("ldd _dbl_ld_acc"); /* load the data */
asm("loadr $0x1fff,_load_regs"); /* load regs 0 - 12 */
asm("nop");
asm("cvdf"); /* convert the value */
asm("nop");
asm("storer $0x1fff,_store_regs"); /* store regs 0 - 12 */
if( force_loop )
asm("brb _cvdf_2_lp1");; /* loop on the error */
/*
* Now compare the stored register values to those that were loaded
*/
index2 = 0;
while( (load_regs[index2] == store_regs[index2]) && (index2 < 13) )
index2++; /* check reg values */
if( index2 < 13 ) { /* error if index2 < 13 */
errcnt++; /* bump the error count */
if( prt_error ) {
writes(" \n"); /* start a new print line */
writes("cycle: ");
writed( cycle );
writes(" CVDF test ");
writed( test_no );
writes(", subtest 2 - A REGISTER WAS MODIFIED\n");
print_cvdf_data(); /* print the operands */
writes("register "); /* print the information */
writed( index2 ); /* about the corrupted */
writes(" = "); /* register */
write32h( store_regs[index2] );
writes(", should be = ");
write32h( load_regs[index2] );
writes("\n");
}
if( halt_flg )
cvdf_er_halt( BAD_REG_HLT ); /* halt on the error */
if( loop_on_err ) {
force_loop = TRUE; /* set the force loop flag */
asm("brw _cvdf_2_lp1");; /* and loop on the error */
} /* end of loop on error */
} while( index++ < max_cvdf_1_index ); /* end of reg corruption error */
} /* end of subtest 2 */
/************************************************************************
*
* SUBTEST 3 - Check for PSL corruption
*
************************************************************************/
cvdf_3()
{
force_loop = FALSE; /* clear force_loop flg */
subtest = 3;
fill_reg_buf( load_regs ); /* get patterns for regs */
for( index = 0; index < 3; index++ ) {
dbl_ld_acc = cvdf_1_data[index].ld; /* get the operand */
sgl_expected = cvdf_1_data[index].exp; /* get expected result */
status_index = 0;
do {
sgl_dummy1 = status_array[status_index]; /* +, -, 0 status */
/*
* If LOOP ON ERROR is set, this is the loop for this subtest.
* The force loop flag is set after the first error.
*/
asm("_cvdf_3_lp1:");
asm("ldd _dbl_ld_acc"); /* load the data */
asm("tstl _sgl_dummy1"); /* set the PSL status */
asm("movpsl _init_psl"); /* save the initial PSL */
asm("nop");
asm("cvdf"); /* convert the value */
asm("nop");
asm("movpsl _psl_val"); /* save the final PSL */
if( force_loop )
asm("brb _cvdf_3_lp1");; /* loop on the error */
/*
* Now compare the final PSL to the initial PSL -they should be the same
*/
exp_psl = init_psl;
exp_psl &= 0xffffff7f;
if( psl_val != exp_psl ) {
errcnt++; /* bump the error count */
if( prt_error ) {
writes(" \n"); /* start a new line */
writes("cycle: ");
writed( cycle );
writes(" CVDF test ");
writed( test_no );
writes(", subtest 3 - INCORRECT FINAL PSL\n");
print_cvdf_data(); /* print the operands */
writes("initial PSL = ");
write32h( init_psl );
writes(", final PSL = ");
write32h( psl_val );
writes(", expected PSL = ");
write32h( exp_psl );
writes("\n");
}
if( halt_flg )
cvdf_er_halt( BAD_PSL_HLT ); /* halt on error */
if( loop_on_err ) {
force_loop = TRUE; /* set force loop flag */
asm("brw _cvdf_3_lp1");; /* and loop */
} /* end of loop on error */
} /* end of PSL corruption error */
} while( ++status_index < 3 ); /* end of status loop */
} while( index++ < max_cvdf_1_index ); /* end of WHILE loop */
} /* end of subtest 3 */
/**************************************************************************
*
* PRINT THE DATA AND STORE RESULTS
*
* initial Acc = xxxxxxxx xxxxxxxx, stored = xxxxxxxx xxxxxxxx, index = xx
**************************************************************************/
print_cvdf_data()
{
writes("initial Acc = ");
write32h( dbl_ld_acc.m );
writec(' ');
write32h( dbl_ld_acc.l );
writes(", final Acc = ");
write32h( sgl_st_acc );
writes(", index = ");
writed( index );
writec('\n');
}
/**************************************************************************
*
* HALT ON ERROR ROUTINE
*
**************************************************************************/
cvdf_er_halt( halt_code )
int halt_code;
{
sgl_value_1 = dbl_ld_acc.m;
sgl_value_2 = dbl_ld_acc.l;
sgl_value_3 = sgl_st_acc;
sgl_dummy1 = halt_code; /* get the error type */
asm("movl _test_no,r0"); /* r0 = test number */
asm("movl _subtest,r1"); /* r1 = subtest number */
asm("movl _sgl_dummy1,r2"); /* r2 = error code */
asm("movl _cycle,r3"); /* r3 = cycle count */
asm("movl _sgl_value_1,r4"); /* r4 = MS accumulator */
asm("movl _sgl_value_2,r5"); /* r5 = LS accumulator */
asm("movl _sgl_value_3,r6"); /* r6 = final acc */
if( halt_code == BAD_ACC_HLT ) {
sgl_value_1 = sgl_expected;
asm("movl _sgl_value_1,r7"); /* r7 = expected acc */
asm("movl _index,r8"); /* r8 = data index */
} else
if( halt_code == BAD_REG_HLT ) {
sgl_dummy1 = load_regs[index2];
sgl_dummy2 = store_regs[index2];
asm("movl _index2,r7"); /* r7 = bad register # */
asm("movl _sgl_dummy2,r8"); /* r8 = actual value */
asm("movl _sgl_dummy1,r9"); /* r9 = expected value */
} else
if( halt_code == BAD_PSL_HLT ) {
asm("movl _init_psl,r7"); /* r7 = initial PSL */
asm("movl _psl_val,r8"); /* r8 = final PSL */
asm("movl _exp_psl,r9"); /* r9 = expected PSL */
};
asm("halt"); /* HALT ... */
}
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