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Up to [Power 6/32 Unix Tahoe 4.2BSD] / cci / d / macro4|
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1.1 root 1: 1 00000000 LL0:
2: 2 00000000 .data
3: 3 000006b4 * .text
4: 4 00000000 .align 1
5: 5 00000000 .globl _cvdf
6: 6 00000000 _cvdf:
7: 7 0001E6F0 0000 .word L215
8: 8 0001E6F2 #
9: 9 0001E6F2 # #include "fpp_defs.h"
10: 10 0001E6F2 #
11: 11 0001E6F2 #
12: 12 0001E6F2 # /*****************************************************************************
13: 13 0001E6F2 # *
14: 14 0001E6F2 # * CVDF - SINGLE PRECISION FLOATING POINT CONVERT LONG TO FLOAT TEST
15: 15 0001E6F2 # *
16: 16 0001E6F2 # *****************************************************************************/
17: 17 0001E6F2 # cvdf()
18: 18 0001E6F2 # {
19: 19 0001E6F2 11 3a jbr L217
20: 20 0001E6F4 L218:
21: 21 0001E6F4 # asm(".globl _cvdf_t");
22: 22 0001E6F4 .globl _cvdf_t
23: 23 0001E6F4 # asm("_cvdf_t:"); /* entry address */
24: 24 0001E6F4 _cvdf_t:
25: 25 0001E6F4 # if( ( cycle == 1 ) && ( prt_hdrs ) ) /* print headers on 1st pass */
26: 26 0001E6F4 1d effffffff6 01 cmpl _cycle,$1
27: 27 0001E6FB 21 15 jneq L219
28: 28 0001E6FD 5d efffffffed tstl _prt_hdrs
29: 29 0001E703 31 0d jeql L219
30: 30 0001E705 # writes("\n CVDF");
31: 31 0001E705 .data 1
32: 32 000006b4 * L221:
33: 33 000006b4 * 0A204356444600 .ascii "\12 CVDF\0"
34: 34 000006bb * .text
35: 35 0001E705 dd 8f000006b4 pushl $L221
36: 36 0001E70B fe 08 efffffffde callf $8,_writes
37: 37 0001E712 # cvdf_1(); /* load through a register */
38: 38 0001E712 L219:
39: 39 0001E712 fe 04 ef00000017 callf $4,_cvdf_1
40: 40 0001E719 # cvdf_2(); /* register stability */
41: 41 0001E719 fe 04 ef0000017e callf $4,_cvdf_2
42: 42 0001E720 # cvdf_3(); /* PSL stability test */
43: 43 0001E720 fe 04 ef00000343 callf $4,_cvdf_3
44: 44 0001E727 # asm("jmp *return"); /* return to the test monitor */
45: 45 0001E727 71 ffffffffc3 jmp *return
46: 46 0001E72D # }
47: 47 0001E72D 40 ret#2
48: 48 0001E72E .set L215,0x0
49: 49 0001E72E L217:
50: 50 0001E72E 11 c4 jbr L218
51: 51 0001E730 .data
52: 52 000006b4 * .text
53: 53 0001E730 .align 1
54: 54 0001E730 .globl _cvdf_1
55: 55 0001E730 _cvdf_1:
56: 56 0001E730 0000 .word L225
57: 57 0001E732 #
58: 58 0001E732 #
59: 59 0001E732 #
60: 60 0001E732 # /************************************************************************
61: 61 0001E732 # *
62: 62 0001E732 # * SUBTEST 1
63: 63 0001E732 # *
64: 64 0001E732 # ************************************************************************/
65: 65 0001E732 # cvdf_1()
66: 66 0001E732 # {
67: 67 0001E732 13 0166 jbr L227
68: 68 0001E735 L228:
69: 69 0001E735 # force_loop = FALSE;
70: 70 0001E735 4d efffffffb5 clrl _force_loop
71: 71 0001E73B # subtest = 1;
72: 72 0001E73B 0d 01 efffffffae movl $1,_subtest
73: 73 0001E742 # index = 0;
74: 74 0001E742 4d efffffffa8 clrl _index
75: 75 0001E748 # do {
76: 76 0001E748 L231:
77: 77 0001E748 # dbl_ld_acc = cvdf_1_data[index].ld; /* get the operand */
78: 78 0001E748 5c 0c efffffffa1 50 mull3 $12,_index,r0
79: 79 0001E750 0c 8f00000000 50 addl2 $_cvdf_1_data,r0
80: 80 0001E757 0d a004 efffffff95 movl 4(r0),_dbl_ld_acc+4
81: 81 0001E75F 0d 60 efffffff8a movl (r0),_dbl_ld_acc
82: 82 0001E766 # sgl_expected = cvdf_1_data[index].exp; /* get expected result */
83: 83 0001E766 5c 0c efffffff83 50 mull3 $12,_index,r0
84: 84 0001E76E 0d e000000008 efffffff77 movl _cvdf_1_data+8(r0),_sgl_expected
85: 85 0001E779 # if( (dbl_ld_acc.m & 0x7f800000) ) {
86: 86 0001E779 3d 8f7f800000 efffffff6c bitl $2139095040,_dbl_ld_acc
87: 87 0001E784 31 1e jeql L232
88: 88 0001E786 # sgl_expected = dbl_ld_acc.m;
89: 89 0001E786 0d efffffff64 efffffff5f movl _dbl_ld_acc,_sgl_expected
90: 90 0001E791 # if( dbl_ld_acc.l & 0x80000000)
91: 91 0001E791 3d 8f80000000 efffffff58 bitl $-2147483648,_dbl_ld_acc+4
92: 92 0001E79C 31 06 jeql L233
93: 93 0001E79E # sgl_expected++;
94: 94 0001E79E 6d efffffff4c incl _sgl_expected
95: 95 0001E7A4 # }
96: 96 0001E7A4 L233:
97: 97 0001E7A4 # /*
98: 98 0001E7A4 # * If LOOP ON ERROR is set, this is the loop for this subtest.
99: 99 0001E7A4 # * The force loop flag is set after the first error.
100: 100 0001E7A4 # */
101: 101 0001E7A4 # asm("_cvdf_1_lp1:");
102: 102 0001E7A4 L232:
103: 103 0001E7A4 _cvdf_1_lp1:
104: 104 0001E7A4 # asm("movl _dbl_ld_acc,r4"); /* get the value to convert */
105: 105 0001E7A4 0d efffffff46 54 movl _dbl_ld_acc,r4
106: 106 0001E7AB # asm("movl _dbl_ld_acc+4,r5");
107: 107 0001E7AB 0d efffffff43 55 movl _dbl_ld_acc+4,r5
108: 108 0001E7B2 # asm("ldd r4"); /* load the data */
109: 109 0001E7B2 07 54 ldd r4
110: 110 0001E7B4 # asm("cvdf"); /* convert the value */
111: 111 0001E7B4 a6 cvdf
112: 112 0001E7B5 # asm("stf r8"); /* store the result */
113: 113 0001E7B5 26 58 stf r8
114: 114 0001E7B7 # if( force_loop )
115: 115 0001E7B7 5d efffffff33 tstl _force_loop
116: 116 0001E7BD 31 02 jeql L234
117: 117 0001E7BF # asm("brb _cvdf_1_lp1");; /* loop on the error */
118: 118 0001E7BF 11 e3 brb _cvdf_1_lp1
119: 119 0001E7C1 L234:
120: 120 0001E7C1 # /*
121: 121 0001E7C1 # * end error loop - test the results
122: 122 0001E7C1 # */
123: 123 0001E7C1 # asm("movl r8,_sgl_st_acc"); /* move result to cache */
124: 124 0001E7C1 0d 58 efffffff28 movl r8,_sgl_st_acc
125: 125 0001E7C8 # if( sgl_st_acc != sgl_expected ) { /* COMPARE the values */
126: 126 0001E7C8 1d efffffff22 efffffff1d cmpl _sgl_st_acc,_sgl_expected
127: 127 0001E7D3 21 03 13 00a9 jeql L235
128: 128 0001E7D8 # errcnt++; /* bump the error count */
129: 129 0001E7D8 6d efffffff12 incl _errcnt
130: 130 0001E7DE # if( prt_error ) {
131: 131 0001E7DE 5d efffffff0c tstl _prt_error
132: 132 0001E7E4 31 78 jeql L236
133: 133 0001E7E6 # writes(" \n"); /* start a new print line */
134: 134 0001E7E6 .data 1
135: 135 000006bb * L237:
136: 136 000006bb * 200A00 .ascii " \12\0"
137: 137 000006be * .text
138: 138 0001E7E6 dd 8f000006bb pushl $L237
139: 139 0001E7EC fe 08 effffffefd callf $8,_writes
140: 140 0001E7F3 # writes("cycle: ");
141: 141 0001E7F3 .data 1
142: 142 000006be * L238:
143: 143 000006be * 6379636C653A2000 .ascii "cycle: \0"
144: 144 000006c6 * .text
145: 145 0001E7F3 dd 8f000006be pushl $L238
146: 146 0001E7F9 fe 08 effffffef0 callf $8,_writes
147: 147 0001E800 # writed( cycle );
148: 148 0001E800 dd effffffeea pushl _cycle
149: 149 0001E806 fe 08 effffffee3 callf $8,_writed
150: 150 0001E80D # writes(" CVDF test ");
151: 151 0001E80D .data 1
152: 152 000006c6 * L240:
153: 153 000006c6 * 2020435644462074657374200 .ascii " CVDF test \0"
154: 0
155: 154 000006d3 * .text
156: 155 0001E80D dd 8f000006c6 pushl $L240
157: 156 0001E813 fe 08 effffffed6 callf $8,_writes
158: 157 0001E81A # writed( test_no );
159: 158 0001E81A dd effffffed0 pushl _test_no
160: 159 0001E820 fe 08 effffffec9 callf $8,_writed
161: 160 0001E827 # writes(", subtest 1 (Reg. Data) - BAD FINAL ACC\n");
162: 161 0001E827 .data 1
163: 162 000006d3 * L241:
164: 163 000006d3 * 2C20737562746573742031202 .ascii ", subtest 1 (Reg. Data) - BAD FINAL ACC\12\0"
165: 85265672E204461746129202D
166: 204241442046494E414C20414
167: 3430A00
168: 164 000006fc * .text
169: 165 0001E827 dd 8f000006d3 pushl $L241
170: 166 0001E82D fe 08 effffffebc callf $8,_writes
171: 167 0001E834 # print_cvdf_data();
172: 168 0001E834 fe 04 ef00000411 callf $4,_print_cvdf_data
173: 169 0001E83B # writes(" Acc expected = ");
174: 170 0001E83B .data 1
175: 171 000006fc * L243:
176: 172 000006fc * 2020202020202020202020202 .ascii " Acc expected = \0"
177: 0202020202020202020202020
178: 2020202020204163632065787
179: 06563746564203D2000
180: 173 0000072b * .text
181: 174 0001E83B dd 8f000006fc pushl $L243
182: 175 0001E841 fe 08 effffffea8 callf $8,_writes
183: 176 0001E848 # write32h( sgl_expected );
184: 177 0001E848 dd effffffea2 pushl _sgl_expected
185: 178 0001E84E fe 08 effffffe9b callf $8,_write32h
186: 179 0001E855 # writec('\n');
187: 180 0001E855 dd 0a pushl $10
188: 181 0001E857 fe 08 effffffe92 callf $8,_writec
189: 182 0001E85E # }
190: 183 0001E85E # if( halt_flg )
191: 184 0001E85E L236:
192: 185 0001E85E 5d effffffe8c tstl _halt_flg
193: 186 0001E864 31 09 jeql L246
194: 187 0001E866 # cvdf_er_halt( BAD_ACC_HLT ); /* halt on the error */
195: 188 0001E866 dd 01 pushl $1
196: 189 0001E868 fe 08 ef00000451 callf $8,_cvdf_er_halt
197: 190 0001E86F # if( loop_on_err ) {
198: 191 0001E86F L246:
199: 192 0001E86F 5d effffffe7b tstl _loop_on_err
200: 193 0001E875 31 0a jeql L248
201: 194 0001E877 # force_loop = TRUE; /* set the force loop flag */
202: 195 0001E877 0d 01 effffffe72 movl $1,_force_loop
203: 196 0001E87E # asm("brw _cvdf_1_lp1");; /* and loop on the error */
204: 197 0001E87E 13 ff23 brw _cvdf_1_lp1
205: 198 0001E881 # } /* end of loop on error */
206: 199 0001E881 # } /* end of compare error */
207: 200 0001E881 L248:
208: 201 0001E881 # } while( index++ < max_cvdf_1_index ); /* end of WHILE loop */
209: 202 0001E881 L235:
210: 203 0001E881 L230:
211: 204 0001E881 0d effffffe69 50 movl _index,r0
212: 205 0001E888 6d effffffe62 incl _index
213: 206 0001E88E 1d 50 effffffe5b cmpl r0,_max_cvdf_1_index
214: 207 0001E895 81 03 13 feae jlss L231
215: 208 0001E89A L229:
216: 209 0001E89A # } /* end of subtest 1 */
217: 210 0001E89A 40 ret#2
218: 211 0001E89B .set L225,0x0
219: 212 0001E89B L227:
220: 213 0001E89B 13 fe97 jbr L228
221: 214 0001E89E .data
222: 215 000006b4 * .text
223: 216 0001E89E .align 1
224: 217 0001E89E .globl _cvdf_2
225: 218 0001E89E _cvdf_2:
226: 219 0001E89E 0000 .word L249
227: 220 0001E8A0 #
228: 221 0001E8A0 #
229: 222 0001E8A0 #
230: 223 0001E8A0 # /************************************************************************
231: 224 0001E8A0 # *
232: 225 0001E8A0 # * SUBTEST 2 - Check for register corruption
233: 226 0001E8A0 # *
234: 227 0001E8A0 # ************************************************************************/
235: 228 0001E8A0 # cvdf_2()
236: 229 0001E8A0 # {
237: 230 0001E8A0 13 01c3 jbr L251
238: 231 0001E8A3 L252:
239: 232 0001E8A3 # force_loop = FALSE; /* clear force_loop flg */
240: 233 0001E8A3 4d effffffe47 clrl _force_loop
241: 234 0001E8A9 # subtest = 2;
242: 235 0001E8A9 0d 02 effffffe40 movl $2,_subtest
243: 236 0001E8B0 # fill_reg_buf( load_regs ); /* get patterns for regs */
244: 237 0001E8B0 dd 8f00000000 pushl $_load_regs
245: 238 0001E8B6 fe 08 effffffe33 callf $8,_fill_reg_buf
246: 239 0001E8BD # index = 0;
247: 240 0001E8BD 4d effffffe2d clrl _index
248: 241 0001E8C3 # dbl_ld_acc = cvdf_1_data[index].ld; /* get the operand */
249: 242 0001E8C3 5c 0c effffffe26 50 mull3 $12,_index,r0
250: 243 0001E8CB 0c 8f00000000 50 addl2 $_cvdf_1_data,r0
251: 244 0001E8D2 0d a004 effffffe1a movl 4(r0),_dbl_ld_acc+4
252: 245 0001E8DA 0d 60 effffffe0f movl (r0),_dbl_ld_acc
253: 246 0001E8E1 # sgl_expected = cvdf_1_data[index].exp; /* get expected result */
254: 247 0001E8E1 5c 0c effffffe08 50 mull3 $12,_index,r0
255: 248 0001E8E9 0d e000000008 effffffdfc movl _cvdf_1_data+8(r0),_sgl_expected
256: 249 0001E8F4 # /*
257: 250 0001E8F4 # * If LOOP ON ERROR is set, this is the loop for this subtest.
258: 251 0001E8F4 # * The force loop flag is set after the first error.
259: 252 0001E8F4 # */
260: 253 0001E8F4 # asm("_cvdf_2_lp1:");
261: 254 0001E8F4 _cvdf_2_lp1:
262: 255 0001E8F4 # asm("ldd _dbl_ld_acc"); /* load the data */
263: 256 0001E8F4 07 effffffdf6 ldd _dbl_ld_acc
264: 257 0001E8FA # asm("loadr $0x1fff,_load_regs"); /* load regs 0 - 12 */
265: 258 0001E8FA ab 891fff effffffded loadr $0x1fff,_load_regs
266: 259 0001E903 # asm("nop");
267: 260 0001E903 10 nop
268: 261 0001E904 # asm("cvdf"); /* convert the value */
269: 262 0001E904 a6 cvdf
270: 263 0001E905 # asm("nop");
271: 264 0001E905 10 nop
272: 265 0001E906 # asm("storer $0x1fff,_store_regs"); /* store regs 0 - 12 */
273: 266 0001E906 bb 891fff effffffde1 storer $0x1fff,_store_regs
274: 267 0001E90F # if( force_loop )
275: 268 0001E90F 5d effffffddb tstl _force_loop
276: 269 0001E915 31 02 jeql L254
277: 270 0001E917 # asm("brb _cvdf_2_lp1");; /* loop on the error */
278: 271 0001E917 11 db brb _cvdf_2_lp1
279: 272 0001E919 L254:
280: 273 0001E919 # /*
281: 274 0001E919 # * Now compare the stored register values to those that were loaded
282: 275 0001E919 # */
283: 276 0001E919 # index2 = 0;
284: 277 0001E919 4d effffffdd1 clrl _index2
285: 278 0001E91F # while( (load_regs[index2] == store_regs[index2]) && (index2 < 13) )
286: 279 0001E91F L255:
287: 280 0001E91F 0d effffffdcb 50 movl _index2,r0
288: 281 0001E926 0d effffffdc4 51 movl _index2,r1
289: 282 0001E92D 1d 40effffffdbc cmpl _load_regs[r0],_store_regs[r1]
290: 41effffffdb6
291: 283 0001E93A 21 11 jneq L256
292: 284 0001E93C 1d effffffdae 0d cmpl _index2,$13
293: 285 0001E943 81 08 jgeq L256
294: 286 0001E945 # index2++; /* check reg values */
295: 287 0001E945 6d effffffda5 incl _index2
296: 288 0001E94B 11 d2 jbr L255
297: 289 0001E94D L256:
298: 290 0001E94D # if( index2 < 13 ) { /* error if index2 < 13 */
299: 291 0001E94D 1d effffffd9d 0d cmpl _index2,$13
300: 292 0001E954 91 03 13 00f4 jgeq L257
301: 293 0001E959 # errcnt++; /* bump the error count */
302: 294 0001E959 6d effffffd91 incl _errcnt
303: 295 0001E95F # if( prt_error ) {
304: 296 0001E95F 5d effffffd8b tstl _prt_error
305: 297 0001E965 21 03 13 00c0 jeql L258
306: 298 0001E96A # writes(" \n"); /* start a new print line */
307: 299 0001E96A .data 1
308: 300 0000072b * L259:
309: 301 0000072b * 200A00 .ascii " \12\0"
310: 302 0000072e * .text
311: 303 0001E96A dd 8f0000072b pushl $L259
312: 304 0001E970 fe 08 effffffd79 callf $8,_writes
313: 305 0001E977 # writes("cycle: ");
314: 306 0001E977 .data 1
315: 307 0000072e * L260:
316: 308 0000072e * 6379636C653A2000 .ascii "cycle: \0"
317: 309 00000736 * .text
318: 310 0001E977 dd 8f0000072e pushl $L260
319: 311 0001E97D fe 08 effffffd6c callf $8,_writes
320: 312 0001E984 # writed( cycle );
321: 313 0001E984 dd effffffd66 pushl _cycle
322: 314 0001E98A fe 08 effffffd5f callf $8,_writed
323: 315 0001E991 # writes(" CVDF test ");
324: 316 0001E991 .data 1
325: 317 00000736 * L261:
326: 318 00000736 * 2020435644462074657374200 .ascii " CVDF test \0"
327: 0
328: 319 00000743 * .text
329: 320 0001E991 dd 8f00000736 pushl $L261
330: 321 0001E997 fe 08 effffffd52 callf $8,_writes
331: 322 0001E99E # writed( test_no );
332: 323 0001E99E dd effffffd4c pushl _test_no
333: 324 0001E9A4 fe 08 effffffd45 callf $8,_writed
334: 325 0001E9AB # writes(", subtest 2 - A REGISTER WAS MODIFIED\n");
335: 326 0001E9AB .data 1
336: 327 00000743 * L262:
337: 328 00000743 * 2C20737562746573742032202 .ascii ", subtest 2 - A REGISTER WAS MODIFIED\12\0"
338: D204120524547495354455220
339: 574153204D4F4449464945440
340: A00
341: 329 0000076a * .text
342: 330 0001E9AB dd 8f00000743 pushl $L262
343: 331 0001E9B1 fe 08 effffffd38 callf $8,_writes
344: 332 0001E9B8 # print_cvdf_data(); /* print the operands */
345: 333 0001E9B8 fe 04 ef0000028d callf $4,_print_cvdf_data
346: 334 0001E9BF # writes("register "); /* print the information */
347: 335 0001E9BF .data 1
348: 336 0000076a * L263:
349: 337 0000076a * 72656769737465722000 .ascii "register \0"
350: 338 00000774 * .text
351: 339 0001E9BF dd 8f0000076a pushl $L263
352: 340 0001E9C5 fe 08 effffffd24 callf $8,_writes
353: 341 0001E9CC # writed( index2 ); /* about the corrupted */
354: 342 0001E9CC dd effffffd1e pushl _index2
355: 343 0001E9D2 fe 08 effffffd17 callf $8,_writed
356: 344 0001E9D9 # writes(" = "); /* register */
357: 345 0001E9D9 .data 1
358: 346 00000774 * L264:
359: 347 00000774 * 203D2000 .ascii " = \0"
360: 348 00000778 * .text
361: 349 0001E9D9 dd 8f00000774 pushl $L264
362: 350 0001E9DF fe 08 effffffd0a callf $8,_writes
363: 351 0001E9E6 # write32h( store_regs[index2] );
364: 352 0001E9E6 0d effffffd04 50 movl _index2,r0
365: 353 0001E9ED dd 40effffffcfc pushl _store_regs[r0]
366: 354 0001E9F4 fe 08 effffffcf5 callf $8,_write32h
367: 355 0001E9FB # writes(", should be = ");
368: 356 0001E9FB .data 1
369: 357 00000778 * L265:
370: 358 00000778 * 2C202073686F756C642062652 .ascii ", should be = \0"
371: 03D2000
372: 359 00000788 * .text
373: 360 0001E9FB dd 8f00000778 pushl $L265
374: 361 0001EA01 fe 08 effffffce8 callf $8,_writes
375: 362 0001EA08 # write32h( load_regs[index2] );
376: 363 0001EA08 0d effffffce2 50 movl _index2,r0
377: 364 0001EA0F dd 40effffffcda pushl _load_regs[r0]
378: 365 0001EA16 fe 08 effffffcd3 callf $8,_write32h
379: 366 0001EA1D # writes("\n");
380: 367 0001EA1D .data 1
381: 368 00000788 * L266:
382: 369 00000788 * 0A00 .ascii "\12\0"
383: 370 0000078a * .text
384: 371 0001EA1D dd 8f00000788 pushl $L266
385: 372 0001EA23 fe 08 effffffcc6 callf $8,_writes
386: 373 0001EA2A # }
387: 374 0001EA2A # if( halt_flg )
388: 375 0001EA2A L258:
389: 376 0001EA2A 5d effffffcc0 tstl _halt_flg
390: 377 0001EA30 31 09 jeql L267
391: 378 0001EA32 # cvdf_er_halt( BAD_REG_HLT ); /* halt on the error */
392: 379 0001EA32 dd 02 pushl $2
393: 380 0001EA34 fe 08 ef00000285 callf $8,_cvdf_er_halt
394: 381 0001EA3B # if( loop_on_err ) {
395: 382 0001EA3B L267:
396: 383 0001EA3B 5d effffffcaf tstl _loop_on_err
397: 384 0001EA41 31 0a jeql L268
398: 385 0001EA43 # force_loop = TRUE; /* set the force loop flag */
399: 386 0001EA43 0d 01 effffffca6 movl $1,_force_loop
400: 387 0001EA4A # asm("brw _cvdf_2_lp1");; /* and loop on the error */
401: 388 0001EA4A 13 fea7 brw _cvdf_2_lp1
402: 389 0001EA4D # } /* end of loop on error */
403: 390 0001EA4D # } while( index++ < max_cvdf_1_index ); /* end of reg corruption error */
404: 391 0001EA4D L268:
405: 392 0001EA4D L257:
406: 393 0001EA4D L269:
407: 394 0001EA4D 0d effffffc9d 50 movl _index,r0
408: 395 0001EA54 6d effffffc96 incl _index
409: 396 0001EA5A 1d 50 effffffc8f cmpl r0,_max_cvdf_1_index
410: 397 0001EA61 81 02 jgeq L270
411: 398 0001EA63 11 e8 jbr L269
412: 399 0001EA65 L270:
413: 400 0001EA65 # } /* end of subtest 2 */
414: 401 0001EA65 40 ret#2
415: 402 0001EA66 .set L249,0x0
416: 403 0001EA66 L251:
417: 404 0001EA66 13 fe3a jbr L252
418: 405 0001EA69 .data
419: 406 000006b4 * .text
420: 407 0001EA69 00 .align 1
421: 408 0001EA6A .globl _cvdf_3
422: 409 0001EA6A _cvdf_3:
423: 410 0001EA6A 0000 .word L271
424: 411 0001EA6C #
425: 412 0001EA6C #
426: 413 0001EA6C #
427: 414 0001EA6C # /************************************************************************
428: 415 0001EA6C # *
429: 416 0001EA6C # * SUBTEST 3 - Check for PSL corruption
430: 417 0001EA6C # *
431: 418 0001EA6C # ************************************************************************/
432: 419 0001EA6C # cvdf_3()
433: 420 0001EA6C # {
434: 421 0001EA6C 13 01da jbr L273
435: 422 0001EA6F L274:
436: 423 0001EA6F # force_loop = FALSE; /* clear force_loop flg */
437: 424 0001EA6F 4d effffffc7b clrl _force_loop
438: 425 0001EA75 # subtest = 3;
439: 426 0001EA75 0d 03 effffffc74 movl $3,_subtest
440: 427 0001EA7C # fill_reg_buf( load_regs ); /* get patterns for regs */
441: 428 0001EA7C dd 8f00000000 pushl $_load_regs
442: 429 0001EA82 fe 08 effffffc67 callf $8,_fill_reg_buf
443: 430 0001EA89 # for( index = 0; index < 3; index++ ) {
444: 431 0001EA89 4d effffffc61 clrl _index
445: 432 0001EA8F L277:
446: 433 0001EA8F 1d effffffc5b 03 cmpl _index,$3
447: 434 0001EA96 91 03 13 0195 jgeq L276
448: 435 0001EA9B # dbl_ld_acc = cvdf_1_data[index].ld; /* get the operand */
449: 436 0001EA9B 5c 0c effffffc4e 50 mull3 $12,_index,r0
450: 437 0001EAA3 0c 8f00000000 50 addl2 $_cvdf_1_data,r0
451: 438 0001EAAA 0d a004 effffffc42 movl 4(r0),_dbl_ld_acc+4
452: 439 0001EAB2 0d 60 effffffc37 movl (r0),_dbl_ld_acc
453: 440 0001EAB9 # sgl_expected = cvdf_1_data[index].exp; /* get expected result */
454: 441 0001EAB9 5c 0c effffffc30 50 mull3 $12,_index,r0
455: 442 0001EAC1 0d e000000008 effffffc24 movl _cvdf_1_data+8(r0),_sgl_expected
456: 443 0001EACC # status_index = 0;
457: 444 0001EACC 4d effffffc1e clrl _status_index
458: 445 0001EAD2 # do {
459: 446 0001EAD2 L280:
460: 447 0001EAD2 # sgl_dummy1 = status_array[status_index]; /* +, -, 0 status */
461: 448 0001EAD2 0d effffffc18 50 movl _status_index,r0
462: 449 0001EAD9 0d 40effffffc10 movl _status_array[r0],_sgl_dummy1
463: effffffc0b
464: 450 0001EAE5 # /*
465: 451 0001EAE5 # * If LOOP ON ERROR is set, this is the loop for this subtest.
466: 452 0001EAE5 # * The force loop flag is set after the first error.
467: 453 0001EAE5 # */
468: 454 0001EAE5 # asm("_cvdf_3_lp1:");
469: 455 0001EAE5 _cvdf_3_lp1:
470: 456 0001EAE5 # asm("ldd _dbl_ld_acc"); /* load the data */
471: 457 0001EAE5 07 effffffc05 ldd _dbl_ld_acc
472: 458 0001EAEB # asm("tstl _sgl_dummy1"); /* set the PSL status */
473: 459 0001EAEB 5d effffffbff tstl _sgl_dummy1
474: 460 0001EAF1 # asm("movpsl _init_psl"); /* save the initial PSL */
475: 461 0001EAF1 cd effffffbf9 movpsl _init_psl
476: 462 0001EAF7 # asm("nop");
477: 463 0001EAF7 10 nop
478: 464 0001EAF8 # asm("cvdf"); /* convert the value */
479: 465 0001EAF8 a6 cvdf
480: 466 0001EAF9 # asm("nop");
481: 467 0001EAF9 10 nop
482: 468 0001EAFA # asm("movpsl _psl_val"); /* save the final PSL */
483: 469 0001EAFA cd effffffbf0 movpsl _psl_val
484: 470 0001EB00 # if( force_loop )
485: 471 0001EB00 5d effffffbea tstl _force_loop
486: 472 0001EB06 31 02 jeql L281
487: 473 0001EB08 # asm("brb _cvdf_3_lp1");; /* loop on the error */
488: 474 0001EB08 11 db brb _cvdf_3_lp1
489: 475 0001EB0A L281:
490: 476 0001EB0A # /*
491: 477 0001EB0A # * Now compare the final PSL to the initial PSL -they should be the same
492: 478 0001EB0A # */
493: 479 0001EB0A # exp_psl = init_psl;
494: 480 0001EB0A 0d effffffbe0 effffffbdb movl _init_psl,_exp_psl
495: 481 0001EB15 # exp_psl &= 0xffffff7f;
496: 482 0001EB15 ac 89ff7f effffffbd2 andl2 $-129,_exp_psl
497: 483 0001EB1E # if( psl_val != exp_psl ) {
498: 484 0001EB1E 1d effffffbcc effffffbc7 cmpl _psl_val,_exp_psl
499: 485 0001EB29 21 03 13 00e4 jeql L282
500: 486 0001EB2E # errcnt++; /* bump the error count */
501: 487 0001EB2E 6d effffffbbc incl _errcnt
502: 488 0001EB34 # if( prt_error ) {
503: 489 0001EB34 5d effffffbb6 tstl _prt_error
504: 490 0001EB3A 21 03 13 00b0 jeql L283
505: 491 0001EB3F # writes(" \n"); /* start a new line */
506: 492 0001EB3F .data 1
507: 493 0000078a * L284:
508: 494 0000078a * 200A00 .ascii " \12\0"
509: 495 0000078d * .text
510: 496 0001EB3F dd 8f0000078a pushl $L284
511: 497 0001EB45 fe 08 effffffba4 callf $8,_writes
512: 498 0001EB4C # writes("cycle: ");
513: 499 0001EB4C .data 1
514: 500 0000078d * L285:
515: 501 0000078d * 6379636C653A2000 .ascii "cycle: \0"
516: 502 00000795 * .text
517: 503 0001EB4C dd 8f0000078d pushl $L285
518: 504 0001EB52 fe 08 effffffb97 callf $8,_writes
519: 505 0001EB59 # writed( cycle );
520: 506 0001EB59 dd effffffb91 pushl _cycle
521: 507 0001EB5F fe 08 effffffb8a callf $8,_writed
522: 508 0001EB66 # writes(" CVDF test ");
523: 509 0001EB66 .data 1
524: 510 00000795 * L286:
525: 511 00000795 * 2020435644462074657374200 .ascii " CVDF test \0"
526: 0
527: 512 000007a2 * .text
528: 513 0001EB66 dd 8f00000795 pushl $L286
529: 514 0001EB6C fe 08 effffffb7d callf $8,_writes
530: 515 0001EB73 # writed( test_no );
531: 516 0001EB73 dd effffffb77 pushl _test_no
532: 517 0001EB79 fe 08 effffffb70 callf $8,_writed
533: 518 0001EB80 # writes(", subtest 3 - INCORRECT FINAL PSL\n");
534: 519 0001EB80 .data 1
535: 520 000007a2 * L287:
536: 521 000007a2 * 2C20737562746573742033202 .ascii ", subtest 3 - INCORRECT FINAL PSL\12\0"
537: 02D20494E434F525245435420
538: 46494E414C2050534C0A00
539: 522 000007c6 * .text
540: 523 0001EB80 dd 8f000007a2 pushl $L287
541: 524 0001EB86 fe 08 effffffb63 callf $8,_writes
542: 525 0001EB8D # print_cvdf_data(); /* print the operands */
543: 526 0001EB8D fe 04 ef000000b8 callf $4,_print_cvdf_data
544: 527 0001EB94 # writes("initial PSL = ");
545: 528 0001EB94 .data 1
546: 529 000007c6 * L288:
547: 530 000007c6 * 696E697469616C2050534C203 .ascii "initial PSL = \0"
548: D2000
549: 531 000007d5 * .text
550: 532 0001EB94 dd 8f000007c6 pushl $L288
551: 533 0001EB9A fe 08 effffffb4f callf $8,_writes
552: 534 0001EBA1 # write32h( init_psl );
553: 535 0001EBA1 dd effffffb49 pushl _init_psl
554: 536 0001EBA7 fe 08 effffffb42 callf $8,_write32h
555: 537 0001EBAE # writes(", final PSL = ");
556: 538 0001EBAE .data 1
557: 539 000007d5 * L289:
558: 540 000007d5 * 2C202066696E616C2050534C2 .ascii ", final PSL = \0"
559: 03D2000
560: 541 000007e5 * .text
561: 542 0001EBAE dd 8f000007d5 pushl $L289
562: 543 0001EBB4 fe 08 effffffb35 callf $8,_writes
563: 544 0001EBBB # write32h( psl_val );
564: 545 0001EBBB dd effffffb2f pushl _psl_val
565: 546 0001EBC1 fe 08 effffffb28 callf $8,_write32h
566: 547 0001EBC8 # writes(", expected PSL = ");
567: 548 0001EBC8 .data 1
568: 549 000007e5 * L290:
569: 550 000007e5 * 2C20206578706563746564205 .ascii ", expected PSL = \0"
570: 0534C203D2000
571: 551 000007f8 * .text
572: 552 0001EBC8 dd 8f000007e5 pushl $L290
573: 553 0001EBCE fe 08 effffffb1b callf $8,_writes
574: 554 0001EBD5 # write32h( exp_psl );
575: 555 0001EBD5 dd effffffb15 pushl _exp_psl
576: 556 0001EBDB fe 08 effffffb0e callf $8,_write32h
577: 557 0001EBE2 # writes("\n");
578: 558 0001EBE2 .data 1
579: 559 000007f8 * L291:
580: 560 000007f8 * 0A00 .ascii "\12\0"
581: 561 000007fa * .text
582: 562 0001EBE2 dd 8f000007f8 pushl $L291
583: 563 0001EBE8 fe 08 effffffb01 callf $8,_writes
584: 564 0001EBEF # }
585: 565 0001EBEF # if( halt_flg )
586: 566 0001EBEF L283:
587: 567 0001EBEF 5d effffffafb tstl _halt_flg
588: 568 0001EBF5 31 09 jeql L292
589: 569 0001EBF7 # cvdf_er_halt( BAD_PSL_HLT ); /* halt on error */
590: 570 0001EBF7 dd 03 pushl $3
591: 571 0001EBF9 fe 08 ef000000c0 callf $8,_cvdf_er_halt
592: 572 0001EC00 # if( loop_on_err ) {
593: 573 0001EC00 L292:
594: 574 0001EC00 5d effffffaea tstl _loop_on_err
595: 575 0001EC06 31 0a jeql L293
596: 576 0001EC08 # force_loop = TRUE; /* set force loop flag */
597: 577 0001EC08 0d 01 effffffae1 movl $1,_force_loop
598: 578 0001EC0F # asm("brw _cvdf_3_lp1");; /* and loop */
599: 579 0001EC0F 13 fed3 brw _cvdf_3_lp1
600: 580 0001EC12 # } /* end of loop on error */
601: 581 0001EC12 # } /* end of PSL corruption error */
602: 582 0001EC12 L293:
603: 583 0001EC12 # } while( ++status_index < 3 ); /* end of status loop */
604: 584 0001EC12 L282:
605: 585 0001EC12 L279:
606: 586 0001EC12 6d effffffad8 incl _status_index
607: 587 0001EC18 0d effffffad2 50 movl _status_index,r0
608: 588 0001EC1F 1d 50 03 cmpl r0,$3
609: 589 0001EC22 81 03 13 feab jlss L280
610: 590 0001EC27 L278:
611: 591 0001EC27 # } while( index++ < max_cvdf_1_index ); /* end of WHILE loop */
612: 592 0001EC27 L275:
613: 593 0001EC27 6d effffffac3 incl _index
614: 594 0001EC2D 13 fe5f jbr L277
615: 595 0001EC30 L276:
616: 596 0001EC30 L294:
617: 597 0001EC30 0d effffffaba 50 movl _index,r0
618: 598 0001EC37 6d effffffab3 incl _index
619: 599 0001EC3D 1d 50 effffffaac cmpl r0,_max_cvdf_1_index
620: 600 0001EC44 81 02 jgeq L295
621: 601 0001EC46 11 e8 jbr L294
622: 602 0001EC48 L295:
623: 603 0001EC48 # } /* end of subtest 3 */
624: 604 0001EC48 40 ret#2
625: 605 0001EC49 .set L271,0x0
626: 606 0001EC49 L273:
627: 607 0001EC49 13 fe23 jbr L274
628: 608 0001EC4C .data
629: 609 000006b4 * .text
630: 610 0001EC4C .align 1
631: 611 0001EC4C .globl _print_cvdf_data
632: 612 0001EC4C _print_cvdf_data:
633: 613 0001EC4C 0000 .word L296
634: 614 0001EC4E #
635: 615 0001EC4E #
636: 616 0001EC4E #
637: 617 0001EC4E # /**************************************************************************
638: 618 0001EC4E # *
639: 619 0001EC4E # * PRINT THE DATA AND STORE RESULTS
640: 620 0001EC4E # *
641: 621 0001EC4E # * initial Acc = xxxxxxxx xxxxxxxx, stored = xxxxxxxx xxxxxxxx, index = xx
642: 622 0001EC4E # **************************************************************************/
643: 623 0001EC4E # print_cvdf_data()
644: 624 0001EC4E # {
645: 625 0001EC4E 11 6e jbr L298
646: 626 0001EC50 L299:
647: 627 0001EC50 # writes("initial Acc = ");
648: 628 0001EC50 .data 1
649: 629 000007fa * L300:
650: 630 000007fa * 696E697469616C20416363203 .ascii "initial Acc = \0"
651: D2000
652: 631 00000809 * .text
653: 632 0001EC50 dd 8f000007fa pushl $L300
654: 633 0001EC56 fe 08 effffffa93 callf $8,_writes
655: 634 0001EC5D # write32h( dbl_ld_acc.m );
656: 635 0001EC5D dd effffffa8d pushl _dbl_ld_acc
657: 636 0001EC63 fe 08 effffffa86 callf $8,_write32h
658: 637 0001EC6A # writec(' ');
659: 638 0001EC6A dd 20 pushl $32
660: 639 0001EC6C fe 08 effffffa7d callf $8,_writec
661: 640 0001EC73 # write32h( dbl_ld_acc.l );
662: 641 0001EC73 dd effffffa7b pushl _dbl_ld_acc+4
663: 642 0001EC79 fe 08 effffffa70 callf $8,_write32h
664: 643 0001EC80 # writes(", final Acc = ");
665: 644 0001EC80 .data 1
666: 645 00000809 * L301:
667: 646 00000809 * 2C202066696E616C204163632 .ascii ", final Acc = \0"
668: 03D2000
669: 647 00000819 * .text
670: 648 0001EC80 dd 8f00000809 pushl $L301
671: 649 0001EC86 fe 08 effffffa63 callf $8,_writes
672: 650 0001EC8D # write32h( sgl_st_acc );
673: 651 0001EC8D dd effffffa5d pushl _sgl_st_acc
674: 652 0001EC93 fe 08 effffffa56 callf $8,_write32h
675: 653 0001EC9A # writes(", index = ");
676: 654 0001EC9A .data 1
677: 655 00000819 * L302:
678: 656 00000819 * 2C2020696E646578203D2000 .ascii ", index = \0"
679: 657 00000825 * .text
680: 658 0001EC9A dd 8f00000819 pushl $L302
681: 659 0001ECA0 fe 08 effffffa49 callf $8,_writes
682: 660 0001ECA7 # writed( index );
683: 661 0001ECA7 dd effffffa43 pushl _index
684: 662 0001ECAD fe 08 effffffa3c callf $8,_writed
685: 663 0001ECB4 # writec('\n');
686: 664 0001ECB4 dd 0a pushl $10
687: 665 0001ECB6 fe 08 effffffa33 callf $8,_writec
688: 666 0001ECBD # }
689: 667 0001ECBD 40 ret#2
690: 668 0001ECBE .set L296,0x0
691: 669 0001ECBE L298:
692: 670 0001ECBE 11 90 jbr L299
693: 671 0001ECC0 .data
694: 672 000006b4 * .text
695: 673 0001ECC0 .align 1
696: 674 0001ECC0 .globl _cvdf_er_halt
697: 675 0001ECC0 _cvdf_er_halt:
698: 676 0001ECC0 0000 .word L303
699: 677 0001ECC2 #
700: 678 0001ECC2 #
701: 679 0001ECC2 #
702: 680 0001ECC2 # /**************************************************************************
703: 681 0001ECC2 # *
704: 682 0001ECC2 # * HALT ON ERROR ROUTINE
705: 683 0001ECC2 # *
706: 684 0001ECC2 # **************************************************************************/
707: 685 0001ECC2 # cvdf_er_halt( halt_code )
708: 686 0001ECC2 # int halt_code;
709: 687 0001ECC2 # {
710: 688 0001ECC2 13 00db jbr L305
711: 689 0001ECC5 L306:
712: 690 0001ECC5 # sgl_value_1 = dbl_ld_acc.m;
713: 691 0001ECC5 0d effffffa25 effffffa20 movl _dbl_ld_acc,_sgl_value_1
714: 692 0001ECD0 # sgl_value_2 = dbl_ld_acc.l;
715: 693 0001ECD0 0d effffffa1e effffffa15 movl _dbl_ld_acc+4,_sgl_value_2
716: 694 0001ECDB # sgl_value_3 = sgl_st_acc;
717: 695 0001ECDB 0d effffffa0f effffffa0a movl _sgl_st_acc,_sgl_value_3
718: 696 0001ECE6 # sgl_dummy1 = halt_code; /* get the error type */
719: 697 0001ECE6 0d ad04 effffffa02 movl 4(fp),_sgl_dummy1
720: 698 0001ECEE # asm("movl _test_no,r0"); /* r0 = test number */
721: 699 0001ECEE 0d effffff9fc 50 movl _test_no,r0
722: 700 0001ECF5 # asm("movl _subtest,r1"); /* r1 = subtest number */
723: 701 0001ECF5 0d effffff9f5 51 movl _subtest,r1
724: 702 0001ECFC # asm("movl _sgl_dummy1,r2"); /* r2 = error code */
725: 703 0001ECFC 0d effffff9ee 52 movl _sgl_dummy1,r2
726: 704 0001ED03 # asm("movl _cycle,r3"); /* r3 = cycle count */
727: 705 0001ED03 0d effffff9e7 53 movl _cycle,r3
728: 706 0001ED0A # asm("movl _sgl_value_1,r4"); /* r4 = MS accumulator */
729: 707 0001ED0A 0d effffff9e0 54 movl _sgl_value_1,r4
730: 708 0001ED11 # asm("movl _sgl_value_2,r5"); /* r5 = LS accumulator */
731: 709 0001ED11 0d effffff9d9 55 movl _sgl_value_2,r5
732: 710 0001ED18 # asm("movl _sgl_value_3,r6"); /* r6 = final acc */
733: 711 0001ED18 0d effffff9d2 56 movl _sgl_value_3,r6
734: 712 0001ED1F # if( halt_code == BAD_ACC_HLT ) {
735: 713 0001ED1F 1d ad04 01 cmpl 4(fp),$1
736: 714 0001ED23 21 1b jneq L307
737: 715 0001ED25 # sgl_value_1 = sgl_expected;
738: 716 0001ED25 0d effffff9c5 effffff9c0 movl _sgl_expected,_sgl_value_1
739: 717 0001ED30 # asm("movl _sgl_value_1,r7"); /* r7 = expected acc */
740: 718 0001ED30 0d effffff9ba 57 movl _sgl_value_1,r7
741: 719 0001ED37 # asm("movl _index,r8"); /* r8 = data index */
742: 720 0001ED37 0d effffff9b3 58 movl _index,r8
743: 721 0001ED3E # } else
744: 722 0001ED3E 11 5e jbr L308
745: 723 0001ED40 L307:
746: 724 0001ED40 # if( halt_code == BAD_REG_HLT ) {
747: 725 0001ED40 1d ad04 02 cmpl 4(fp),$2
748: 726 0001ED44 21 3d jneq L309
749: 727 0001ED46 # sgl_dummy1 = load_regs[index2];
750: 728 0001ED46 0d effffff9a4 50 movl _index2,r0
751: 729 0001ED4D 0d 40effffff99c movl _load_regs[r0],_sgl_dummy1
752: effffff997
753: 730 0001ED59 # sgl_dummy2 = store_regs[index2];
754: 731 0001ED59 0d effffff991 50 movl _index2,r0
755: 732 0001ED60 0d 40effffff989 movl _store_regs[r0],_sgl_dummy2
756: effffff984
757: 733 0001ED6C # asm("movl _index2,r7"); /* r7 = bad register # */
758: 734 0001ED6C 0d effffff97e 57 movl _index2,r7
759: 735 0001ED73 # asm("movl _sgl_dummy2,r8"); /* r8 = actual value */
760: 736 0001ED73 0d effffff977 58 movl _sgl_dummy2,r8
761: 737 0001ED7A # asm("movl _sgl_dummy1,r9"); /* r9 = expected value */
762: 738 0001ED7A 0d effffff970 59 movl _sgl_dummy1,r9
763: 739 0001ED81 # } else
764: 740 0001ED81 11 1b jbr L310
765: 741 0001ED83 L309:
766: 742 0001ED83 # if( halt_code == BAD_PSL_HLT ) {
767: 743 0001ED83 1d ad04 03 cmpl 4(fp),$3
768: 744 0001ED87 21 15 jneq L311
769: 745 0001ED89 # asm("movl _init_psl,r7"); /* r7 = initial PSL */
770: 746 0001ED89 0d effffff961 57 movl _init_psl,r7
771: 747 0001ED90 # asm("movl _psl_val,r8"); /* r8 = final PSL */
772: 748 0001ED90 0d effffff95a 58 movl _psl_val,r8
773: 749 0001ED97 # asm("movl _exp_psl,r9"); /* r9 = expected PSL */
774: 750 0001ED97 0d effffff953 59 movl _exp_psl,r9
775: 751 0001ED9E # };
776: 752 0001ED9E L311:
777: 753 0001ED9E L310:
778: 754 0001ED9E L308:
779: 755 0001ED9E # asm("halt"); /* HALT ... */
780: 756 0001ED9E 00 halt
781: 757 0001ED9F # }
782: 758 0001ED9F 40 ret#2
783: 759 0001EDA0 .set L303,0x0
784: 760 0001EDA0 L305:
785: 761 0001EDA0 13 ff22 jbr L306
786: 762 0001EDA3 .data
787: 762 0003D493 .data
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