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Up to [Power 6/32 Unix Tahoe 4.2BSD] / cci / d / macro4|
Return to cvdf.lst CVS log | Up to [Power 6/32 Unix Tahoe 4.2BSD] / cci / d / macro4 |
Power 6/32 Unix version 1.21
1 00000000 LL0:
2 00000000 .data
3 000006b4 * .text
4 00000000 .align 1
5 00000000 .globl _cvdf
6 00000000 _cvdf:
7 0001E6F0 0000 .word L215
8 0001E6F2 #
9 0001E6F2 # #include "fpp_defs.h"
10 0001E6F2 #
11 0001E6F2 #
12 0001E6F2 # /*****************************************************************************
13 0001E6F2 # *
14 0001E6F2 # * CVDF - SINGLE PRECISION FLOATING POINT CONVERT LONG TO FLOAT TEST
15 0001E6F2 # *
16 0001E6F2 # *****************************************************************************/
17 0001E6F2 # cvdf()
18 0001E6F2 # {
19 0001E6F2 11 3a jbr L217
20 0001E6F4 L218:
21 0001E6F4 # asm(".globl _cvdf_t");
22 0001E6F4 .globl _cvdf_t
23 0001E6F4 # asm("_cvdf_t:"); /* entry address */
24 0001E6F4 _cvdf_t:
25 0001E6F4 # if( ( cycle == 1 ) && ( prt_hdrs ) ) /* print headers on 1st pass */
26 0001E6F4 1d effffffff6 01 cmpl _cycle,$1
27 0001E6FB 21 15 jneq L219
28 0001E6FD 5d efffffffed tstl _prt_hdrs
29 0001E703 31 0d jeql L219
30 0001E705 # writes("\n CVDF");
31 0001E705 .data 1
32 000006b4 * L221:
33 000006b4 * 0A204356444600 .ascii "\12 CVDF\0"
34 000006bb * .text
35 0001E705 dd 8f000006b4 pushl $L221
36 0001E70B fe 08 efffffffde callf $8,_writes
37 0001E712 # cvdf_1(); /* load through a register */
38 0001E712 L219:
39 0001E712 fe 04 ef00000017 callf $4,_cvdf_1
40 0001E719 # cvdf_2(); /* register stability */
41 0001E719 fe 04 ef0000017e callf $4,_cvdf_2
42 0001E720 # cvdf_3(); /* PSL stability test */
43 0001E720 fe 04 ef00000343 callf $4,_cvdf_3
44 0001E727 # asm("jmp *return"); /* return to the test monitor */
45 0001E727 71 ffffffffc3 jmp *return
46 0001E72D # }
47 0001E72D 40 ret#2
48 0001E72E .set L215,0x0
49 0001E72E L217:
50 0001E72E 11 c4 jbr L218
51 0001E730 .data
52 000006b4 * .text
53 0001E730 .align 1
54 0001E730 .globl _cvdf_1
55 0001E730 _cvdf_1:
56 0001E730 0000 .word L225
57 0001E732 #
58 0001E732 #
59 0001E732 #
60 0001E732 # /************************************************************************
61 0001E732 # *
62 0001E732 # * SUBTEST 1
63 0001E732 # *
64 0001E732 # ************************************************************************/
65 0001E732 # cvdf_1()
66 0001E732 # {
67 0001E732 13 0166 jbr L227
68 0001E735 L228:
69 0001E735 # force_loop = FALSE;
70 0001E735 4d efffffffb5 clrl _force_loop
71 0001E73B # subtest = 1;
72 0001E73B 0d 01 efffffffae movl $1,_subtest
73 0001E742 # index = 0;
74 0001E742 4d efffffffa8 clrl _index
75 0001E748 # do {
76 0001E748 L231:
77 0001E748 # dbl_ld_acc = cvdf_1_data[index].ld; /* get the operand */
78 0001E748 5c 0c efffffffa1 50 mull3 $12,_index,r0
79 0001E750 0c 8f00000000 50 addl2 $_cvdf_1_data,r0
80 0001E757 0d a004 efffffff95 movl 4(r0),_dbl_ld_acc+4
81 0001E75F 0d 60 efffffff8a movl (r0),_dbl_ld_acc
82 0001E766 # sgl_expected = cvdf_1_data[index].exp; /* get expected result */
83 0001E766 5c 0c efffffff83 50 mull3 $12,_index,r0
84 0001E76E 0d e000000008 efffffff77 movl _cvdf_1_data+8(r0),_sgl_expected
85 0001E779 # if( (dbl_ld_acc.m & 0x7f800000) ) {
86 0001E779 3d 8f7f800000 efffffff6c bitl $2139095040,_dbl_ld_acc
87 0001E784 31 1e jeql L232
88 0001E786 # sgl_expected = dbl_ld_acc.m;
89 0001E786 0d efffffff64 efffffff5f movl _dbl_ld_acc,_sgl_expected
90 0001E791 # if( dbl_ld_acc.l & 0x80000000)
91 0001E791 3d 8f80000000 efffffff58 bitl $-2147483648,_dbl_ld_acc+4
92 0001E79C 31 06 jeql L233
93 0001E79E # sgl_expected++;
94 0001E79E 6d efffffff4c incl _sgl_expected
95 0001E7A4 # }
96 0001E7A4 L233:
97 0001E7A4 # /*
98 0001E7A4 # * If LOOP ON ERROR is set, this is the loop for this subtest.
99 0001E7A4 # * The force loop flag is set after the first error.
100 0001E7A4 # */
101 0001E7A4 # asm("_cvdf_1_lp1:");
102 0001E7A4 L232:
103 0001E7A4 _cvdf_1_lp1:
104 0001E7A4 # asm("movl _dbl_ld_acc,r4"); /* get the value to convert */
105 0001E7A4 0d efffffff46 54 movl _dbl_ld_acc,r4
106 0001E7AB # asm("movl _dbl_ld_acc+4,r5");
107 0001E7AB 0d efffffff43 55 movl _dbl_ld_acc+4,r5
108 0001E7B2 # asm("ldd r4"); /* load the data */
109 0001E7B2 07 54 ldd r4
110 0001E7B4 # asm("cvdf"); /* convert the value */
111 0001E7B4 a6 cvdf
112 0001E7B5 # asm("stf r8"); /* store the result */
113 0001E7B5 26 58 stf r8
114 0001E7B7 # if( force_loop )
115 0001E7B7 5d efffffff33 tstl _force_loop
116 0001E7BD 31 02 jeql L234
117 0001E7BF # asm("brb _cvdf_1_lp1");; /* loop on the error */
118 0001E7BF 11 e3 brb _cvdf_1_lp1
119 0001E7C1 L234:
120 0001E7C1 # /*
121 0001E7C1 # * end error loop - test the results
122 0001E7C1 # */
123 0001E7C1 # asm("movl r8,_sgl_st_acc"); /* move result to cache */
124 0001E7C1 0d 58 efffffff28 movl r8,_sgl_st_acc
125 0001E7C8 # if( sgl_st_acc != sgl_expected ) { /* COMPARE the values */
126 0001E7C8 1d efffffff22 efffffff1d cmpl _sgl_st_acc,_sgl_expected
127 0001E7D3 21 03 13 00a9 jeql L235
128 0001E7D8 # errcnt++; /* bump the error count */
129 0001E7D8 6d efffffff12 incl _errcnt
130 0001E7DE # if( prt_error ) {
131 0001E7DE 5d efffffff0c tstl _prt_error
132 0001E7E4 31 78 jeql L236
133 0001E7E6 # writes(" \n"); /* start a new print line */
134 0001E7E6 .data 1
135 000006bb * L237:
136 000006bb * 200A00 .ascii " \12\0"
137 000006be * .text
138 0001E7E6 dd 8f000006bb pushl $L237
139 0001E7EC fe 08 effffffefd callf $8,_writes
140 0001E7F3 # writes("cycle: ");
141 0001E7F3 .data 1
142 000006be * L238:
143 000006be * 6379636C653A2000 .ascii "cycle: \0"
144 000006c6 * .text
145 0001E7F3 dd 8f000006be pushl $L238
146 0001E7F9 fe 08 effffffef0 callf $8,_writes
147 0001E800 # writed( cycle );
148 0001E800 dd effffffeea pushl _cycle
149 0001E806 fe 08 effffffee3 callf $8,_writed
150 0001E80D # writes(" CVDF test ");
151 0001E80D .data 1
152 000006c6 * L240:
153 000006c6 * 2020435644462074657374200 .ascii " CVDF test \0"
0
154 000006d3 * .text
155 0001E80D dd 8f000006c6 pushl $L240
156 0001E813 fe 08 effffffed6 callf $8,_writes
157 0001E81A # writed( test_no );
158 0001E81A dd effffffed0 pushl _test_no
159 0001E820 fe 08 effffffec9 callf $8,_writed
160 0001E827 # writes(", subtest 1 (Reg. Data) - BAD FINAL ACC\n");
161 0001E827 .data 1
162 000006d3 * L241:
163 000006d3 * 2C20737562746573742031202 .ascii ", subtest 1 (Reg. Data) - BAD FINAL ACC\12\0"
85265672E204461746129202D
204241442046494E414C20414
3430A00
164 000006fc * .text
165 0001E827 dd 8f000006d3 pushl $L241
166 0001E82D fe 08 effffffebc callf $8,_writes
167 0001E834 # print_cvdf_data();
168 0001E834 fe 04 ef00000411 callf $4,_print_cvdf_data
169 0001E83B # writes(" Acc expected = ");
170 0001E83B .data 1
171 000006fc * L243:
172 000006fc * 2020202020202020202020202 .ascii " Acc expected = \0"
0202020202020202020202020
2020202020204163632065787
06563746564203D2000
173 0000072b * .text
174 0001E83B dd 8f000006fc pushl $L243
175 0001E841 fe 08 effffffea8 callf $8,_writes
176 0001E848 # write32h( sgl_expected );
177 0001E848 dd effffffea2 pushl _sgl_expected
178 0001E84E fe 08 effffffe9b callf $8,_write32h
179 0001E855 # writec('\n');
180 0001E855 dd 0a pushl $10
181 0001E857 fe 08 effffffe92 callf $8,_writec
182 0001E85E # }
183 0001E85E # if( halt_flg )
184 0001E85E L236:
185 0001E85E 5d effffffe8c tstl _halt_flg
186 0001E864 31 09 jeql L246
187 0001E866 # cvdf_er_halt( BAD_ACC_HLT ); /* halt on the error */
188 0001E866 dd 01 pushl $1
189 0001E868 fe 08 ef00000451 callf $8,_cvdf_er_halt
190 0001E86F # if( loop_on_err ) {
191 0001E86F L246:
192 0001E86F 5d effffffe7b tstl _loop_on_err
193 0001E875 31 0a jeql L248
194 0001E877 # force_loop = TRUE; /* set the force loop flag */
195 0001E877 0d 01 effffffe72 movl $1,_force_loop
196 0001E87E # asm("brw _cvdf_1_lp1");; /* and loop on the error */
197 0001E87E 13 ff23 brw _cvdf_1_lp1
198 0001E881 # } /* end of loop on error */
199 0001E881 # } /* end of compare error */
200 0001E881 L248:
201 0001E881 # } while( index++ < max_cvdf_1_index ); /* end of WHILE loop */
202 0001E881 L235:
203 0001E881 L230:
204 0001E881 0d effffffe69 50 movl _index,r0
205 0001E888 6d effffffe62 incl _index
206 0001E88E 1d 50 effffffe5b cmpl r0,_max_cvdf_1_index
207 0001E895 81 03 13 feae jlss L231
208 0001E89A L229:
209 0001E89A # } /* end of subtest 1 */
210 0001E89A 40 ret#2
211 0001E89B .set L225,0x0
212 0001E89B L227:
213 0001E89B 13 fe97 jbr L228
214 0001E89E .data
215 000006b4 * .text
216 0001E89E .align 1
217 0001E89E .globl _cvdf_2
218 0001E89E _cvdf_2:
219 0001E89E 0000 .word L249
220 0001E8A0 #
221 0001E8A0 #
222 0001E8A0 #
223 0001E8A0 # /************************************************************************
224 0001E8A0 # *
225 0001E8A0 # * SUBTEST 2 - Check for register corruption
226 0001E8A0 # *
227 0001E8A0 # ************************************************************************/
228 0001E8A0 # cvdf_2()
229 0001E8A0 # {
230 0001E8A0 13 01c3 jbr L251
231 0001E8A3 L252:
232 0001E8A3 # force_loop = FALSE; /* clear force_loop flg */
233 0001E8A3 4d effffffe47 clrl _force_loop
234 0001E8A9 # subtest = 2;
235 0001E8A9 0d 02 effffffe40 movl $2,_subtest
236 0001E8B0 # fill_reg_buf( load_regs ); /* get patterns for regs */
237 0001E8B0 dd 8f00000000 pushl $_load_regs
238 0001E8B6 fe 08 effffffe33 callf $8,_fill_reg_buf
239 0001E8BD # index = 0;
240 0001E8BD 4d effffffe2d clrl _index
241 0001E8C3 # dbl_ld_acc = cvdf_1_data[index].ld; /* get the operand */
242 0001E8C3 5c 0c effffffe26 50 mull3 $12,_index,r0
243 0001E8CB 0c 8f00000000 50 addl2 $_cvdf_1_data,r0
244 0001E8D2 0d a004 effffffe1a movl 4(r0),_dbl_ld_acc+4
245 0001E8DA 0d 60 effffffe0f movl (r0),_dbl_ld_acc
246 0001E8E1 # sgl_expected = cvdf_1_data[index].exp; /* get expected result */
247 0001E8E1 5c 0c effffffe08 50 mull3 $12,_index,r0
248 0001E8E9 0d e000000008 effffffdfc movl _cvdf_1_data+8(r0),_sgl_expected
249 0001E8F4 # /*
250 0001E8F4 # * If LOOP ON ERROR is set, this is the loop for this subtest.
251 0001E8F4 # * The force loop flag is set after the first error.
252 0001E8F4 # */
253 0001E8F4 # asm("_cvdf_2_lp1:");
254 0001E8F4 _cvdf_2_lp1:
255 0001E8F4 # asm("ldd _dbl_ld_acc"); /* load the data */
256 0001E8F4 07 effffffdf6 ldd _dbl_ld_acc
257 0001E8FA # asm("loadr $0x1fff,_load_regs"); /* load regs 0 - 12 */
258 0001E8FA ab 891fff effffffded loadr $0x1fff,_load_regs
259 0001E903 # asm("nop");
260 0001E903 10 nop
261 0001E904 # asm("cvdf"); /* convert the value */
262 0001E904 a6 cvdf
263 0001E905 # asm("nop");
264 0001E905 10 nop
265 0001E906 # asm("storer $0x1fff,_store_regs"); /* store regs 0 - 12 */
266 0001E906 bb 891fff effffffde1 storer $0x1fff,_store_regs
267 0001E90F # if( force_loop )
268 0001E90F 5d effffffddb tstl _force_loop
269 0001E915 31 02 jeql L254
270 0001E917 # asm("brb _cvdf_2_lp1");; /* loop on the error */
271 0001E917 11 db brb _cvdf_2_lp1
272 0001E919 L254:
273 0001E919 # /*
274 0001E919 # * Now compare the stored register values to those that were loaded
275 0001E919 # */
276 0001E919 # index2 = 0;
277 0001E919 4d effffffdd1 clrl _index2
278 0001E91F # while( (load_regs[index2] == store_regs[index2]) && (index2 < 13) )
279 0001E91F L255:
280 0001E91F 0d effffffdcb 50 movl _index2,r0
281 0001E926 0d effffffdc4 51 movl _index2,r1
282 0001E92D 1d 40effffffdbc cmpl _load_regs[r0],_store_regs[r1]
41effffffdb6
283 0001E93A 21 11 jneq L256
284 0001E93C 1d effffffdae 0d cmpl _index2,$13
285 0001E943 81 08 jgeq L256
286 0001E945 # index2++; /* check reg values */
287 0001E945 6d effffffda5 incl _index2
288 0001E94B 11 d2 jbr L255
289 0001E94D L256:
290 0001E94D # if( index2 < 13 ) { /* error if index2 < 13 */
291 0001E94D 1d effffffd9d 0d cmpl _index2,$13
292 0001E954 91 03 13 00f4 jgeq L257
293 0001E959 # errcnt++; /* bump the error count */
294 0001E959 6d effffffd91 incl _errcnt
295 0001E95F # if( prt_error ) {
296 0001E95F 5d effffffd8b tstl _prt_error
297 0001E965 21 03 13 00c0 jeql L258
298 0001E96A # writes(" \n"); /* start a new print line */
299 0001E96A .data 1
300 0000072b * L259:
301 0000072b * 200A00 .ascii " \12\0"
302 0000072e * .text
303 0001E96A dd 8f0000072b pushl $L259
304 0001E970 fe 08 effffffd79 callf $8,_writes
305 0001E977 # writes("cycle: ");
306 0001E977 .data 1
307 0000072e * L260:
308 0000072e * 6379636C653A2000 .ascii "cycle: \0"
309 00000736 * .text
310 0001E977 dd 8f0000072e pushl $L260
311 0001E97D fe 08 effffffd6c callf $8,_writes
312 0001E984 # writed( cycle );
313 0001E984 dd effffffd66 pushl _cycle
314 0001E98A fe 08 effffffd5f callf $8,_writed
315 0001E991 # writes(" CVDF test ");
316 0001E991 .data 1
317 00000736 * L261:
318 00000736 * 2020435644462074657374200 .ascii " CVDF test \0"
0
319 00000743 * .text
320 0001E991 dd 8f00000736 pushl $L261
321 0001E997 fe 08 effffffd52 callf $8,_writes
322 0001E99E # writed( test_no );
323 0001E99E dd effffffd4c pushl _test_no
324 0001E9A4 fe 08 effffffd45 callf $8,_writed
325 0001E9AB # writes(", subtest 2 - A REGISTER WAS MODIFIED\n");
326 0001E9AB .data 1
327 00000743 * L262:
328 00000743 * 2C20737562746573742032202 .ascii ", subtest 2 - A REGISTER WAS MODIFIED\12\0"
D204120524547495354455220
574153204D4F4449464945440
A00
329 0000076a * .text
330 0001E9AB dd 8f00000743 pushl $L262
331 0001E9B1 fe 08 effffffd38 callf $8,_writes
332 0001E9B8 # print_cvdf_data(); /* print the operands */
333 0001E9B8 fe 04 ef0000028d callf $4,_print_cvdf_data
334 0001E9BF # writes("register "); /* print the information */
335 0001E9BF .data 1
336 0000076a * L263:
337 0000076a * 72656769737465722000 .ascii "register \0"
338 00000774 * .text
339 0001E9BF dd 8f0000076a pushl $L263
340 0001E9C5 fe 08 effffffd24 callf $8,_writes
341 0001E9CC # writed( index2 ); /* about the corrupted */
342 0001E9CC dd effffffd1e pushl _index2
343 0001E9D2 fe 08 effffffd17 callf $8,_writed
344 0001E9D9 # writes(" = "); /* register */
345 0001E9D9 .data 1
346 00000774 * L264:
347 00000774 * 203D2000 .ascii " = \0"
348 00000778 * .text
349 0001E9D9 dd 8f00000774 pushl $L264
350 0001E9DF fe 08 effffffd0a callf $8,_writes
351 0001E9E6 # write32h( store_regs[index2] );
352 0001E9E6 0d effffffd04 50 movl _index2,r0
353 0001E9ED dd 40effffffcfc pushl _store_regs[r0]
354 0001E9F4 fe 08 effffffcf5 callf $8,_write32h
355 0001E9FB # writes(", should be = ");
356 0001E9FB .data 1
357 00000778 * L265:
358 00000778 * 2C202073686F756C642062652 .ascii ", should be = \0"
03D2000
359 00000788 * .text
360 0001E9FB dd 8f00000778 pushl $L265
361 0001EA01 fe 08 effffffce8 callf $8,_writes
362 0001EA08 # write32h( load_regs[index2] );
363 0001EA08 0d effffffce2 50 movl _index2,r0
364 0001EA0F dd 40effffffcda pushl _load_regs[r0]
365 0001EA16 fe 08 effffffcd3 callf $8,_write32h
366 0001EA1D # writes("\n");
367 0001EA1D .data 1
368 00000788 * L266:
369 00000788 * 0A00 .ascii "\12\0"
370 0000078a * .text
371 0001EA1D dd 8f00000788 pushl $L266
372 0001EA23 fe 08 effffffcc6 callf $8,_writes
373 0001EA2A # }
374 0001EA2A # if( halt_flg )
375 0001EA2A L258:
376 0001EA2A 5d effffffcc0 tstl _halt_flg
377 0001EA30 31 09 jeql L267
378 0001EA32 # cvdf_er_halt( BAD_REG_HLT ); /* halt on the error */
379 0001EA32 dd 02 pushl $2
380 0001EA34 fe 08 ef00000285 callf $8,_cvdf_er_halt
381 0001EA3B # if( loop_on_err ) {
382 0001EA3B L267:
383 0001EA3B 5d effffffcaf tstl _loop_on_err
384 0001EA41 31 0a jeql L268
385 0001EA43 # force_loop = TRUE; /* set the force loop flag */
386 0001EA43 0d 01 effffffca6 movl $1,_force_loop
387 0001EA4A # asm("brw _cvdf_2_lp1");; /* and loop on the error */
388 0001EA4A 13 fea7 brw _cvdf_2_lp1
389 0001EA4D # } /* end of loop on error */
390 0001EA4D # } while( index++ < max_cvdf_1_index ); /* end of reg corruption error */
391 0001EA4D L268:
392 0001EA4D L257:
393 0001EA4D L269:
394 0001EA4D 0d effffffc9d 50 movl _index,r0
395 0001EA54 6d effffffc96 incl _index
396 0001EA5A 1d 50 effffffc8f cmpl r0,_max_cvdf_1_index
397 0001EA61 81 02 jgeq L270
398 0001EA63 11 e8 jbr L269
399 0001EA65 L270:
400 0001EA65 # } /* end of subtest 2 */
401 0001EA65 40 ret#2
402 0001EA66 .set L249,0x0
403 0001EA66 L251:
404 0001EA66 13 fe3a jbr L252
405 0001EA69 .data
406 000006b4 * .text
407 0001EA69 00 .align 1
408 0001EA6A .globl _cvdf_3
409 0001EA6A _cvdf_3:
410 0001EA6A 0000 .word L271
411 0001EA6C #
412 0001EA6C #
413 0001EA6C #
414 0001EA6C # /************************************************************************
415 0001EA6C # *
416 0001EA6C # * SUBTEST 3 - Check for PSL corruption
417 0001EA6C # *
418 0001EA6C # ************************************************************************/
419 0001EA6C # cvdf_3()
420 0001EA6C # {
421 0001EA6C 13 01da jbr L273
422 0001EA6F L274:
423 0001EA6F # force_loop = FALSE; /* clear force_loop flg */
424 0001EA6F 4d effffffc7b clrl _force_loop
425 0001EA75 # subtest = 3;
426 0001EA75 0d 03 effffffc74 movl $3,_subtest
427 0001EA7C # fill_reg_buf( load_regs ); /* get patterns for regs */
428 0001EA7C dd 8f00000000 pushl $_load_regs
429 0001EA82 fe 08 effffffc67 callf $8,_fill_reg_buf
430 0001EA89 # for( index = 0; index < 3; index++ ) {
431 0001EA89 4d effffffc61 clrl _index
432 0001EA8F L277:
433 0001EA8F 1d effffffc5b 03 cmpl _index,$3
434 0001EA96 91 03 13 0195 jgeq L276
435 0001EA9B # dbl_ld_acc = cvdf_1_data[index].ld; /* get the operand */
436 0001EA9B 5c 0c effffffc4e 50 mull3 $12,_index,r0
437 0001EAA3 0c 8f00000000 50 addl2 $_cvdf_1_data,r0
438 0001EAAA 0d a004 effffffc42 movl 4(r0),_dbl_ld_acc+4
439 0001EAB2 0d 60 effffffc37 movl (r0),_dbl_ld_acc
440 0001EAB9 # sgl_expected = cvdf_1_data[index].exp; /* get expected result */
441 0001EAB9 5c 0c effffffc30 50 mull3 $12,_index,r0
442 0001EAC1 0d e000000008 effffffc24 movl _cvdf_1_data+8(r0),_sgl_expected
443 0001EACC # status_index = 0;
444 0001EACC 4d effffffc1e clrl _status_index
445 0001EAD2 # do {
446 0001EAD2 L280:
447 0001EAD2 # sgl_dummy1 = status_array[status_index]; /* +, -, 0 status */
448 0001EAD2 0d effffffc18 50 movl _status_index,r0
449 0001EAD9 0d 40effffffc10 movl _status_array[r0],_sgl_dummy1
effffffc0b
450 0001EAE5 # /*
451 0001EAE5 # * If LOOP ON ERROR is set, this is the loop for this subtest.
452 0001EAE5 # * The force loop flag is set after the first error.
453 0001EAE5 # */
454 0001EAE5 # asm("_cvdf_3_lp1:");
455 0001EAE5 _cvdf_3_lp1:
456 0001EAE5 # asm("ldd _dbl_ld_acc"); /* load the data */
457 0001EAE5 07 effffffc05 ldd _dbl_ld_acc
458 0001EAEB # asm("tstl _sgl_dummy1"); /* set the PSL status */
459 0001EAEB 5d effffffbff tstl _sgl_dummy1
460 0001EAF1 # asm("movpsl _init_psl"); /* save the initial PSL */
461 0001EAF1 cd effffffbf9 movpsl _init_psl
462 0001EAF7 # asm("nop");
463 0001EAF7 10 nop
464 0001EAF8 # asm("cvdf"); /* convert the value */
465 0001EAF8 a6 cvdf
466 0001EAF9 # asm("nop");
467 0001EAF9 10 nop
468 0001EAFA # asm("movpsl _psl_val"); /* save the final PSL */
469 0001EAFA cd effffffbf0 movpsl _psl_val
470 0001EB00 # if( force_loop )
471 0001EB00 5d effffffbea tstl _force_loop
472 0001EB06 31 02 jeql L281
473 0001EB08 # asm("brb _cvdf_3_lp1");; /* loop on the error */
474 0001EB08 11 db brb _cvdf_3_lp1
475 0001EB0A L281:
476 0001EB0A # /*
477 0001EB0A # * Now compare the final PSL to the initial PSL -they should be the same
478 0001EB0A # */
479 0001EB0A # exp_psl = init_psl;
480 0001EB0A 0d effffffbe0 effffffbdb movl _init_psl,_exp_psl
481 0001EB15 # exp_psl &= 0xffffff7f;
482 0001EB15 ac 89ff7f effffffbd2 andl2 $-129,_exp_psl
483 0001EB1E # if( psl_val != exp_psl ) {
484 0001EB1E 1d effffffbcc effffffbc7 cmpl _psl_val,_exp_psl
485 0001EB29 21 03 13 00e4 jeql L282
486 0001EB2E # errcnt++; /* bump the error count */
487 0001EB2E 6d effffffbbc incl _errcnt
488 0001EB34 # if( prt_error ) {
489 0001EB34 5d effffffbb6 tstl _prt_error
490 0001EB3A 21 03 13 00b0 jeql L283
491 0001EB3F # writes(" \n"); /* start a new line */
492 0001EB3F .data 1
493 0000078a * L284:
494 0000078a * 200A00 .ascii " \12\0"
495 0000078d * .text
496 0001EB3F dd 8f0000078a pushl $L284
497 0001EB45 fe 08 effffffba4 callf $8,_writes
498 0001EB4C # writes("cycle: ");
499 0001EB4C .data 1
500 0000078d * L285:
501 0000078d * 6379636C653A2000 .ascii "cycle: \0"
502 00000795 * .text
503 0001EB4C dd 8f0000078d pushl $L285
504 0001EB52 fe 08 effffffb97 callf $8,_writes
505 0001EB59 # writed( cycle );
506 0001EB59 dd effffffb91 pushl _cycle
507 0001EB5F fe 08 effffffb8a callf $8,_writed
508 0001EB66 # writes(" CVDF test ");
509 0001EB66 .data 1
510 00000795 * L286:
511 00000795 * 2020435644462074657374200 .ascii " CVDF test \0"
0
512 000007a2 * .text
513 0001EB66 dd 8f00000795 pushl $L286
514 0001EB6C fe 08 effffffb7d callf $8,_writes
515 0001EB73 # writed( test_no );
516 0001EB73 dd effffffb77 pushl _test_no
517 0001EB79 fe 08 effffffb70 callf $8,_writed
518 0001EB80 # writes(", subtest 3 - INCORRECT FINAL PSL\n");
519 0001EB80 .data 1
520 000007a2 * L287:
521 000007a2 * 2C20737562746573742033202 .ascii ", subtest 3 - INCORRECT FINAL PSL\12\0"
02D20494E434F525245435420
46494E414C2050534C0A00
522 000007c6 * .text
523 0001EB80 dd 8f000007a2 pushl $L287
524 0001EB86 fe 08 effffffb63 callf $8,_writes
525 0001EB8D # print_cvdf_data(); /* print the operands */
526 0001EB8D fe 04 ef000000b8 callf $4,_print_cvdf_data
527 0001EB94 # writes("initial PSL = ");
528 0001EB94 .data 1
529 000007c6 * L288:
530 000007c6 * 696E697469616C2050534C203 .ascii "initial PSL = \0"
D2000
531 000007d5 * .text
532 0001EB94 dd 8f000007c6 pushl $L288
533 0001EB9A fe 08 effffffb4f callf $8,_writes
534 0001EBA1 # write32h( init_psl );
535 0001EBA1 dd effffffb49 pushl _init_psl
536 0001EBA7 fe 08 effffffb42 callf $8,_write32h
537 0001EBAE # writes(", final PSL = ");
538 0001EBAE .data 1
539 000007d5 * L289:
540 000007d5 * 2C202066696E616C2050534C2 .ascii ", final PSL = \0"
03D2000
541 000007e5 * .text
542 0001EBAE dd 8f000007d5 pushl $L289
543 0001EBB4 fe 08 effffffb35 callf $8,_writes
544 0001EBBB # write32h( psl_val );
545 0001EBBB dd effffffb2f pushl _psl_val
546 0001EBC1 fe 08 effffffb28 callf $8,_write32h
547 0001EBC8 # writes(", expected PSL = ");
548 0001EBC8 .data 1
549 000007e5 * L290:
550 000007e5 * 2C20206578706563746564205 .ascii ", expected PSL = \0"
0534C203D2000
551 000007f8 * .text
552 0001EBC8 dd 8f000007e5 pushl $L290
553 0001EBCE fe 08 effffffb1b callf $8,_writes
554 0001EBD5 # write32h( exp_psl );
555 0001EBD5 dd effffffb15 pushl _exp_psl
556 0001EBDB fe 08 effffffb0e callf $8,_write32h
557 0001EBE2 # writes("\n");
558 0001EBE2 .data 1
559 000007f8 * L291:
560 000007f8 * 0A00 .ascii "\12\0"
561 000007fa * .text
562 0001EBE2 dd 8f000007f8 pushl $L291
563 0001EBE8 fe 08 effffffb01 callf $8,_writes
564 0001EBEF # }
565 0001EBEF # if( halt_flg )
566 0001EBEF L283:
567 0001EBEF 5d effffffafb tstl _halt_flg
568 0001EBF5 31 09 jeql L292
569 0001EBF7 # cvdf_er_halt( BAD_PSL_HLT ); /* halt on error */
570 0001EBF7 dd 03 pushl $3
571 0001EBF9 fe 08 ef000000c0 callf $8,_cvdf_er_halt
572 0001EC00 # if( loop_on_err ) {
573 0001EC00 L292:
574 0001EC00 5d effffffaea tstl _loop_on_err
575 0001EC06 31 0a jeql L293
576 0001EC08 # force_loop = TRUE; /* set force loop flag */
577 0001EC08 0d 01 effffffae1 movl $1,_force_loop
578 0001EC0F # asm("brw _cvdf_3_lp1");; /* and loop */
579 0001EC0F 13 fed3 brw _cvdf_3_lp1
580 0001EC12 # } /* end of loop on error */
581 0001EC12 # } /* end of PSL corruption error */
582 0001EC12 L293:
583 0001EC12 # } while( ++status_index < 3 ); /* end of status loop */
584 0001EC12 L282:
585 0001EC12 L279:
586 0001EC12 6d effffffad8 incl _status_index
587 0001EC18 0d effffffad2 50 movl _status_index,r0
588 0001EC1F 1d 50 03 cmpl r0,$3
589 0001EC22 81 03 13 feab jlss L280
590 0001EC27 L278:
591 0001EC27 # } while( index++ < max_cvdf_1_index ); /* end of WHILE loop */
592 0001EC27 L275:
593 0001EC27 6d effffffac3 incl _index
594 0001EC2D 13 fe5f jbr L277
595 0001EC30 L276:
596 0001EC30 L294:
597 0001EC30 0d effffffaba 50 movl _index,r0
598 0001EC37 6d effffffab3 incl _index
599 0001EC3D 1d 50 effffffaac cmpl r0,_max_cvdf_1_index
600 0001EC44 81 02 jgeq L295
601 0001EC46 11 e8 jbr L294
602 0001EC48 L295:
603 0001EC48 # } /* end of subtest 3 */
604 0001EC48 40 ret#2
605 0001EC49 .set L271,0x0
606 0001EC49 L273:
607 0001EC49 13 fe23 jbr L274
608 0001EC4C .data
609 000006b4 * .text
610 0001EC4C .align 1
611 0001EC4C .globl _print_cvdf_data
612 0001EC4C _print_cvdf_data:
613 0001EC4C 0000 .word L296
614 0001EC4E #
615 0001EC4E #
616 0001EC4E #
617 0001EC4E # /**************************************************************************
618 0001EC4E # *
619 0001EC4E # * PRINT THE DATA AND STORE RESULTS
620 0001EC4E # *
621 0001EC4E # * initial Acc = xxxxxxxx xxxxxxxx, stored = xxxxxxxx xxxxxxxx, index = xx
622 0001EC4E # **************************************************************************/
623 0001EC4E # print_cvdf_data()
624 0001EC4E # {
625 0001EC4E 11 6e jbr L298
626 0001EC50 L299:
627 0001EC50 # writes("initial Acc = ");
628 0001EC50 .data 1
629 000007fa * L300:
630 000007fa * 696E697469616C20416363203 .ascii "initial Acc = \0"
D2000
631 00000809 * .text
632 0001EC50 dd 8f000007fa pushl $L300
633 0001EC56 fe 08 effffffa93 callf $8,_writes
634 0001EC5D # write32h( dbl_ld_acc.m );
635 0001EC5D dd effffffa8d pushl _dbl_ld_acc
636 0001EC63 fe 08 effffffa86 callf $8,_write32h
637 0001EC6A # writec(' ');
638 0001EC6A dd 20 pushl $32
639 0001EC6C fe 08 effffffa7d callf $8,_writec
640 0001EC73 # write32h( dbl_ld_acc.l );
641 0001EC73 dd effffffa7b pushl _dbl_ld_acc+4
642 0001EC79 fe 08 effffffa70 callf $8,_write32h
643 0001EC80 # writes(", final Acc = ");
644 0001EC80 .data 1
645 00000809 * L301:
646 00000809 * 2C202066696E616C204163632 .ascii ", final Acc = \0"
03D2000
647 00000819 * .text
648 0001EC80 dd 8f00000809 pushl $L301
649 0001EC86 fe 08 effffffa63 callf $8,_writes
650 0001EC8D # write32h( sgl_st_acc );
651 0001EC8D dd effffffa5d pushl _sgl_st_acc
652 0001EC93 fe 08 effffffa56 callf $8,_write32h
653 0001EC9A # writes(", index = ");
654 0001EC9A .data 1
655 00000819 * L302:
656 00000819 * 2C2020696E646578203D2000 .ascii ", index = \0"
657 00000825 * .text
658 0001EC9A dd 8f00000819 pushl $L302
659 0001ECA0 fe 08 effffffa49 callf $8,_writes
660 0001ECA7 # writed( index );
661 0001ECA7 dd effffffa43 pushl _index
662 0001ECAD fe 08 effffffa3c callf $8,_writed
663 0001ECB4 # writec('\n');
664 0001ECB4 dd 0a pushl $10
665 0001ECB6 fe 08 effffffa33 callf $8,_writec
666 0001ECBD # }
667 0001ECBD 40 ret#2
668 0001ECBE .set L296,0x0
669 0001ECBE L298:
670 0001ECBE 11 90 jbr L299
671 0001ECC0 .data
672 000006b4 * .text
673 0001ECC0 .align 1
674 0001ECC0 .globl _cvdf_er_halt
675 0001ECC0 _cvdf_er_halt:
676 0001ECC0 0000 .word L303
677 0001ECC2 #
678 0001ECC2 #
679 0001ECC2 #
680 0001ECC2 # /**************************************************************************
681 0001ECC2 # *
682 0001ECC2 # * HALT ON ERROR ROUTINE
683 0001ECC2 # *
684 0001ECC2 # **************************************************************************/
685 0001ECC2 # cvdf_er_halt( halt_code )
686 0001ECC2 # int halt_code;
687 0001ECC2 # {
688 0001ECC2 13 00db jbr L305
689 0001ECC5 L306:
690 0001ECC5 # sgl_value_1 = dbl_ld_acc.m;
691 0001ECC5 0d effffffa25 effffffa20 movl _dbl_ld_acc,_sgl_value_1
692 0001ECD0 # sgl_value_2 = dbl_ld_acc.l;
693 0001ECD0 0d effffffa1e effffffa15 movl _dbl_ld_acc+4,_sgl_value_2
694 0001ECDB # sgl_value_3 = sgl_st_acc;
695 0001ECDB 0d effffffa0f effffffa0a movl _sgl_st_acc,_sgl_value_3
696 0001ECE6 # sgl_dummy1 = halt_code; /* get the error type */
697 0001ECE6 0d ad04 effffffa02 movl 4(fp),_sgl_dummy1
698 0001ECEE # asm("movl _test_no,r0"); /* r0 = test number */
699 0001ECEE 0d effffff9fc 50 movl _test_no,r0
700 0001ECF5 # asm("movl _subtest,r1"); /* r1 = subtest number */
701 0001ECF5 0d effffff9f5 51 movl _subtest,r1
702 0001ECFC # asm("movl _sgl_dummy1,r2"); /* r2 = error code */
703 0001ECFC 0d effffff9ee 52 movl _sgl_dummy1,r2
704 0001ED03 # asm("movl _cycle,r3"); /* r3 = cycle count */
705 0001ED03 0d effffff9e7 53 movl _cycle,r3
706 0001ED0A # asm("movl _sgl_value_1,r4"); /* r4 = MS accumulator */
707 0001ED0A 0d effffff9e0 54 movl _sgl_value_1,r4
708 0001ED11 # asm("movl _sgl_value_2,r5"); /* r5 = LS accumulator */
709 0001ED11 0d effffff9d9 55 movl _sgl_value_2,r5
710 0001ED18 # asm("movl _sgl_value_3,r6"); /* r6 = final acc */
711 0001ED18 0d effffff9d2 56 movl _sgl_value_3,r6
712 0001ED1F # if( halt_code == BAD_ACC_HLT ) {
713 0001ED1F 1d ad04 01 cmpl 4(fp),$1
714 0001ED23 21 1b jneq L307
715 0001ED25 # sgl_value_1 = sgl_expected;
716 0001ED25 0d effffff9c5 effffff9c0 movl _sgl_expected,_sgl_value_1
717 0001ED30 # asm("movl _sgl_value_1,r7"); /* r7 = expected acc */
718 0001ED30 0d effffff9ba 57 movl _sgl_value_1,r7
719 0001ED37 # asm("movl _index,r8"); /* r8 = data index */
720 0001ED37 0d effffff9b3 58 movl _index,r8
721 0001ED3E # } else
722 0001ED3E 11 5e jbr L308
723 0001ED40 L307:
724 0001ED40 # if( halt_code == BAD_REG_HLT ) {
725 0001ED40 1d ad04 02 cmpl 4(fp),$2
726 0001ED44 21 3d jneq L309
727 0001ED46 # sgl_dummy1 = load_regs[index2];
728 0001ED46 0d effffff9a4 50 movl _index2,r0
729 0001ED4D 0d 40effffff99c movl _load_regs[r0],_sgl_dummy1
effffff997
730 0001ED59 # sgl_dummy2 = store_regs[index2];
731 0001ED59 0d effffff991 50 movl _index2,r0
732 0001ED60 0d 40effffff989 movl _store_regs[r0],_sgl_dummy2
effffff984
733 0001ED6C # asm("movl _index2,r7"); /* r7 = bad register # */
734 0001ED6C 0d effffff97e 57 movl _index2,r7
735 0001ED73 # asm("movl _sgl_dummy2,r8"); /* r8 = actual value */
736 0001ED73 0d effffff977 58 movl _sgl_dummy2,r8
737 0001ED7A # asm("movl _sgl_dummy1,r9"); /* r9 = expected value */
738 0001ED7A 0d effffff970 59 movl _sgl_dummy1,r9
739 0001ED81 # } else
740 0001ED81 11 1b jbr L310
741 0001ED83 L309:
742 0001ED83 # if( halt_code == BAD_PSL_HLT ) {
743 0001ED83 1d ad04 03 cmpl 4(fp),$3
744 0001ED87 21 15 jneq L311
745 0001ED89 # asm("movl _init_psl,r7"); /* r7 = initial PSL */
746 0001ED89 0d effffff961 57 movl _init_psl,r7
747 0001ED90 # asm("movl _psl_val,r8"); /* r8 = final PSL */
748 0001ED90 0d effffff95a 58 movl _psl_val,r8
749 0001ED97 # asm("movl _exp_psl,r9"); /* r9 = expected PSL */
750 0001ED97 0d effffff953 59 movl _exp_psl,r9
751 0001ED9E # };
752 0001ED9E L311:
753 0001ED9E L310:
754 0001ED9E L308:
755 0001ED9E # asm("halt"); /* HALT ... */
756 0001ED9E 00 halt
757 0001ED9F # }
758 0001ED9F 40 ret#2
759 0001EDA0 .set L303,0x0
760 0001EDA0 L305:
761 0001EDA0 13 ff22 jbr L306
762 0001EDA3 .data
762 0003D493 .data
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