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1.1 ! root 1: ! 2: #include "fpp_defs.h" ! 3: ! 4: ! 5: /***************************************************************************** ! 6: * ! 7: * CVDL - SINGLE PRECISION FLOATING POINT CONVERT LONG TO FLOAT TEST ! 8: * ! 9: *****************************************************************************/ ! 10: cvdl() ! 11: { ! 12: asm(".globl _cvdl_t"); ! 13: asm("_cvdl_t:"); /* entry address */ ! 14: if( ( cycle == 1 ) && ( prt_hdrs ) ) /* print headers on 1st cycle */ ! 15: writes(" CVDL"); ! 16: cvdl_1(); /* load through a register */ ! 17: cvdl_2(); /* load through the cache */ ! 18: cvdl_3(); /* register stability */ ! 19: cvdl_4(); /* PSL stability test */ ! 20: asm("jmp *return"); /* return to the test monitor */ ! 21: } ! 22: ! 23: ! 24: ! 25: /************************************************************************ ! 26: * ! 27: * SUBTEST 1 ! 28: * ! 29: ************************************************************************/ ! 30: cvdl_1() ! 31: { ! 32: force_loop = FALSE; ! 33: subtest = 1; ! 34: index = 0; ! 35: do ! 36: { ! 37: dbl_ld_acc = cvdl_1_data[index].ld; /* get the operand */ ! 38: sgl_expected = cvdl_1_data[index].exp; /* get expected result */ ! 39: sgl_value_1 = dbl_ld_acc.m; /* get an initial value */ ! 40: sgl_value_2 = dbl_ld_acc.l; /* for the accumulator */ ! 41: /* ! 42: * If LOOP ON ERROR is set, this is the loop for this subtest. ! 43: * The force loop flag is set after the first error. ! 44: */ ! 45: asm("_cvdl_1_lp1:"); ! 46: asm("movl _sgl_value_1,r4"); /* get the value to convert */ ! 47: asm("movl _sgl_value_2,r5"); ! 48: asm("ldd r4"); /* load the value to convert*/ ! 49: asm("cvdl r8"); /* convert the value */ ! 50: asm("nop"); ! 51: asm("std _dbl_st_acc"); /* save the accumulator */ ! 52: if( force_loop ) ! 53: asm("brb _cvdl_1_lp1");; /* loop on the error */ ! 54: /* ! 55: * end error loop - test the results ! 56: */ ! 57: asm("movl r8,_sgl_value_3"); /* move result to cache */ ! 58: if( sgl_value_3 != sgl_expected ) {/* COMPARE the values */ ! 59: errcnt++; /* bump the error count */ ! 60: if( prt_error ) { ! 61: writes(" \n"); /* start a new print line */ ! 62: writes("cycle: "); ! 63: writed( cycle ); ! 64: writes(" CVDL test "); ! 65: writed( test_no ); ! 66: writes(", subtest 1 (Reg. Data) - WRONG DATA STORED\n"); ! 67: print_cvdl_data(); ! 68: writes(", index = "); ! 69: writed( index ); ! 70: writec('\n'); ! 71: writes(" final Acc = "); ! 72: write32h( dbl_st_acc.m ); ! 73: writec(' '); ! 74: write32h( dbl_st_acc.l ); ! 75: writes(", int. expected = "); ! 76: write32h( sgl_expected ); ! 77: writec('\n'); ! 78: } ! 79: if( halt_flg ) ! 80: cvdl_er_halt( BAD_STORE_HLT ); /* halt on the error */ ! 81: if( loop_on_err ) { ! 82: force_loop = TRUE; /* set the force loop flag */ ! 83: asm("brw _cvdl_1_lp1");; /* and loop on the error */ ! 84: } /* end of loop on error */ ! 85: } /* end of convert compare error */ ! 86: if( dbl_ld_acc.m & 0x7f800000 ) { ! 87: dbl_expected.m = dbl_ld_acc.m; /* the Acc should */ ! 88: dbl_expected.l = dbl_ld_acc.l; /* not change */ ! 89: } else { ! 90: dbl_expected.m = 0; /* expect a '0' final Acc */ ! 91: dbl_expected.l = 0; ! 92: } ! 93: if( ( dbl_st_acc.m != dbl_expected.m ) || ! 94: ( dbl_st_acc.l != dbl_expected.l ) ) { /* COMPARE values */ ! 95: errcnt++; /* bump the error count */ ! 96: if( prt_error ) { ! 97: writes(" \n"); /* start a new print line */ ! 98: writes("cycle: "); ! 99: writed( cycle ); ! 100: writes(" CVDL test "); ! 101: writed( test_no ); ! 102: writes(", subtest 1 (Reg. Data) - BAD FINAL ACC\n"); ! 103: print_cvdl_data(); ! 104: writes(", index = "); ! 105: writed( index ); ! 106: writec('\n'); ! 107: writes(" final Acc = "); ! 108: write32h( dbl_st_acc.m ); ! 109: writec(' '); ! 110: write32h( dbl_st_acc.l ); ! 111: writec('\n'); ! 112: writes(" expected = "); ! 113: write32h( dbl_expected.m ); ! 114: writec(' '); ! 115: write32h( dbl_expected.l ); ! 116: writec('\n'); ! 117: } ! 118: if( halt_flg ) ! 119: cvdl_er_halt( BAD_ACC_HLT ); /* halt on the error */ ! 120: if( loop_on_err ) { ! 121: force_loop = TRUE; /* set the force loop flag */ ! 122: asm("brw _cvdl_1_lp1");; /* and loop on the error */ ! 123: } /* end of loop on error */ ! 124: } /* end of ACC compare error */ ! 125: } while( index++ < max_cvdl_1_index ); /* end of WHILE loop */ ! 126: } /* end of subtest 1 */ ! 127: ! 128: ! 129: ! 130: /************************************************************************ ! 131: * ! 132: * SUBTEST 2 - convert through memory ! 133: * ! 134: ************************************************************************/ ! 135: cvdl_2() ! 136: { ! 137: force_loop = FALSE; ! 138: subtest = 2; ! 139: index = 0; ! 140: do ! 141: { ! 142: dbl_ld_acc = cvdl_1_data[index].ld; /* get the operand */ ! 143: sgl_expected = cvdl_1_data[index].exp; /* get expected result */ ! 144: /* ! 145: * If LOOP ON ERROR is set, this is the loop for this subtest. ! 146: * The force loop flag is set after the first error. ! 147: */ ! 148: asm("_cvdl_2_lp1:"); ! 149: asm("ldd _dbl_ld_acc"); /* load the background */ ! 150: asm("cvdl _sgl_value_3"); /* convert the value */ ! 151: asm("nop"); ! 152: asm("std _dbl_st_acc"); /* save the accumulator */ ! 153: if( force_loop ) ! 154: asm("brb _cvdl_2_lp1");; /* loop on the error */ ! 155: /* ! 156: * end error loop - test the results ! 157: */ ! 158: if( sgl_value_3 != sgl_expected ) {/* COMPARE the values */ ! 159: errcnt++; /* bump the error count */ ! 160: if( prt_error ) { ! 161: writes(" \n"); /* start a new print line */ ! 162: writes("cycle: "); ! 163: writed( cycle ); ! 164: writes(" CVDL test "); ! 165: writed( test_no ); ! 166: writes(", subtest 2 (Cache Data) - WRONG DATA STORED\n"); ! 167: print_cvdl_data(); ! 168: writes(", index = "); ! 169: writed( index ); ! 170: writec('\n'); ! 171: writes(" final Acc = "); ! 172: write32h( dbl_st_acc.m ); ! 173: writec(' '); ! 174: write32h( dbl_st_acc.l ); ! 175: writes(", int. expected = "); ! 176: write32h( sgl_expected ); ! 177: writec('\n'); ! 178: } ! 179: if( halt_flg ) ! 180: cvdl_er_halt( BAD_STORE_HLT ); /* halt on the error */ ! 181: if( loop_on_err ) { ! 182: force_loop = TRUE; /* set the force loop flag */ ! 183: asm("brw _cvdl_2_lp1");; /* and loop on the error */ ! 184: } /* end of loop on error */ ! 185: } /* end of convert compare error */ ! 186: if( dbl_ld_acc.m & 0x7f800000 ) { ! 187: dbl_expected.m = dbl_ld_acc.m; /* the Acc should */ ! 188: dbl_expected.l = dbl_ld_acc.l; /* not change */ ! 189: } else { ! 190: dbl_expected.m = 0; /* expect a '0' final Acc */ ! 191: dbl_expected.l = 0; ! 192: } ! 193: if( ( dbl_st_acc.m != dbl_expected.m ) || ! 194: ( dbl_st_acc.l != dbl_expected.l ) ) { /* COMPARE values */ ! 195: errcnt++; /* bump the error count */ ! 196: if( prt_error ) { ! 197: writes(" \n"); /* start a new print line */ ! 198: writes("cycle: "); ! 199: writed( cycle ); ! 200: writes(" CVDL test "); ! 201: writed( test_no ); ! 202: writes(", subtest 2 (Cache Data) - BAD FINAL ACC\n"); ! 203: print_cvdl_data(); ! 204: writes(", index = "); ! 205: writed( index ); ! 206: writec('\n'); ! 207: writes(" final Acc = "); ! 208: write32h( dbl_st_acc.m ); ! 209: writec(' '); ! 210: write32h( dbl_st_acc.l ); ! 211: writec('\n'); ! 212: writes(" expected = "); ! 213: write32h( dbl_expected.m ); ! 214: writec(' '); ! 215: write32h( dbl_expected.l ); ! 216: writec('\n'); ! 217: } ! 218: if( halt_flg ) ! 219: cvdl_er_halt( BAD_ACC_HLT ); /* halt on the error */ ! 220: if( loop_on_err ) { ! 221: force_loop = TRUE; /* set the force loop flag */ ! 222: asm("brw _cvdl_1_lp1");; /* and loop on the error */ ! 223: } /* end of loop on error */ ! 224: } /* end of ACC compare error */ ! 225: } while( index++ < max_cvdl_1_index ); /* end of WHILE loop */ ! 226: } /* end of subtest 2 */ ! 227: ! 228: ! 229: ! 230: /************************************************************************ ! 231: * ! 232: * SUBTEST 3 - Check for register corruption ! 233: * ! 234: ************************************************************************/ ! 235: cvdl_3() ! 236: { ! 237: force_loop = FALSE; /* clear force_loop flg */ ! 238: subtest = 3; ! 239: fill_reg_buf( load_regs ); /* get patterns for regs */ ! 240: index = 0; ! 241: dbl_ld_acc = cvdl_1_data[index].ld; /* get the operand */ ! 242: sgl_expected = cvdl_1_data[index].exp; /* get expected result */ ! 243: /* ! 244: * If LOOP ON ERROR is set, this is the loop for this subtest. ! 245: * The force loop flag is set after the first error. ! 246: */ ! 247: asm("_cvdl_3_lp1:"); ! 248: asm("ldd _dbl_ld_acc"); /* load base value */ ! 249: asm("loadr $0x1fff,_load_regs"); /* load regs 0 - 12 */ ! 250: asm("nop"); ! 251: asm("cvdl _sgl_value_3"); /* convert the value */ ! 252: asm("nop"); ! 253: asm("storer $0x1fff,_store_regs"); /* store regs 0 - 12 */ ! 254: asm("std _dbl_st_acc"); /* save the accumulator */ ! 255: if( force_loop ) ! 256: asm("brb _cvdl_3_lp1");; /* loop on the error */ ! 257: /* ! 258: * Now compare the stored register values to those that were loaded ! 259: */ ! 260: index2 = 0; ! 261: while( (load_regs[index2] == store_regs[index2]) && (index2 < 13) ) ! 262: index2++; /* check reg values */ ! 263: if( index2 < 13 ) { /* error if index2 < 13 */ ! 264: errcnt++; /* bump the error count */ ! 265: if( prt_error ) { ! 266: writes(" \n"); /* start a new print line */ ! 267: writes("cycle: "); ! 268: writed( cycle ); ! 269: writes(" CVDL test "); ! 270: writed( test_no ); ! 271: writes(", subtest 3 - A REGISTER WAS MODIFIED\n"); ! 272: print_cvdl_data(); /* print the operands */ ! 273: writec('\n'); ! 274: writes(" final Acc = "); ! 275: write32h( dbl_st_acc.m ); ! 276: writec(' '); ! 277: write32h( dbl_st_acc.l ); ! 278: writec('\n'); ! 279: writes("register "); /* print the information */ ! 280: writed( index2 ); /* about the corrupted */ ! 281: writes(" = "); /* register */ ! 282: write32h( store_regs[index2] ); ! 283: writes(", should be = "); ! 284: write32h( load_regs[index2] ); ! 285: writes("\n"); ! 286: } ! 287: if( halt_flg ) ! 288: cvdl_er_halt( BAD_REG_HLT ); /* halt on the error */ ! 289: if( loop_on_err ) { ! 290: force_loop = TRUE; /* set the force loop flag */ ! 291: asm("brw _cvdl_3_lp1");; /* and loop on the error */ ! 292: } /* end of loop on error */ ! 293: } while( index++ < max_cvdl_1_index );/* end of reg corruption error */ ! 294: } /* end of subtest 3 */ ! 295: ! 296: ! 297: ! 298: /************************************************************************ ! 299: * ! 300: * SUBTEST 4 - Check for PSL corruption ! 301: * ! 302: ************************************************************************/ ! 303: cvdl_4() ! 304: { ! 305: force_loop = FALSE; /* clear force_loop flg */ ! 306: subtest = 4; ! 307: for( index = 0; index < max_cvdl_1_index; index++ ) { ! 308: dbl_ld_acc = cvdl_1_data[index].ld; /* get the operand */ ! 309: sgl_expected = cvdl_1_data[index].exp; /* get expected */ ! 310: sgl_value_1 = dbl_ld_acc.m; ! 311: sgl_value_2 = dbl_ld_acc.l; ! 312: for( status_index = 0; status_index < 3; status_index++ ) { ! 313: sgl_dummy1 = status_array[status_index];/* status = +, -, 0 */ ! 314: /* ! 315: * If LOOP ON ERROR is set, this is the loop for this subtest. ! 316: * The force loop flag is set after the first error. ! 317: */ ! 318: asm("_cvdl_4_lp1:"); ! 319: asm("movl _sgl_value_1,r4"); /* put MS value in r4 */ ! 320: asm("movl _sgl_value_2,r5"); /* put LS value in r5 */ ! 321: asm("ldd r4"); /* load the acc */ ! 322: asm("tstl _sgl_dummy1"); /* set the PSL status */ ! 323: asm("movpsl _init_psl"); /* save the initial PSL */ ! 324: asm("nop"); ! 325: asm("cvdl r8"); /* convert the value */ ! 326: asm("nop"); ! 327: asm("movpsl _psl_val"); /* save the final PSL */ ! 328: asm("nop"); ! 329: asm("std _dbl_st_acc"); /* save the accumulator */ ! 330: if( force_loop ) ! 331: asm("brb _cvdl_4_lp1");; /* loop on the error */ ! 332: /* ! 333: * Now compare the final PSL to the initial PSL -they should be the same ! 334: */ ! 335: asm("movl r8,_sgl_value_3"); /* mave result to cache */ ! 336: exp_psl = init_psl; /* get the initial PSL */ ! 337: exp_psl &= 0xfffffff3; /* clear ZERO, NEGATIVE */ ! 338: if( !sgl_expected ) ! 339: exp_psl |= PSL_Z; /* expect ZERO bit set */ ! 340: if( sgl_expected < 0 ) ! 341: exp_psl |= PSL_N; /* expect NEG bit set */ ! 342: if( psl_val != exp_psl ) { ! 343: errcnt++; /* bump error count */ ! 344: if( prt_error ) { ! 345: writes(" \n"); /* start new print line */ ! 346: writes("cycle: "); ! 347: writed( cycle ); ! 348: writes( ! 349: " CVDL test 24, subtest 4 - INCORRECT FINAL PSL\n"); ! 350: print_cvdl_data(); /* print operands */ ! 351: writes(", index = "); ! 352: writed( index ); ! 353: writec('\n'); ! 354: writes(" final Acc = "); ! 355: write32h( dbl_st_acc.m ); ! 356: writec(' '); ! 357: write32h( dbl_st_acc.l ); ! 358: writec('\n'); ! 359: writes("initial PSL = "); ! 360: write32h( init_psl ); ! 361: writes(", final PSL = "); ! 362: write32h( psl_val ); ! 363: writes(", expected PSL = "); ! 364: write32h( exp_psl ); ! 365: writes("\n"); ! 366: } ! 367: if( halt_flg ) ! 368: cvdl_er_halt( BAD_PSL_HLT ); /* halt on error */ ! 369: if( loop_on_err ) { ! 370: force_loop = TRUE; /* set force loop flag */ ! 371: asm("brw _cvdl_4_lp1");; /* and loop on error */ ! 372: } /* end of loop on error */ ! 373: } /* end of PSL corruption error */ ! 374: } /* end of status WHILE loop */ ! 375: } /* end of data WHILE loop */ ! 376: } /* end of subtest 4 */ ! 377: ! 378: ! 379: ! 380: /************************************************************************** ! 381: * ! 382: * PRINT THE DATA AND STORE RESULTS ! 383: * ! 384: * initial Acc = xxxxxxxx xxxxxxxx, integer stored = xxxxxxxx ! 385: **************************************************************************/ ! 386: print_cvdl_data() ! 387: { ! 388: writes("initial Acc = "); ! 389: write32h( dbl_ld_acc.m ); ! 390: writec(' '); ! 391: write32h( dbl_ld_acc.l ); ! 392: writes(", int. stored = "); ! 393: write32h( sgl_value_3 ); ! 394: } ! 395: ! 396: ! 397: ! 398: /************************************************************************** ! 399: * ! 400: * HALT ON ERROR ROUTINE ! 401: * ! 402: **************************************************************************/ ! 403: cvdl_er_halt( halt_code ) ! 404: int halt_code; ! 405: { ! 406: sgl_value_1 = dbl_ld_acc.m; ! 407: sgl_value_2 = dbl_ld_acc.l; ! 408: sgl_value_4 = dbl_st_acc.m; ! 409: sgl_value_5 = dbl_st_acc.l; ! 410: sgl_dummy1 = halt_code; /* get the error type */ ! 411: asm("movl _test_no,r0"); /* r0 = test number */ ! 412: asm("movl _subtest,r1"); /* r1 = subtest number */ ! 413: asm("movl _sgl_dummy1,r2"); /* r2 = error code */ ! 414: asm("movl _cycle,r3"); /* r3 = cycle count */ ! 415: asm("movl _sgl_value_1,r4"); /* r4 = MS acc loaded */ ! 416: asm("movl _sgl_value_2,r5"); /* r5 = LS acc loaded */ ! 417: asm("movl _sgl_value_4,r6"); /* r6 = MS acc stored */ ! 418: asm("movl _sgl_value_5,r7"); /* r7 = LS acc stored */ ! 419: asm("movl _sgl_value_3,r8"); /* r8 = integer stored */ ! 420: if( halt_code == BAD_ACC_HLT ) { ! 421: sgl_value_1 = dbl_expected.m; ! 422: sgl_value_2 = dbl_expected.l; ! 423: asm("movl _sgl_value_1,r9"); /* r9 = MS expected */ ! 424: asm("movl _sgl_value_2,r10"); /* r10 = LS expected */ ! 425: asm("movl _index,r11"); /* r11 = data index */ ! 426: } else ! 427: if( halt_code == BAD_STORE_HLT ) { ! 428: asm("movl _sgl_expected,r9"); /* r9 = int expected */ ! 429: asm("movl _index,r10"); /* r10 = data index */ ! 430: } else ! 431: if( halt_code == BAD_REG_HLT ) { ! 432: sgl_dummy1 = load_regs[index2]; ! 433: sgl_dummy2 = store_regs[index2]; ! 434: asm("movl _index2,r9"); /* r9 = bad register # */ ! 435: asm("movl _sgl_dummy2,r10"); /* r10 = actual value */ ! 436: asm("movl _sgl_dummy1,r11"); /* r11 = expected value */ ! 437: } else ! 438: if( halt_code == BAD_PSL_HLT ) { ! 439: asm("movl _init_psl,r9"); /* r9 = initial PSL */ ! 440: asm("movl _psl_val,r10"); /* r10 = final PSL */ ! 441: asm("movl _exp_psl,r11"); /* r11 = expected PSL */ ! 442: }; ! 443: asm("halt"); /* HALT ... */ ! 444: }
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