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Power 6/32 Unix version 1.21
#include "fpp_defs.h"
/*****************************************************************************
*
* CVDL - SINGLE PRECISION FLOATING POINT CONVERT LONG TO FLOAT TEST
*
*****************************************************************************/
cvdl()
{
asm(".globl _cvdl_t");
asm("_cvdl_t:"); /* entry address */
if( ( cycle == 1 ) && ( prt_hdrs ) ) /* print headers on 1st cycle */
writes(" CVDL");
cvdl_1(); /* load through a register */
cvdl_2(); /* load through the cache */
cvdl_3(); /* register stability */
cvdl_4(); /* PSL stability test */
asm("jmp *return"); /* return to the test monitor */
}
/************************************************************************
*
* SUBTEST 1
*
************************************************************************/
cvdl_1()
{
force_loop = FALSE;
subtest = 1;
index = 0;
do
{
dbl_ld_acc = cvdl_1_data[index].ld; /* get the operand */
sgl_expected = cvdl_1_data[index].exp; /* get expected result */
sgl_value_1 = dbl_ld_acc.m; /* get an initial value */
sgl_value_2 = dbl_ld_acc.l; /* for the accumulator */
/*
* If LOOP ON ERROR is set, this is the loop for this subtest.
* The force loop flag is set after the first error.
*/
asm("_cvdl_1_lp1:");
asm("movl _sgl_value_1,r4"); /* get the value to convert */
asm("movl _sgl_value_2,r5");
asm("ldd r4"); /* load the value to convert*/
asm("cvdl r8"); /* convert the value */
asm("nop");
asm("std _dbl_st_acc"); /* save the accumulator */
if( force_loop )
asm("brb _cvdl_1_lp1");; /* loop on the error */
/*
* end error loop - test the results
*/
asm("movl r8,_sgl_value_3"); /* move result to cache */
if( sgl_value_3 != sgl_expected ) {/* COMPARE the values */
errcnt++; /* bump the error count */
if( prt_error ) {
writes(" \n"); /* start a new print line */
writes("cycle: ");
writed( cycle );
writes(" CVDL test ");
writed( test_no );
writes(", subtest 1 (Reg. Data) - WRONG DATA STORED\n");
print_cvdl_data();
writes(", index = ");
writed( index );
writec('\n');
writes(" final Acc = ");
write32h( dbl_st_acc.m );
writec(' ');
write32h( dbl_st_acc.l );
writes(", int. expected = ");
write32h( sgl_expected );
writec('\n');
}
if( halt_flg )
cvdl_er_halt( BAD_STORE_HLT ); /* halt on the error */
if( loop_on_err ) {
force_loop = TRUE; /* set the force loop flag */
asm("brw _cvdl_1_lp1");; /* and loop on the error */
} /* end of loop on error */
} /* end of convert compare error */
if( dbl_ld_acc.m & 0x7f800000 ) {
dbl_expected.m = dbl_ld_acc.m; /* the Acc should */
dbl_expected.l = dbl_ld_acc.l; /* not change */
} else {
dbl_expected.m = 0; /* expect a '0' final Acc */
dbl_expected.l = 0;
}
if( ( dbl_st_acc.m != dbl_expected.m ) ||
( dbl_st_acc.l != dbl_expected.l ) ) { /* COMPARE values */
errcnt++; /* bump the error count */
if( prt_error ) {
writes(" \n"); /* start a new print line */
writes("cycle: ");
writed( cycle );
writes(" CVDL test ");
writed( test_no );
writes(", subtest 1 (Reg. Data) - BAD FINAL ACC\n");
print_cvdl_data();
writes(", index = ");
writed( index );
writec('\n');
writes(" final Acc = ");
write32h( dbl_st_acc.m );
writec(' ');
write32h( dbl_st_acc.l );
writec('\n');
writes(" expected = ");
write32h( dbl_expected.m );
writec(' ');
write32h( dbl_expected.l );
writec('\n');
}
if( halt_flg )
cvdl_er_halt( BAD_ACC_HLT ); /* halt on the error */
if( loop_on_err ) {
force_loop = TRUE; /* set the force loop flag */
asm("brw _cvdl_1_lp1");; /* and loop on the error */
} /* end of loop on error */
} /* end of ACC compare error */
} while( index++ < max_cvdl_1_index ); /* end of WHILE loop */
} /* end of subtest 1 */
/************************************************************************
*
* SUBTEST 2 - convert through memory
*
************************************************************************/
cvdl_2()
{
force_loop = FALSE;
subtest = 2;
index = 0;
do
{
dbl_ld_acc = cvdl_1_data[index].ld; /* get the operand */
sgl_expected = cvdl_1_data[index].exp; /* get expected result */
/*
* If LOOP ON ERROR is set, this is the loop for this subtest.
* The force loop flag is set after the first error.
*/
asm("_cvdl_2_lp1:");
asm("ldd _dbl_ld_acc"); /* load the background */
asm("cvdl _sgl_value_3"); /* convert the value */
asm("nop");
asm("std _dbl_st_acc"); /* save the accumulator */
if( force_loop )
asm("brb _cvdl_2_lp1");; /* loop on the error */
/*
* end error loop - test the results
*/
if( sgl_value_3 != sgl_expected ) {/* COMPARE the values */
errcnt++; /* bump the error count */
if( prt_error ) {
writes(" \n"); /* start a new print line */
writes("cycle: ");
writed( cycle );
writes(" CVDL test ");
writed( test_no );
writes(", subtest 2 (Cache Data) - WRONG DATA STORED\n");
print_cvdl_data();
writes(", index = ");
writed( index );
writec('\n');
writes(" final Acc = ");
write32h( dbl_st_acc.m );
writec(' ');
write32h( dbl_st_acc.l );
writes(", int. expected = ");
write32h( sgl_expected );
writec('\n');
}
if( halt_flg )
cvdl_er_halt( BAD_STORE_HLT ); /* halt on the error */
if( loop_on_err ) {
force_loop = TRUE; /* set the force loop flag */
asm("brw _cvdl_2_lp1");; /* and loop on the error */
} /* end of loop on error */
} /* end of convert compare error */
if( dbl_ld_acc.m & 0x7f800000 ) {
dbl_expected.m = dbl_ld_acc.m; /* the Acc should */
dbl_expected.l = dbl_ld_acc.l; /* not change */
} else {
dbl_expected.m = 0; /* expect a '0' final Acc */
dbl_expected.l = 0;
}
if( ( dbl_st_acc.m != dbl_expected.m ) ||
( dbl_st_acc.l != dbl_expected.l ) ) { /* COMPARE values */
errcnt++; /* bump the error count */
if( prt_error ) {
writes(" \n"); /* start a new print line */
writes("cycle: ");
writed( cycle );
writes(" CVDL test ");
writed( test_no );
writes(", subtest 2 (Cache Data) - BAD FINAL ACC\n");
print_cvdl_data();
writes(", index = ");
writed( index );
writec('\n');
writes(" final Acc = ");
write32h( dbl_st_acc.m );
writec(' ');
write32h( dbl_st_acc.l );
writec('\n');
writes(" expected = ");
write32h( dbl_expected.m );
writec(' ');
write32h( dbl_expected.l );
writec('\n');
}
if( halt_flg )
cvdl_er_halt( BAD_ACC_HLT ); /* halt on the error */
if( loop_on_err ) {
force_loop = TRUE; /* set the force loop flag */
asm("brw _cvdl_1_lp1");; /* and loop on the error */
} /* end of loop on error */
} /* end of ACC compare error */
} while( index++ < max_cvdl_1_index ); /* end of WHILE loop */
} /* end of subtest 2 */
/************************************************************************
*
* SUBTEST 3 - Check for register corruption
*
************************************************************************/
cvdl_3()
{
force_loop = FALSE; /* clear force_loop flg */
subtest = 3;
fill_reg_buf( load_regs ); /* get patterns for regs */
index = 0;
dbl_ld_acc = cvdl_1_data[index].ld; /* get the operand */
sgl_expected = cvdl_1_data[index].exp; /* get expected result */
/*
* If LOOP ON ERROR is set, this is the loop for this subtest.
* The force loop flag is set after the first error.
*/
asm("_cvdl_3_lp1:");
asm("ldd _dbl_ld_acc"); /* load base value */
asm("loadr $0x1fff,_load_regs"); /* load regs 0 - 12 */
asm("nop");
asm("cvdl _sgl_value_3"); /* convert the value */
asm("nop");
asm("storer $0x1fff,_store_regs"); /* store regs 0 - 12 */
asm("std _dbl_st_acc"); /* save the accumulator */
if( force_loop )
asm("brb _cvdl_3_lp1");; /* loop on the error */
/*
* Now compare the stored register values to those that were loaded
*/
index2 = 0;
while( (load_regs[index2] == store_regs[index2]) && (index2 < 13) )
index2++; /* check reg values */
if( index2 < 13 ) { /* error if index2 < 13 */
errcnt++; /* bump the error count */
if( prt_error ) {
writes(" \n"); /* start a new print line */
writes("cycle: ");
writed( cycle );
writes(" CVDL test ");
writed( test_no );
writes(", subtest 3 - A REGISTER WAS MODIFIED\n");
print_cvdl_data(); /* print the operands */
writec('\n');
writes(" final Acc = ");
write32h( dbl_st_acc.m );
writec(' ');
write32h( dbl_st_acc.l );
writec('\n');
writes("register "); /* print the information */
writed( index2 ); /* about the corrupted */
writes(" = "); /* register */
write32h( store_regs[index2] );
writes(", should be = ");
write32h( load_regs[index2] );
writes("\n");
}
if( halt_flg )
cvdl_er_halt( BAD_REG_HLT ); /* halt on the error */
if( loop_on_err ) {
force_loop = TRUE; /* set the force loop flag */
asm("brw _cvdl_3_lp1");; /* and loop on the error */
} /* end of loop on error */
} while( index++ < max_cvdl_1_index );/* end of reg corruption error */
} /* end of subtest 3 */
/************************************************************************
*
* SUBTEST 4 - Check for PSL corruption
*
************************************************************************/
cvdl_4()
{
force_loop = FALSE; /* clear force_loop flg */
subtest = 4;
for( index = 0; index < max_cvdl_1_index; index++ ) {
dbl_ld_acc = cvdl_1_data[index].ld; /* get the operand */
sgl_expected = cvdl_1_data[index].exp; /* get expected */
sgl_value_1 = dbl_ld_acc.m;
sgl_value_2 = dbl_ld_acc.l;
for( status_index = 0; status_index < 3; status_index++ ) {
sgl_dummy1 = status_array[status_index];/* status = +, -, 0 */
/*
* If LOOP ON ERROR is set, this is the loop for this subtest.
* The force loop flag is set after the first error.
*/
asm("_cvdl_4_lp1:");
asm("movl _sgl_value_1,r4"); /* put MS value in r4 */
asm("movl _sgl_value_2,r5"); /* put LS value in r5 */
asm("ldd r4"); /* load the acc */
asm("tstl _sgl_dummy1"); /* set the PSL status */
asm("movpsl _init_psl"); /* save the initial PSL */
asm("nop");
asm("cvdl r8"); /* convert the value */
asm("nop");
asm("movpsl _psl_val"); /* save the final PSL */
asm("nop");
asm("std _dbl_st_acc"); /* save the accumulator */
if( force_loop )
asm("brb _cvdl_4_lp1");; /* loop on the error */
/*
* Now compare the final PSL to the initial PSL -they should be the same
*/
asm("movl r8,_sgl_value_3"); /* mave result to cache */
exp_psl = init_psl; /* get the initial PSL */
exp_psl &= 0xfffffff3; /* clear ZERO, NEGATIVE */
if( !sgl_expected )
exp_psl |= PSL_Z; /* expect ZERO bit set */
if( sgl_expected < 0 )
exp_psl |= PSL_N; /* expect NEG bit set */
if( psl_val != exp_psl ) {
errcnt++; /* bump error count */
if( prt_error ) {
writes(" \n"); /* start new print line */
writes("cycle: ");
writed( cycle );
writes(
" CVDL test 24, subtest 4 - INCORRECT FINAL PSL\n");
print_cvdl_data(); /* print operands */
writes(", index = ");
writed( index );
writec('\n');
writes(" final Acc = ");
write32h( dbl_st_acc.m );
writec(' ');
write32h( dbl_st_acc.l );
writec('\n');
writes("initial PSL = ");
write32h( init_psl );
writes(", final PSL = ");
write32h( psl_val );
writes(", expected PSL = ");
write32h( exp_psl );
writes("\n");
}
if( halt_flg )
cvdl_er_halt( BAD_PSL_HLT ); /* halt on error */
if( loop_on_err ) {
force_loop = TRUE; /* set force loop flag */
asm("brw _cvdl_4_lp1");; /* and loop on error */
} /* end of loop on error */
} /* end of PSL corruption error */
} /* end of status WHILE loop */
} /* end of data WHILE loop */
} /* end of subtest 4 */
/**************************************************************************
*
* PRINT THE DATA AND STORE RESULTS
*
* initial Acc = xxxxxxxx xxxxxxxx, integer stored = xxxxxxxx
**************************************************************************/
print_cvdl_data()
{
writes("initial Acc = ");
write32h( dbl_ld_acc.m );
writec(' ');
write32h( dbl_ld_acc.l );
writes(", int. stored = ");
write32h( sgl_value_3 );
}
/**************************************************************************
*
* HALT ON ERROR ROUTINE
*
**************************************************************************/
cvdl_er_halt( halt_code )
int halt_code;
{
sgl_value_1 = dbl_ld_acc.m;
sgl_value_2 = dbl_ld_acc.l;
sgl_value_4 = dbl_st_acc.m;
sgl_value_5 = dbl_st_acc.l;
sgl_dummy1 = halt_code; /* get the error type */
asm("movl _test_no,r0"); /* r0 = test number */
asm("movl _subtest,r1"); /* r1 = subtest number */
asm("movl _sgl_dummy1,r2"); /* r2 = error code */
asm("movl _cycle,r3"); /* r3 = cycle count */
asm("movl _sgl_value_1,r4"); /* r4 = MS acc loaded */
asm("movl _sgl_value_2,r5"); /* r5 = LS acc loaded */
asm("movl _sgl_value_4,r6"); /* r6 = MS acc stored */
asm("movl _sgl_value_5,r7"); /* r7 = LS acc stored */
asm("movl _sgl_value_3,r8"); /* r8 = integer stored */
if( halt_code == BAD_ACC_HLT ) {
sgl_value_1 = dbl_expected.m;
sgl_value_2 = dbl_expected.l;
asm("movl _sgl_value_1,r9"); /* r9 = MS expected */
asm("movl _sgl_value_2,r10"); /* r10 = LS expected */
asm("movl _index,r11"); /* r11 = data index */
} else
if( halt_code == BAD_STORE_HLT ) {
asm("movl _sgl_expected,r9"); /* r9 = int expected */
asm("movl _index,r10"); /* r10 = data index */
} else
if( halt_code == BAD_REG_HLT ) {
sgl_dummy1 = load_regs[index2];
sgl_dummy2 = store_regs[index2];
asm("movl _index2,r9"); /* r9 = bad register # */
asm("movl _sgl_dummy2,r10"); /* r10 = actual value */
asm("movl _sgl_dummy1,r11"); /* r11 = expected value */
} else
if( halt_code == BAD_PSL_HLT ) {
asm("movl _init_psl,r9"); /* r9 = initial PSL */
asm("movl _psl_val,r10"); /* r10 = final PSL */
asm("movl _exp_psl,r11"); /* r11 = expected PSL */
};
asm("halt"); /* HALT ... */
}
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