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Up to [Power 6/32 Unix Tahoe 4.2BSD] / cci / d / macro4|
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1.1 root 1: 1 00000000 LL0:
2: 2 00000000 .data
3: 3 00000c48 * .text
4: 4 00000000 .align 1
5: 5 00000000 .globl _cvdl
6: 6 00000000 _cvdl:
7: 7 0001DAA8 0000 .word L215
8: 8 0001DAAA #
9: 9 0001DAAA # #include "fpp_defs.h"
10: 10 0001DAAA #
11: 11 0001DAAA #
12: 12 0001DAAA # /*****************************************************************************
13: 13 0001DAAA # *
14: 14 0001DAAA # * CVDL - SINGLE PRECISION FLOATING POINT CONVERT LONG TO FLOAT TEST
15: 15 0001DAAA # *
16: 16 0001DAAA # *****************************************************************************/
17: 17 0001DAAA # cvdl()
18: 18 0001DAAA # {
19: 19 0001DAAA 11 41 jbr L217
20: 20 0001DAAC L218:
21: 21 0001DAAC # asm(".globl _cvdl_t");
22: 22 0001DAAC .globl _cvdl_t
23: 23 0001DAAC # asm("_cvdl_t:"); /* entry address */
24: 24 0001DAAC _cvdl_t:
25: 25 0001DAAC # if( ( cycle == 1 ) && ( prt_hdrs ) ) /* print headers on 1st cycle */
26: 26 0001DAAC 1d effffffff6 01 cmpl _cycle,$1
27: 27 0001DAB3 21 15 jneq L219
28: 28 0001DAB5 5d efffffffed tstl _prt_hdrs
29: 29 0001DABB 31 0d jeql L219
30: 30 0001DABD # writes(" CVDL");
31: 31 0001DABD .data 1
32: 32 00000c48 * L221:
33: 33 00000c48 * 204356444C00 .ascii " CVDL\0"
34: 34 00000c4e * .text
35: 35 0001DABD dd 8f00000c48 pushl $L221
36: 36 0001DAC3 fe 08 efffffffde callf $8,_writes
37: 37 0001DACA # cvdl_1(); /* load through a register */
38: 38 0001DACA L219:
39: 39 0001DACA fe 04 ef0000001f callf $4,_cvdl_1
40: 40 0001DAD1 # cvdl_2(); /* load through the cache */
41: 41 0001DAD1 fe 04 ef0000033a callf $4,_cvdl_2
42: 42 0001DAD8 # cvdl_3(); /* register stability */
43: 43 0001DAD8 fe 04 ef00000631 callf $4,_cvdl_3
44: 44 0001DADF # cvdl_4(); /* PSL stability test */
45: 45 0001DADF fe 04 ef00000842 callf $4,_cvdl_4
46: 46 0001DAE6 # asm("jmp *return"); /* return to the test monitor */
47: 47 0001DAE6 71 ffffffffbc jmp *return
48: 48 0001DAEC # }
49: 49 0001DAEC 40 ret#2
50: 50 0001DAED .set L215,0x0
51: 51 0001DAED L217:
52: 52 0001DAED 11 bd jbr L218
53: 53 0001DAEF .data
54: 54 00000c48 * .text
55: 55 0001DAEF 00 .align 1
56: 56 0001DAF0 .globl _cvdl_1
57: 57 0001DAF0 _cvdl_1:
58: 58 0001DAF0 0000 .word L226
59: 59 0001DAF2 #
60: 60 0001DAF2 #
61: 61 0001DAF2 #
62: 62 0001DAF2 # /************************************************************************
63: 63 0001DAF2 # *
64: 64 0001DAF2 # * SUBTEST 1
65: 65 0001DAF2 # *
66: 66 0001DAF2 # ************************************************************************/
67: 67 0001DAF2 # cvdl_1()
68: 68 0001DAF2 # {
69: 69 0001DAF2 13 0319 jbr L228
70: 70 0001DAF5 L229:
71: 71 0001DAF5 # force_loop = FALSE;
72: 72 0001DAF5 4d efffffffad clrl _force_loop
73: 73 0001DAFB # subtest = 1;
74: 74 0001DAFB 0d 01 efffffffa6 movl $1,_subtest
75: 75 0001DB02 # index = 0;
76: 76 0001DB02 4d efffffffa0 clrl _index
77: 77 0001DB08 # do
78: 78 0001DB08 L232:
79: 79 0001DB08 # {
80: 80 0001DB08 # dbl_ld_acc = cvdl_1_data[index].ld; /* get the operand */
81: 81 0001DB08 5c 0c efffffff99 50 mull3 $12,_index,r0
82: 82 0001DB10 0c 8f00000000 50 addl2 $_cvdl_1_data,r0
83: 83 0001DB17 0d a004 efffffff8d movl 4(r0),_dbl_ld_acc+4
84: 84 0001DB1F 0d 60 efffffff82 movl (r0),_dbl_ld_acc
85: 85 0001DB26 # sgl_expected = cvdl_1_data[index].exp; /* get expected result */
86: 86 0001DB26 5c 0c efffffff7b 50 mull3 $12,_index,r0
87: 87 0001DB2E 0d e000000008 efffffff6f movl _cvdl_1_data+8(r0),_sgl_expected
88: 88 0001DB39 # sgl_value_1 = dbl_ld_acc.m; /* get an initial value */
89: 89 0001DB39 0d efffffff69 efffffff64 movl _dbl_ld_acc,_sgl_value_1
90: 90 0001DB44 # sgl_value_2 = dbl_ld_acc.l; /* for the accumulator */
91: 91 0001DB44 0d efffffff62 efffffff59 movl _dbl_ld_acc+4,_sgl_value_2
92: 92 0001DB4F # /*
93: 93 0001DB4F # * If LOOP ON ERROR is set, this is the loop for this subtest.
94: 94 0001DB4F # * The force loop flag is set after the first error.
95: 95 0001DB4F # */
96: 96 0001DB4F # asm("_cvdl_1_lp1:");
97: 97 0001DB4F _cvdl_1_lp1:
98: 98 0001DB4F # asm("movl _sgl_value_1,r4"); /* get the value to convert */
99: 99 0001DB4F 0d efffffff53 54 movl _sgl_value_1,r4
100: 100 0001DB56 # asm("movl _sgl_value_2,r5");
101: 101 0001DB56 0d efffffff4c 55 movl _sgl_value_2,r5
102: 102 0001DB5D # asm("ldd r4"); /* load the value to convert*/
103: 103 0001DB5D 07 54 ldd r4
104: 104 0001DB5F # asm("cvdl r8"); /* convert the value */
105: 105 0001DB5F 87 58 cvdl r8
106: 106 0001DB61 # asm("nop");
107: 107 0001DB61 10 nop
108: 108 0001DB62 # asm("std _dbl_st_acc"); /* save the accumulator */
109: 109 0001DB62 27 efffffff40 std _dbl_st_acc
110: 110 0001DB68 # if( force_loop )
111: 111 0001DB68 5d efffffff3a tstl _force_loop
112: 112 0001DB6E 31 02 jeql L233
113: 113 0001DB70 # asm("brb _cvdl_1_lp1");; /* loop on the error */
114: 114 0001DB70 11 dd brb _cvdl_1_lp1
115: 115 0001DB72 L233:
116: 116 0001DB72 # /*
117: 117 0001DB72 # * end error loop - test the results
118: 118 0001DB72 # */
119: 119 0001DB72 # asm("movl r8,_sgl_value_3"); /* move result to cache */
120: 120 0001DB72 0d 58 efffffff2f movl r8,_sgl_value_3
121: 121 0001DB79 # if( sgl_value_3 != sgl_expected ) {/* COMPARE the values */
122: 122 0001DB79 1d efffffff29 efffffff24 cmpl _sgl_value_3,_sgl_expected
123: 123 0001DB84 21 03 13 00ff jeql L234
124: 124 0001DB89 # errcnt++; /* bump the error count */
125: 125 0001DB89 6d efffffff19 incl _errcnt
126: 126 0001DB8F # if( prt_error ) {
127: 127 0001DB8F 5d efffffff13 tstl _prt_error
128: 128 0001DB95 21 03 13 00cb jeql L235
129: 129 0001DB9A # writes(" \n"); /* start a new print line */
130: 130 0001DB9A .data 1
131: 131 00000c4e * L236:
132: 132 00000c4e * 200A00 .ascii " \12\0"
133: 133 00000c51 * .text
134: 134 0001DB9A dd 8f00000c4e pushl $L236
135: 135 0001DBA0 fe 08 efffffff01 callf $8,_writes
136: 136 0001DBA7 # writes("cycle: ");
137: 137 0001DBA7 .data 1
138: 138 00000c51 * L237:
139: 139 00000c51 * 6379636C653A2000 .ascii "cycle: \0"
140: 140 00000c59 * .text
141: 141 0001DBA7 dd 8f00000c51 pushl $L237
142: 142 0001DBAD fe 08 effffffef4 callf $8,_writes
143: 143 0001DBB4 # writed( cycle );
144: 144 0001DBB4 dd effffffeee pushl _cycle
145: 145 0001DBBA fe 08 effffffee7 callf $8,_writed
146: 146 0001DBC1 # writes(" CVDL test ");
147: 147 0001DBC1 .data 1
148: 148 00000c59 * L239:
149: 149 00000c59 * 20204356444C2074657374200 .ascii " CVDL test \0"
150: 0
151: 150 00000c66 * .text
152: 151 0001DBC1 dd 8f00000c59 pushl $L239
153: 152 0001DBC7 fe 08 effffffeda callf $8,_writes
154: 153 0001DBCE # writed( test_no );
155: 154 0001DBCE dd effffffed4 pushl _test_no
156: 155 0001DBD4 fe 08 effffffecd callf $8,_writed
157: 156 0001DBDB # writes(", subtest 1 (Reg. Data) - WRONG DATA STORED\n");
158: 157 0001DBDB .data 1
159: 158 00000c66 * L240:
160: 159 00000c66 * 2C20737562746573742031202 .ascii ", subtest 1 (Reg. Data) - WRONG DATA STORED\12\0"
161: 85265672E204461746129202D
162: 2057524F4E472044415441205
163: 3544F5245440A00
164: 160 00000c93 * .text
165: 161 0001DBDB dd 8f00000c66 pushl $L240
166: 162 0001DBE1 fe 08 effffffec0 callf $8,_writes
167: 163 0001DBE8 # print_cvdl_data();
168: 164 0001DBE8 fe 04 ef00000989 callf $4,_print_cvdl_data
169: 165 0001DBEF # writes(", index = ");
170: 166 0001DBEF .data 1
171: 167 00000c93 * L242:
172: 168 00000c93 * 2C202020696E646578203D200 .ascii ", index = \0"
173: 0
174: 169 00000ca0 * .text
175: 170 0001DBEF dd 8f00000c93 pushl $L242
176: 171 0001DBF5 fe 08 effffffeac callf $8,_writes
177: 172 0001DBFC # writed( index );
178: 173 0001DBFC dd effffffea6 pushl _index
179: 174 0001DC02 fe 08 effffffe9f callf $8,_writed
180: 175 0001DC09 # writec('\n');
181: 176 0001DC09 dd 0a pushl $10
182: 177 0001DC0B fe 08 effffffe96 callf $8,_writec
183: 178 0001DC12 # writes(" final Acc = ");
184: 179 0001DC12 .data 1
185: 180 00000ca0 * L244:
186: 181 00000ca0 * 202066696E616C20416363203 .ascii " final Acc = \0"
187: D2000
188: 182 00000caf * .text
189: 183 0001DC12 dd 8f00000ca0 pushl $L244
190: 184 0001DC18 fe 08 effffffe89 callf $8,_writes
191: 185 0001DC1F # write32h( dbl_st_acc.m );
192: 186 0001DC1F dd effffffe83 pushl _dbl_st_acc
193: 187 0001DC25 fe 08 effffffe7c callf $8,_write32h
194: 188 0001DC2C # writec(' ');
195: 189 0001DC2C dd 20 pushl $32
196: 190 0001DC2E fe 08 effffffe73 callf $8,_writec
197: 191 0001DC35 # write32h( dbl_st_acc.l );
198: 192 0001DC35 dd effffffe71 pushl _dbl_st_acc+4
199: 193 0001DC3B fe 08 effffffe66 callf $8,_write32h
200: 194 0001DC42 # writes(", int. expected = ");
201: 195 0001DC42 .data 1
202: 196 00000caf * L246:
203: 197 00000caf * 2C2020696E742E20657870656 .ascii ", int. expected = \0"
204: 3746564203D2000
205: 198 00000cc3 * .text
206: 199 0001DC42 dd 8f00000caf pushl $L246
207: 200 0001DC48 fe 08 effffffe59 callf $8,_writes
208: 201 0001DC4F # write32h( sgl_expected );
209: 202 0001DC4F dd effffffe53 pushl _sgl_expected
210: 203 0001DC55 fe 08 effffffe4c callf $8,_write32h
211: 204 0001DC5C # writec('\n');
212: 205 0001DC5C dd 0a pushl $10
213: 206 0001DC5E fe 08 effffffe43 callf $8,_writec
214: 207 0001DC65 # }
215: 208 0001DC65 # if( halt_flg )
216: 209 0001DC65 L235:
217: 210 0001DC65 5d effffffe3d tstl _halt_flg
218: 211 0001DC6B 31 09 jeql L247
219: 212 0001DC6D # cvdl_er_halt( BAD_STORE_HLT ); /* halt on the error */
220: 213 0001DC6D dd 09 pushl $9
221: 214 0001DC6F fe 08 ef00000954 callf $8,_cvdl_er_halt
222: 215 0001DC76 # if( loop_on_err ) {
223: 216 0001DC76 L247:
224: 217 0001DC76 5d effffffe2c tstl _loop_on_err
225: 218 0001DC7C 31 0a jeql L249
226: 219 0001DC7E # force_loop = TRUE; /* set the force loop flag */
227: 220 0001DC7E 0d 01 effffffe23 movl $1,_force_loop
228: 221 0001DC85 # asm("brw _cvdl_1_lp1");; /* and loop on the error */
229: 222 0001DC85 13 fec7 brw _cvdl_1_lp1
230: 223 0001DC88 # } /* end of loop on error */
231: 224 0001DC88 # } /* end of convert compare error */
232: 225 0001DC88 L249:
233: 226 0001DC88 # if( dbl_ld_acc.m & 0x7f800000 ) {
234: 227 0001DC88 L234:
235: 228 0001DC88 3d 8f7f800000 effffffe15 bitl $2139095040,_dbl_ld_acc
236: 229 0001DC93 31 18 jeql L250
237: 230 0001DC95 # dbl_expected.m = dbl_ld_acc.m; /* the Acc should */
238: 231 0001DC95 0d effffffe0d effffffe08 movl _dbl_ld_acc,_dbl_expected
239: 232 0001DCA0 # dbl_expected.l = dbl_ld_acc.l; /* not change */
240: 233 0001DCA0 0d effffffe06 effffffe01 movl _dbl_ld_acc+4,_dbl_expected+4
241: 234 0001DCAB # } else {
242: 235 0001DCAB 11 0c jbr L251
243: 236 0001DCAD L250:
244: 237 0001DCAD # dbl_expected.m = 0; /* expect a '0' final Acc */
245: 238 0001DCAD 4d effffffdf5 clrl _dbl_expected
246: 239 0001DCB3 # dbl_expected.l = 0;
247: 240 0001DCB3 4d effffffdf3 clrl _dbl_expected+4
248: 241 0001DCB9 # }
249: 242 0001DCB9 L251:
250: 243 0001DCB9 # if( ( dbl_st_acc.m != dbl_expected.m ) ||
251: 244 0001DCB9 # ( dbl_st_acc.l != dbl_expected.l ) ) { /* COMPARE values */
252: 245 0001DCB9 1d effffffde9 effffffde4 cmpl _dbl_st_acc,_dbl_expected
253: 246 0001DCC4 21 10 jneq L9999
254: 247 0001DCC6 1d effffffde0 effffffddb cmpl _dbl_st_acc+4,_dbl_expected+4
255: 248 0001DCD1 21 03 13 011e jeql L252
256: 249 0001DCD6 L9999:
257: 250 0001DCD6 # errcnt++; /* bump the error count */
258: 251 0001DCD6 6d effffffdcc incl _errcnt
259: 252 0001DCDC # if( prt_error ) {
260: 253 0001DCDC 5d effffffdc6 tstl _prt_error
261: 254 0001DCE2 21 03 13 00ea jeql L253
262: 255 0001DCE7 # writes(" \n"); /* start a new print line */
263: 256 0001DCE7 .data 1
264: 257 00000cc3 * L254:
265: 258 00000cc3 * 200A00 .ascii " \12\0"
266: 259 00000cc6 * .text
267: 260 0001DCE7 dd 8f00000cc3 pushl $L254
268: 261 0001DCED fe 08 effffffdb4 callf $8,_writes
269: 262 0001DCF4 # writes("cycle: ");
270: 263 0001DCF4 .data 1
271: 264 00000cc6 * L255:
272: 265 00000cc6 * 6379636C653A2000 .ascii "cycle: \0"
273: 266 00000cce * .text
274: 267 0001DCF4 dd 8f00000cc6 pushl $L255
275: 268 0001DCFA fe 08 effffffda7 callf $8,_writes
276: 269 0001DD01 # writed( cycle );
277: 270 0001DD01 dd effffffda1 pushl _cycle
278: 271 0001DD07 fe 08 effffffd9a callf $8,_writed
279: 272 0001DD0E # writes(" CVDL test ");
280: 273 0001DD0E .data 1
281: 274 00000cce * L256:
282: 275 00000cce * 20204356444C2074657374200 .ascii " CVDL test \0"
283: 0
284: 276 00000cdb * .text
285: 277 0001DD0E dd 8f00000cce pushl $L256
286: 278 0001DD14 fe 08 effffffd8d callf $8,_writes
287: 279 0001DD1B # writed( test_no );
288: 280 0001DD1B dd effffffd87 pushl _test_no
289: 281 0001DD21 fe 08 effffffd80 callf $8,_writed
290: 282 0001DD28 # writes(", subtest 1 (Reg. Data) - BAD FINAL ACC\n");
291: 283 0001DD28 .data 1
292: 284 00000cdb * L257:
293: 285 00000cdb * 2C20737562746573742031202 .ascii ", subtest 1 (Reg. Data) - BAD FINAL ACC\12\0"
294: 85265672E204461746129202D
295: 204241442046494E414C20414
296: 3430A00
297: 286 00000d04 * .text
298: 287 0001DD28 dd 8f00000cdb pushl $L257
299: 288 0001DD2E fe 08 effffffd73 callf $8,_writes
300: 289 0001DD35 # print_cvdl_data();
301: 290 0001DD35 fe 04 ef0000083c callf $4,_print_cvdl_data
302: 291 0001DD3C # writes(", index = ");
303: 292 0001DD3C .data 1
304: 293 00000d04 * L258:
305: 294 00000d04 * 2C202020696E646578203D200 .ascii ", index = \0"
306: 0
307: 295 00000d11 * .text
308: 296 0001DD3C dd 8f00000d04 pushl $L258
309: 297 0001DD42 fe 08 effffffd5f callf $8,_writes
310: 298 0001DD49 # writed( index );
311: 299 0001DD49 dd effffffd59 pushl _index
312: 300 0001DD4F fe 08 effffffd52 callf $8,_writed
313: 301 0001DD56 # writec('\n');
314: 302 0001DD56 dd 0a pushl $10
315: 303 0001DD58 fe 08 effffffd49 callf $8,_writec
316: 304 0001DD5F # writes(" final Acc = ");
317: 305 0001DD5F .data 1
318: 306 00000d11 * L259:
319: 307 00000d11 * 202066696E616C20416363203 .ascii " final Acc = \0"
320: D2000
321: 308 00000d20 * .text
322: 309 0001DD5F dd 8f00000d11 pushl $L259
323: 310 0001DD65 fe 08 effffffd3c callf $8,_writes
324: 311 0001DD6C # write32h( dbl_st_acc.m );
325: 312 0001DD6C dd effffffd36 pushl _dbl_st_acc
326: 313 0001DD72 fe 08 effffffd2f callf $8,_write32h
327: 314 0001DD79 # writec(' ');
328: 315 0001DD79 dd 20 pushl $32
329: 316 0001DD7B fe 08 effffffd26 callf $8,_writec
330: 317 0001DD82 # write32h( dbl_st_acc.l );
331: 318 0001DD82 dd effffffd24 pushl _dbl_st_acc+4
332: 319 0001DD88 fe 08 effffffd19 callf $8,_write32h
333: 320 0001DD8F # writec('\n');
334: 321 0001DD8F dd 0a pushl $10
335: 322 0001DD91 fe 08 effffffd10 callf $8,_writec
336: 323 0001DD98 # writes(" expected = ");
337: 324 0001DD98 .data 1
338: 325 00000d20 * L260:
339: 326 00000d20 * 2020206578706563746564203 .ascii " expected = \0"
340: D2000
341: 327 00000d2f * .text
342: 328 0001DD98 dd 8f00000d20 pushl $L260
343: 329 0001DD9E fe 08 effffffd03 callf $8,_writes
344: 330 0001DDA5 # write32h( dbl_expected.m );
345: 331 0001DDA5 dd effffffcfd pushl _dbl_expected
346: 332 0001DDAB fe 08 effffffcf6 callf $8,_write32h
347: 333 0001DDB2 # writec(' ');
348: 334 0001DDB2 dd 20 pushl $32
349: 335 0001DDB4 fe 08 effffffced callf $8,_writec
350: 336 0001DDBB # write32h( dbl_expected.l );
351: 337 0001DDBB dd effffffceb pushl _dbl_expected+4
352: 338 0001DDC1 fe 08 effffffce0 callf $8,_write32h
353: 339 0001DDC8 # writec('\n');
354: 340 0001DDC8 dd 0a pushl $10
355: 341 0001DDCA fe 08 effffffcd7 callf $8,_writec
356: 342 0001DDD1 # }
357: 343 0001DDD1 # if( halt_flg )
358: 344 0001DDD1 L253:
359: 345 0001DDD1 5d effffffcd1 tstl _halt_flg
360: 346 0001DDD7 31 09 jeql L261
361: 347 0001DDD9 # cvdl_er_halt( BAD_ACC_HLT ); /* halt on the error */
362: 348 0001DDD9 dd 01 pushl $1
363: 349 0001DDDB fe 08 ef000007e8 callf $8,_cvdl_er_halt
364: 350 0001DDE2 # if( loop_on_err ) {
365: 351 0001DDE2 L261:
366: 352 0001DDE2 5d effffffcc0 tstl _loop_on_err
367: 353 0001DDE8 31 0a jeql L262
368: 354 0001DDEA # force_loop = TRUE; /* set the force loop flag */
369: 355 0001DDEA 0d 01 effffffcb7 movl $1,_force_loop
370: 356 0001DDF1 # asm("brw _cvdl_1_lp1");; /* and loop on the error */
371: 357 0001DDF1 13 fd5b brw _cvdl_1_lp1
372: 358 0001DDF4 # } /* end of loop on error */
373: 359 0001DDF4 # } /* end of ACC compare error */
374: 360 0001DDF4 L262:
375: 361 0001DDF4 # } while( index++ < max_cvdl_1_index ); /* end of WHILE loop */
376: 362 0001DDF4 L252:
377: 363 0001DDF4 L231:
378: 364 0001DDF4 0d effffffcae 50 movl _index,r0
379: 365 0001DDFB 6d effffffca7 incl _index
380: 366 0001DE01 1d 50 effffffca0 cmpl r0,_max_cvdl_1_index
381: 367 0001DE08 81 03 13 fcfb jlss L232
382: 368 0001DE0D L230:
383: 369 0001DE0D # } /* end of subtest 1 */
384: 370 0001DE0D 40 ret#2
385: 371 0001DE0E .set L226,0x0
386: 372 0001DE0E L228:
387: 373 0001DE0E 13 fce4 jbr L229
388: 374 0001DE11 .data
389: 375 00000c48 * .text
390: 376 0001DE11 00 .align 1
391: 377 0001DE12 .globl _cvdl_2
392: 378 0001DE12 _cvdl_2:
393: 379 0001DE12 0000 .word L263
394: 380 0001DE14 #
395: 381 0001DE14 #
396: 382 0001DE14 #
397: 383 0001DE14 # /************************************************************************
398: 384 0001DE14 # *
399: 385 0001DE14 # * SUBTEST 2 - convert through memory
400: 386 0001DE14 # *
401: 387 0001DE14 # ************************************************************************/
402: 388 0001DE14 # cvdl_2()
403: 389 0001DE14 # {
404: 390 0001DE14 13 02f6 jbr L265
405: 391 0001DE17 L266:
406: 392 0001DE17 # force_loop = FALSE;
407: 393 0001DE17 4d effffffc8b clrl _force_loop
408: 394 0001DE1D # subtest = 2;
409: 395 0001DE1D 0d 02 effffffc84 movl $2,_subtest
410: 396 0001DE24 # index = 0;
411: 397 0001DE24 4d effffffc7e clrl _index
412: 398 0001DE2A # do
413: 399 0001DE2A L269:
414: 400 0001DE2A # {
415: 401 0001DE2A # dbl_ld_acc = cvdl_1_data[index].ld; /* get the operand */
416: 402 0001DE2A 5c 0c effffffc77 50 mull3 $12,_index,r0
417: 403 0001DE32 0c 8f00000000 50 addl2 $_cvdl_1_data,r0
418: 404 0001DE39 0d a004 effffffc6b movl 4(r0),_dbl_ld_acc+4
419: 405 0001DE41 0d 60 effffffc60 movl (r0),_dbl_ld_acc
420: 406 0001DE48 # sgl_expected = cvdl_1_data[index].exp; /* get expected result */
421: 407 0001DE48 5c 0c effffffc59 50 mull3 $12,_index,r0
422: 408 0001DE50 0d e000000008 effffffc4d movl _cvdl_1_data+8(r0),_sgl_expected
423: 409 0001DE5B # /*
424: 410 0001DE5B # * If LOOP ON ERROR is set, this is the loop for this subtest.
425: 411 0001DE5B # * The force loop flag is set after the first error.
426: 412 0001DE5B # */
427: 413 0001DE5B # asm("_cvdl_2_lp1:");
428: 414 0001DE5B _cvdl_2_lp1:
429: 415 0001DE5B # asm("ldd _dbl_ld_acc"); /* load the background */
430: 416 0001DE5B 07 effffffc47 ldd _dbl_ld_acc
431: 417 0001DE61 # asm("cvdl _sgl_value_3"); /* convert the value */
432: 418 0001DE61 87 effffffc41 cvdl _sgl_value_3
433: 419 0001DE67 # asm("nop");
434: 420 0001DE67 10 nop
435: 421 0001DE68 # asm("std _dbl_st_acc"); /* save the accumulator */
436: 422 0001DE68 27 effffffc3a std _dbl_st_acc
437: 423 0001DE6E # if( force_loop )
438: 424 0001DE6E 5d effffffc34 tstl _force_loop
439: 425 0001DE74 31 02 jeql L270
440: 426 0001DE76 # asm("brb _cvdl_2_lp1");; /* loop on the error */
441: 427 0001DE76 11 e3 brb _cvdl_2_lp1
442: 428 0001DE78 L270:
443: 429 0001DE78 # /*
444: 430 0001DE78 # * end error loop - test the results
445: 431 0001DE78 # */
446: 432 0001DE78 # if( sgl_value_3 != sgl_expected ) {/* COMPARE the values */
447: 433 0001DE78 1d effffffc2a effffffc25 cmpl _sgl_value_3,_sgl_expected
448: 434 0001DE83 21 03 13 00ff jeql L271
449: 435 0001DE88 # errcnt++; /* bump the error count */
450: 436 0001DE88 6d effffffc1a incl _errcnt
451: 437 0001DE8E # if( prt_error ) {
452: 438 0001DE8E 5d effffffc14 tstl _prt_error
453: 439 0001DE94 21 03 13 00cb jeql L272
454: 440 0001DE99 # writes(" \n"); /* start a new print line */
455: 441 0001DE99 .data 1
456: 442 00000d2f * L273:
457: 443 00000d2f * 200A00 .ascii " \12\0"
458: 444 00000d32 * .text
459: 445 0001DE99 dd 8f00000d2f pushl $L273
460: 446 0001DE9F fe 08 effffffc02 callf $8,_writes
461: 447 0001DEA6 # writes("cycle: ");
462: 448 0001DEA6 .data 1
463: 449 00000d32 * L274:
464: 450 00000d32 * 6379636C653A2000 .ascii "cycle: \0"
465: 451 00000d3a * .text
466: 452 0001DEA6 dd 8f00000d32 pushl $L274
467: 453 0001DEAC fe 08 effffffbf5 callf $8,_writes
468: 454 0001DEB3 # writed( cycle );
469: 455 0001DEB3 dd effffffbef pushl _cycle
470: 456 0001DEB9 fe 08 effffffbe8 callf $8,_writed
471: 457 0001DEC0 # writes(" CVDL test ");
472: 458 0001DEC0 .data 1
473: 459 00000d3a * L275:
474: 460 00000d3a * 20204356444C2074657374200 .ascii " CVDL test \0"
475: 0
476: 461 00000d47 * .text
477: 462 0001DEC0 dd 8f00000d3a pushl $L275
478: 463 0001DEC6 fe 08 effffffbdb callf $8,_writes
479: 464 0001DECD # writed( test_no );
480: 465 0001DECD dd effffffbd5 pushl _test_no
481: 466 0001DED3 fe 08 effffffbce callf $8,_writed
482: 467 0001DEDA # writes(", subtest 2 (Cache Data) - WRONG DATA STORED\n");
483: 468 0001DEDA .data 1
484: 469 00000d47 * L276:
485: 470 00000d47 * 2C20737562746573742032202 .ascii ", subtest 2 (Cache Data) - WRONG DATA STORED\12\0"
486: 8436163686520446174612920
487: 2D2057524F4E4720444154412
488: 053544F5245440A00
489: 471 00000d75 * .text
490: 472 0001DEDA dd 8f00000d47 pushl $L276
491: 473 0001DEE0 fe 08 effffffbc1 callf $8,_writes
492: 474 0001DEE7 # print_cvdl_data();
493: 475 0001DEE7 fe 04 ef0000068a callf $4,_print_cvdl_data
494: 476 0001DEEE # writes(", index = ");
495: 477 0001DEEE .data 1
496: 478 00000d75 * L277:
497: 479 00000d75 * 2C202020696E646578203D200 .ascii ", index = \0"
498: 0
499: 480 00000d82 * .text
500: 481 0001DEEE dd 8f00000d75 pushl $L277
501: 482 0001DEF4 fe 08 effffffbad callf $8,_writes
502: 483 0001DEFB # writed( index );
503: 484 0001DEFB dd effffffba7 pushl _index
504: 485 0001DF01 fe 08 effffffba0 callf $8,_writed
505: 486 0001DF08 # writec('\n');
506: 487 0001DF08 dd 0a pushl $10
507: 488 0001DF0A fe 08 effffffb97 callf $8,_writec
508: 489 0001DF11 # writes(" final Acc = ");
509: 490 0001DF11 .data 1
510: 491 00000d82 * L278:
511: 492 00000d82 * 202066696E616C20416363203 .ascii " final Acc = \0"
512: D2000
513: 493 00000d91 * .text
514: 494 0001DF11 dd 8f00000d82 pushl $L278
515: 495 0001DF17 fe 08 effffffb8a callf $8,_writes
516: 496 0001DF1E # write32h( dbl_st_acc.m );
517: 497 0001DF1E dd effffffb84 pushl _dbl_st_acc
518: 498 0001DF24 fe 08 effffffb7d callf $8,_write32h
519: 499 0001DF2B # writec(' ');
520: 500 0001DF2B dd 20 pushl $32
521: 501 0001DF2D fe 08 effffffb74 callf $8,_writec
522: 502 0001DF34 # write32h( dbl_st_acc.l );
523: 503 0001DF34 dd effffffb72 pushl _dbl_st_acc+4
524: 504 0001DF3A fe 08 effffffb67 callf $8,_write32h
525: 505 0001DF41 # writes(", int. expected = ");
526: 506 0001DF41 .data 1
527: 507 00000d91 * L279:
528: 508 00000d91 * 2C2020696E742E20657870656 .ascii ", int. expected = \0"
529: 3746564203D2000
530: 509 00000da5 * .text
531: 510 0001DF41 dd 8f00000d91 pushl $L279
532: 511 0001DF47 fe 08 effffffb5a callf $8,_writes
533: 512 0001DF4E # write32h( sgl_expected );
534: 513 0001DF4E dd effffffb54 pushl _sgl_expected
535: 514 0001DF54 fe 08 effffffb4d callf $8,_write32h
536: 515 0001DF5B # writec('\n');
537: 516 0001DF5B dd 0a pushl $10
538: 517 0001DF5D fe 08 effffffb44 callf $8,_writec
539: 518 0001DF64 # }
540: 519 0001DF64 # if( halt_flg )
541: 520 0001DF64 L272:
542: 521 0001DF64 5d effffffb3e tstl _halt_flg
543: 522 0001DF6A 31 09 jeql L280
544: 523 0001DF6C # cvdl_er_halt( BAD_STORE_HLT ); /* halt on the error */
545: 524 0001DF6C dd 09 pushl $9
546: 525 0001DF6E fe 08 ef00000655 callf $8,_cvdl_er_halt
547: 526 0001DF75 # if( loop_on_err ) {
548: 527 0001DF75 L280:
549: 528 0001DF75 5d effffffb2d tstl _loop_on_err
550: 529 0001DF7B 31 0a jeql L281
551: 530 0001DF7D # force_loop = TRUE; /* set the force loop flag */
552: 531 0001DF7D 0d 01 effffffb24 movl $1,_force_loop
553: 532 0001DF84 # asm("brw _cvdl_2_lp1");; /* and loop on the error */
554: 533 0001DF84 13 fed4 brw _cvdl_2_lp1
555: 534 0001DF87 # } /* end of loop on error */
556: 535 0001DF87 # } /* end of convert compare error */
557: 536 0001DF87 L281:
558: 537 0001DF87 # if( dbl_ld_acc.m & 0x7f800000 ) {
559: 538 0001DF87 L271:
560: 539 0001DF87 3d 8f7f800000 effffffb16 bitl $2139095040,_dbl_ld_acc
561: 540 0001DF92 31 18 jeql L282
562: 541 0001DF94 # dbl_expected.m = dbl_ld_acc.m; /* the Acc should */
563: 542 0001DF94 0d effffffb0e effffffb09 movl _dbl_ld_acc,_dbl_expected
564: 543 0001DF9F # dbl_expected.l = dbl_ld_acc.l; /* not change */
565: 544 0001DF9F 0d effffffb07 effffffb02 movl _dbl_ld_acc+4,_dbl_expected+4
566: 545 0001DFAA # } else {
567: 546 0001DFAA 11 0c jbr L283
568: 547 0001DFAC L282:
569: 548 0001DFAC # dbl_expected.m = 0; /* expect a '0' final Acc */
570: 549 0001DFAC 4d effffffaf6 clrl _dbl_expected
571: 550 0001DFB2 # dbl_expected.l = 0;
572: 551 0001DFB2 4d effffffaf4 clrl _dbl_expected+4
573: 552 0001DFB8 # }
574: 553 0001DFB8 L283:
575: 554 0001DFB8 # if( ( dbl_st_acc.m != dbl_expected.m ) ||
576: 555 0001DFB8 # ( dbl_st_acc.l != dbl_expected.l ) ) { /* COMPARE values */
577: 556 0001DFB8 1d effffffaea effffffae5 cmpl _dbl_st_acc,_dbl_expected
578: 557 0001DFC3 21 10 jneq L9998
579: 558 0001DFC5 1d effffffae1 effffffadc cmpl _dbl_st_acc+4,_dbl_expected+4
580: 559 0001DFD0 21 03 13 011e jeql L284
581: 560 0001DFD5 L9998:
582: 561 0001DFD5 # errcnt++; /* bump the error count */
583: 562 0001DFD5 6d effffffacd incl _errcnt
584: 563 0001DFDB # if( prt_error ) {
585: 564 0001DFDB 5d effffffac7 tstl _prt_error
586: 565 0001DFE1 21 03 13 00ea jeql L285
587: 566 0001DFE6 # writes(" \n"); /* start a new print line */
588: 567 0001DFE6 .data 1
589: 568 00000da5 * L286:
590: 569 00000da5 * 200A00 .ascii " \12\0"
591: 570 00000da8 * .text
592: 571 0001DFE6 dd 8f00000da5 pushl $L286
593: 572 0001DFEC fe 08 effffffab5 callf $8,_writes
594: 573 0001DFF3 # writes("cycle: ");
595: 574 0001DFF3 .data 1
596: 575 00000da8 * L287:
597: 576 00000da8 * 6379636C653A2000 .ascii "cycle: \0"
598: 577 00000db0 * .text
599: 578 0001DFF3 dd 8f00000da8 pushl $L287
600: 579 0001DFF9 fe 08 effffffaa8 callf $8,_writes
601: 580 0001E000 # writed( cycle );
602: 581 0001E000 dd effffffaa2 pushl _cycle
603: 582 0001E006 fe 08 effffffa9b callf $8,_writed
604: 583 0001E00D # writes(" CVDL test ");
605: 584 0001E00D .data 1
606: 585 00000db0 * L288:
607: 586 00000db0 * 20204356444C2074657374200 .ascii " CVDL test \0"
608: 0
609: 587 00000dbd * .text
610: 588 0001E00D dd 8f00000db0 pushl $L288
611: 589 0001E013 fe 08 effffffa8e callf $8,_writes
612: 590 0001E01A # writed( test_no );
613: 591 0001E01A dd effffffa88 pushl _test_no
614: 592 0001E020 fe 08 effffffa81 callf $8,_writed
615: 593 0001E027 # writes(", subtest 2 (Cache Data) - BAD FINAL ACC\n");
616: 594 0001E027 .data 1
617: 595 00000dbd * L289:
618: 596 00000dbd * 2C20737562746573742032202 .ascii ", subtest 2 (Cache Data) - BAD FINAL ACC\12\0"
619: 8436163686520446174612920
620: 2D204241442046494E414C204
621: 143430A00
622: 597 00000de7 * .text
623: 598 0001E027 dd 8f00000dbd pushl $L289
624: 599 0001E02D fe 08 effffffa74 callf $8,_writes
625: 600 0001E034 # print_cvdl_data();
626: 601 0001E034 fe 04 ef0000053d callf $4,_print_cvdl_data
627: 602 0001E03B # writes(", index = ");
628: 603 0001E03B .data 1
629: 604 00000de7 * L290:
630: 605 00000de7 * 2C202020696E646578203D200 .ascii ", index = \0"
631: 0
632: 606 00000df4 * .text
633: 607 0001E03B dd 8f00000de7 pushl $L290
634: 608 0001E041 fe 08 effffffa60 callf $8,_writes
635: 609 0001E048 # writed( index );
636: 610 0001E048 dd effffffa5a pushl _index
637: 611 0001E04E fe 08 effffffa53 callf $8,_writed
638: 612 0001E055 # writec('\n');
639: 613 0001E055 dd 0a pushl $10
640: 614 0001E057 fe 08 effffffa4a callf $8,_writec
641: 615 0001E05E # writes(" final Acc = ");
642: 616 0001E05E .data 1
643: 617 00000df4 * L291:
644: 618 00000df4 * 202066696E616C20416363203 .ascii " final Acc = \0"
645: D2000
646: 619 00000e03 * .text
647: 620 0001E05E dd 8f00000df4 pushl $L291
648: 621 0001E064 fe 08 effffffa3d callf $8,_writes
649: 622 0001E06B # write32h( dbl_st_acc.m );
650: 623 0001E06B dd effffffa37 pushl _dbl_st_acc
651: 624 0001E071 fe 08 effffffa30 callf $8,_write32h
652: 625 0001E078 # writec(' ');
653: 626 0001E078 dd 20 pushl $32
654: 627 0001E07A fe 08 effffffa27 callf $8,_writec
655: 628 0001E081 # write32h( dbl_st_acc.l );
656: 629 0001E081 dd effffffa25 pushl _dbl_st_acc+4
657: 630 0001E087 fe 08 effffffa1a callf $8,_write32h
658: 631 0001E08E # writec('\n');
659: 632 0001E08E dd 0a pushl $10
660: 633 0001E090 fe 08 effffffa11 callf $8,_writec
661: 634 0001E097 # writes(" expected = ");
662: 635 0001E097 .data 1
663: 636 00000e03 * L292:
664: 637 00000e03 * 2020206578706563746564203 .ascii " expected = \0"
665: D2000
666: 638 00000e12 * .text
667: 639 0001E097 dd 8f00000e03 pushl $L292
668: 640 0001E09D fe 08 effffffa04 callf $8,_writes
669: 641 0001E0A4 # write32h( dbl_expected.m );
670: 642 0001E0A4 dd effffff9fe pushl _dbl_expected
671: 643 0001E0AA fe 08 effffff9f7 callf $8,_write32h
672: 644 0001E0B1 # writec(' ');
673: 645 0001E0B1 dd 20 pushl $32
674: 646 0001E0B3 fe 08 effffff9ee callf $8,_writec
675: 647 0001E0BA # write32h( dbl_expected.l );
676: 648 0001E0BA dd effffff9ec pushl _dbl_expected+4
677: 649 0001E0C0 fe 08 effffff9e1 callf $8,_write32h
678: 650 0001E0C7 # writec('\n');
679: 651 0001E0C7 dd 0a pushl $10
680: 652 0001E0C9 fe 08 effffff9d8 callf $8,_writec
681: 653 0001E0D0 # }
682: 654 0001E0D0 # if( halt_flg )
683: 655 0001E0D0 L285:
684: 656 0001E0D0 5d effffff9d2 tstl _halt_flg
685: 657 0001E0D6 31 09 jeql L293
686: 658 0001E0D8 # cvdl_er_halt( BAD_ACC_HLT ); /* halt on the error */
687: 659 0001E0D8 dd 01 pushl $1
688: 660 0001E0DA fe 08 ef000004e9 callf $8,_cvdl_er_halt
689: 661 0001E0E1 # if( loop_on_err ) {
690: 662 0001E0E1 L293:
691: 663 0001E0E1 5d effffff9c1 tstl _loop_on_err
692: 664 0001E0E7 31 0a jeql L294
693: 665 0001E0E9 # force_loop = TRUE; /* set the force loop flag */
694: 666 0001E0E9 0d 01 effffff9b8 movl $1,_force_loop
695: 667 0001E0F0 # asm("brw _cvdl_1_lp1");; /* and loop on the error */
696: 668 0001E0F0 13 fa5c brw _cvdl_1_lp1
697: 669 0001E0F3 # } /* end of loop on error */
698: 670 0001E0F3 # } /* end of ACC compare error */
699: 671 0001E0F3 L294:
700: 672 0001E0F3 # } while( index++ < max_cvdl_1_index ); /* end of WHILE loop */
701: 673 0001E0F3 L284:
702: 674 0001E0F3 L268:
703: 675 0001E0F3 0d effffff9af 50 movl _index,r0
704: 676 0001E0FA 6d effffff9a8 incl _index
705: 677 0001E100 1d 50 effffff9a1 cmpl r0,_max_cvdl_1_index
706: 678 0001E107 81 03 13 fd1e jlss L269
707: 679 0001E10C L267:
708: 680 0001E10C # } /* end of subtest 2 */
709: 681 0001E10C 40 ret#2
710: 682 0001E10D .set L263,0x0
711: 683 0001E10D L265:
712: 684 0001E10D 13 fd07 jbr L266
713: 685 0001E110 .data
714: 686 00000c48 * .text
715: 687 0001E110 .align 1
716: 688 0001E110 .globl _cvdl_3
717: 689 0001E110 _cvdl_3:
718: 690 0001E110 0000 .word L295
719: 691 0001E112 #
720: 692 0001E112 #
721: 693 0001E112 #
722: 694 0001E112 # /************************************************************************
723: 695 0001E112 # *
724: 696 0001E112 # * SUBTEST 3 - Check for register corruption
725: 697 0001E112 # *
726: 698 0001E112 # ************************************************************************/
727: 699 0001E112 # cvdl_3()
728: 700 0001E112 # {
729: 701 0001E112 13 0210 jbr L297
730: 702 0001E115 L298:
731: 703 0001E115 # force_loop = FALSE; /* clear force_loop flg */
732: 704 0001E115 4d effffff98d clrl _force_loop
733: 705 0001E11B # subtest = 3;
734: 706 0001E11B 0d 03 effffff986 movl $3,_subtest
735: 707 0001E122 # fill_reg_buf( load_regs ); /* get patterns for regs */
736: 708 0001E122 dd 8f00000000 pushl $_load_regs
737: 709 0001E128 fe 08 effffff979 callf $8,_fill_reg_buf
738: 710 0001E12F # index = 0;
739: 711 0001E12F 4d effffff973 clrl _index
740: 712 0001E135 # dbl_ld_acc = cvdl_1_data[index].ld; /* get the operand */
741: 713 0001E135 5c 0c effffff96c 50 mull3 $12,_index,r0
742: 714 0001E13D 0c 8f00000000 50 addl2 $_cvdl_1_data,r0
743: 715 0001E144 0d a004 effffff960 movl 4(r0),_dbl_ld_acc+4
744: 716 0001E14C 0d 60 effffff955 movl (r0),_dbl_ld_acc
745: 717 0001E153 # sgl_expected = cvdl_1_data[index].exp; /* get expected result */
746: 718 0001E153 5c 0c effffff94e 50 mull3 $12,_index,r0
747: 719 0001E15B 0d e000000008 effffff942 movl _cvdl_1_data+8(r0),_sgl_expected
748: 720 0001E166 # /*
749: 721 0001E166 # * If LOOP ON ERROR is set, this is the loop for this subtest.
750: 722 0001E166 # * The force loop flag is set after the first error.
751: 723 0001E166 # */
752: 724 0001E166 # asm("_cvdl_3_lp1:");
753: 725 0001E166 _cvdl_3_lp1:
754: 726 0001E166 # asm("ldd _dbl_ld_acc"); /* load base value */
755: 727 0001E166 07 effffff93c ldd _dbl_ld_acc
756: 728 0001E16C # asm("loadr $0x1fff,_load_regs"); /* load regs 0 - 12 */
757: 729 0001E16C ab 891fff effffff933 loadr $0x1fff,_load_regs
758: 730 0001E175 # asm("nop");
759: 731 0001E175 10 nop
760: 732 0001E176 # asm("cvdl _sgl_value_3"); /* convert the value */
761: 733 0001E176 87 effffff92c cvdl _sgl_value_3
762: 734 0001E17C # asm("nop");
763: 735 0001E17C 10 nop
764: 736 0001E17D # asm("storer $0x1fff,_store_regs"); /* store regs 0 - 12 */
765: 737 0001E17D bb 891fff effffff922 storer $0x1fff,_store_regs
766: 738 0001E186 # asm("std _dbl_st_acc"); /* save the accumulator */
767: 739 0001E186 27 effffff91c std _dbl_st_acc
768: 740 0001E18C # if( force_loop )
769: 741 0001E18C 5d effffff916 tstl _force_loop
770: 742 0001E192 31 02 jeql L300
771: 743 0001E194 # asm("brb _cvdl_3_lp1");; /* loop on the error */
772: 744 0001E194 11 d0 brb _cvdl_3_lp1
773: 745 0001E196 L300:
774: 746 0001E196 # /*
775: 747 0001E196 # * Now compare the stored register values to those that were loaded
776: 748 0001E196 # */
777: 749 0001E196 # index2 = 0;
778: 750 0001E196 4d effffff90c clrl _index2
779: 751 0001E19C # while( (load_regs[index2] == store_regs[index2]) && (index2 < 13) )
780: 752 0001E19C L301:
781: 753 0001E19C 0d effffff906 50 movl _index2,r0
782: 754 0001E1A3 0d effffff8ff 51 movl _index2,r1
783: 755 0001E1AA 1d 40effffff8f7 cmpl _load_regs[r0],_store_regs[r1]
784: 41effffff8f1
785: 756 0001E1B7 21 11 jneq L302
786: 757 0001E1B9 1d effffff8e9 0d cmpl _index2,$13
787: 758 0001E1C0 81 08 jgeq L302
788: 759 0001E1C2 # index2++; /* check reg values */
789: 760 0001E1C2 6d effffff8e0 incl _index2
790: 761 0001E1C8 11 d2 jbr L301
791: 762 0001E1CA L302:
792: 763 0001E1CA # if( index2 < 13 ) { /* error if index2 < 13 */
793: 764 0001E1CA 1d effffff8d8 0d cmpl _index2,$13
794: 765 0001E1D1 91 03 13 0136 jgeq L303
795: 766 0001E1D6 # errcnt++; /* bump the error count */
796: 767 0001E1D6 6d effffff8cc incl _errcnt
797: 768 0001E1DC # if( prt_error ) {
798: 769 0001E1DC 5d effffff8c6 tstl _prt_error
799: 770 0001E1E2 21 03 13 0102 jeql L304
800: 771 0001E1E7 # writes(" \n"); /* start a new print line */
801: 772 0001E1E7 .data 1
802: 773 00000e12 * L305:
803: 774 00000e12 * 200A00 .ascii " \12\0"
804: 775 00000e15 * .text
805: 776 0001E1E7 dd 8f00000e12 pushl $L305
806: 777 0001E1ED fe 08 effffff8b4 callf $8,_writes
807: 778 0001E1F4 # writes("cycle: ");
808: 779 0001E1F4 .data 1
809: 780 00000e15 * L306:
810: 781 00000e15 * 6379636C653A2000 .ascii "cycle: \0"
811: 782 00000e1d * .text
812: 783 0001E1F4 dd 8f00000e15 pushl $L306
813: 784 0001E1FA fe 08 effffff8a7 callf $8,_writes
814: 785 0001E201 # writed( cycle );
815: 786 0001E201 dd effffff8a1 pushl _cycle
816: 787 0001E207 fe 08 effffff89a callf $8,_writed
817: 788 0001E20E # writes(" CVDL test ");
818: 789 0001E20E .data 1
819: 790 00000e1d * L307:
820: 791 00000e1d * 20204356444C2074657374200 .ascii " CVDL test \0"
821: 0
822: 792 00000e2a * .text
823: 793 0001E20E dd 8f00000e1d pushl $L307
824: 794 0001E214 fe 08 effffff88d callf $8,_writes
825: 795 0001E21B # writed( test_no );
826: 796 0001E21B dd effffff887 pushl _test_no
827: 797 0001E221 fe 08 effffff880 callf $8,_writed
828: 798 0001E228 # writes(", subtest 3 - A REGISTER WAS MODIFIED\n");
829: 799 0001E228 .data 1
830: 800 00000e2a * L308:
831: 801 00000e2a * 2C20737562746573742033202 .ascii ", subtest 3 - A REGISTER WAS MODIFIED\12\0"
832: D204120524547495354455220
833: 574153204D4F4449464945440
834: A00
835: 802 00000e51 * .text
836: 803 0001E228 dd 8f00000e2a pushl $L308
837: 804 0001E22E fe 08 effffff873 callf $8,_writes
838: 805 0001E235 # print_cvdl_data(); /* print the operands */
839: 806 0001E235 fe 04 ef0000033c callf $4,_print_cvdl_data
840: 807 0001E23C # writec('\n');
841: 808 0001E23C dd 0a pushl $10
842: 809 0001E23E fe 08 effffff863 callf $8,_writec
843: 810 0001E245 # writes(" final Acc = ");
844: 811 0001E245 .data 1
845: 812 00000e51 * L309:
846: 813 00000e51 * 202066696E616C20416363203 .ascii " final Acc = \0"
847: D2000
848: 814 00000e60 * .text
849: 815 0001E245 dd 8f00000e51 pushl $L309
850: 816 0001E24B fe 08 effffff856 callf $8,_writes
851: 817 0001E252 # write32h( dbl_st_acc.m );
852: 818 0001E252 dd effffff850 pushl _dbl_st_acc
853: 819 0001E258 fe 08 effffff849 callf $8,_write32h
854: 820 0001E25F # writec(' ');
855: 821 0001E25F dd 20 pushl $32
856: 822 0001E261 fe 08 effffff840 callf $8,_writec
857: 823 0001E268 # write32h( dbl_st_acc.l );
858: 824 0001E268 dd effffff83e pushl _dbl_st_acc+4
859: 825 0001E26E fe 08 effffff833 callf $8,_write32h
860: 826 0001E275 # writec('\n');
861: 827 0001E275 dd 0a pushl $10
862: 828 0001E277 fe 08 effffff82a callf $8,_writec
863: 829 0001E27E # writes("register "); /* print the information */
864: 830 0001E27E .data 1
865: 831 00000e60 * L310:
866: 832 00000e60 * 72656769737465722000 .ascii "register \0"
867: 833 00000e6a * .text
868: 834 0001E27E dd 8f00000e60 pushl $L310
869: 835 0001E284 fe 08 effffff81d callf $8,_writes
870: 836 0001E28B # writed( index2 ); /* about the corrupted */
871: 837 0001E28B dd effffff817 pushl _index2
872: 838 0001E291 fe 08 effffff810 callf $8,_writed
873: 839 0001E298 # writes(" = "); /* register */
874: 840 0001E298 .data 1
875: 841 00000e6a * L311:
876: 842 00000e6a * 203D2000 .ascii " = \0"
877: 843 00000e6e * .text
878: 844 0001E298 dd 8f00000e6a pushl $L311
879: 845 0001E29E fe 08 effffff803 callf $8,_writes
880: 846 0001E2A5 # write32h( store_regs[index2] );
881: 847 0001E2A5 0d effffff7fd 50 movl _index2,r0
882: 848 0001E2AC dd 40effffff7f5 pushl _store_regs[r0]
883: 849 0001E2B3 fe 08 effffff7ee callf $8,_write32h
884: 850 0001E2BA # writes(", should be = ");
885: 851 0001E2BA .data 1
886: 852 00000e6e * L312:
887: 853 00000e6e * 2C202073686F756C642062652 .ascii ", should be = \0"
888: 03D2000
889: 854 00000e7e * .text
890: 855 0001E2BA dd 8f00000e6e pushl $L312
891: 856 0001E2C0 fe 08 effffff7e1 callf $8,_writes
892: 857 0001E2C7 # write32h( load_regs[index2] );
893: 858 0001E2C7 0d effffff7db 50 movl _index2,r0
894: 859 0001E2CE dd 40effffff7d3 pushl _load_regs[r0]
895: 860 0001E2D5 fe 08 effffff7cc callf $8,_write32h
896: 861 0001E2DC # writes("\n");
897: 862 0001E2DC .data 1
898: 863 00000e7e * L313:
899: 864 00000e7e * 0A00 .ascii "\12\0"
900: 865 00000e80 * .text
901: 866 0001E2DC dd 8f00000e7e pushl $L313
902: 867 0001E2E2 fe 08 effffff7bf callf $8,_writes
903: 868 0001E2E9 # }
904: 869 0001E2E9 # if( halt_flg )
905: 870 0001E2E9 L304:
906: 871 0001E2E9 5d effffff7b9 tstl _halt_flg
907: 872 0001E2EF 31 09 jeql L314
908: 873 0001E2F1 # cvdl_er_halt( BAD_REG_HLT ); /* halt on the error */
909: 874 0001E2F1 dd 02 pushl $2
910: 875 0001E2F3 fe 08 ef000002d0 callf $8,_cvdl_er_halt
911: 876 0001E2FA # if( loop_on_err ) {
912: 877 0001E2FA L314:
913: 878 0001E2FA 5d effffff7a8 tstl _loop_on_err
914: 879 0001E300 31 0a jeql L315
915: 880 0001E302 # force_loop = TRUE; /* set the force loop flag */
916: 881 0001E302 0d 01 effffff79f movl $1,_force_loop
917: 882 0001E309 # asm("brw _cvdl_3_lp1");; /* and loop on the error */
918: 883 0001E309 13 fe5a brw _cvdl_3_lp1
919: 884 0001E30C # } /* end of loop on error */
920: 885 0001E30C # } while( index++ < max_cvdl_1_index );/* end of reg corruption error */
921: 886 0001E30C L315:
922: 887 0001E30C L303:
923: 888 0001E30C L316:
924: 889 0001E30C 0d effffff796 50 movl _index,r0
925: 890 0001E313 6d effffff78f incl _index
926: 891 0001E319 1d 50 effffff788 cmpl r0,_max_cvdl_1_index
927: 892 0001E320 81 02 jgeq L317
928: 893 0001E322 11 e8 jbr L316
929: 894 0001E324 L317:
930: 895 0001E324 # } /* end of subtest 3 */
931: 896 0001E324 40 ret#2
932: 897 0001E325 .set L295,0x0
933: 898 0001E325 L297:
934: 899 0001E325 13 fded jbr L298
935: 900 0001E328 .data
936: 901 00000c48 * .text
937: 902 0001E328 .align 1
938: 903 0001E328 .globl _cvdl_4
939: 904 0001E328 _cvdl_4:
940: 905 0001E328 0000 .word L318
941: 906 0001E32A #
942: 907 0001E32A #
943: 908 0001E32A #
944: 909 0001E32A # /************************************************************************
945: 910 0001E32A # *
946: 911 0001E32A # * SUBTEST 4 - Check for PSL corruption
947: 912 0001E32A # *
948: 913 0001E32A # ************************************************************************/
949: 914 0001E32A # cvdl_4()
950: 915 0001E32A # {
951: 916 0001E32A 13 0247 jbr L320
952: 917 0001E32D L321:
953: 918 0001E32D # force_loop = FALSE; /* clear force_loop flg */
954: 919 0001E32D 4d effffff775 clrl _force_loop
955: 920 0001E333 # subtest = 4;
956: 921 0001E333 0d 04 effffff76e movl $4,_subtest
957: 922 0001E33A # for( index = 0; index < max_cvdl_1_index; index++ ) {
958: 923 0001E33A 4d effffff768 clrl _index
959: 924 0001E340 L324:
960: 925 0001E340 1d effffff762 effffff75d cmpl _index,_max_cvdl_1_index
961: 926 0001E34B 91 03 13 0223 jgeq L323
962: 927 0001E350 # dbl_ld_acc = cvdl_1_data[index].ld; /* get the operand */
963: 928 0001E350 5c 0c effffff751 50 mull3 $12,_index,r0
964: 929 0001E358 0c 8f00000000 50 addl2 $_cvdl_1_data,r0
965: 930 0001E35F 0d a004 effffff745 movl 4(r0),_dbl_ld_acc+4
966: 931 0001E367 0d 60 effffff73a movl (r0),_dbl_ld_acc
967: 932 0001E36E # sgl_expected = cvdl_1_data[index].exp; /* get expected */
968: 933 0001E36E 5c 0c effffff733 50 mull3 $12,_index,r0
969: 934 0001E376 0d e000000008 effffff727 movl _cvdl_1_data+8(r0),_sgl_expected
970: 935 0001E381 # sgl_value_1 = dbl_ld_acc.m;
971: 936 0001E381 0d effffff721 effffff71c movl _dbl_ld_acc,_sgl_value_1
972: 937 0001E38C # sgl_value_2 = dbl_ld_acc.l;
973: 938 0001E38C 0d effffff71a effffff711 movl _dbl_ld_acc+4,_sgl_value_2
974: 939 0001E397 # for( status_index = 0; status_index < 3; status_index++ ) {
975: 940 0001E397 4d effffff70b clrl _status_index
976: 941 0001E39D L327:
977: 942 0001E39D 1d effffff705 03 cmpl _status_index,$3
978: 943 0001E3A4 91 03 13 01c1 jgeq L326
979: 944 0001E3A9 # sgl_dummy1 = status_array[status_index];/* status = +, -, 0 */
980: 945 0001E3A9 0d effffff6f9 50 movl _status_index,r0
981: 946 0001E3B0 0d 40effffff6f1 movl _status_array[r0],_sgl_dummy1
982: effffff6ec
983: 947 0001E3BC # /*
984: 948 0001E3BC # * If LOOP ON ERROR is set, this is the loop for this subtest.
985: 949 0001E3BC # * The force loop flag is set after the first error.
986: 950 0001E3BC # */
987: 951 0001E3BC # asm("_cvdl_4_lp1:");
988: 952 0001E3BC _cvdl_4_lp1:
989: 953 0001E3BC # asm("movl _sgl_value_1,r4"); /* put MS value in r4 */
990: 954 0001E3BC 0d effffff6e6 54 movl _sgl_value_1,r4
991: 955 0001E3C3 # asm("movl _sgl_value_2,r5"); /* put LS value in r5 */
992: 956 0001E3C3 0d effffff6df 55 movl _sgl_value_2,r5
993: 957 0001E3CA # asm("ldd r4"); /* load the acc */
994: 958 0001E3CA 07 54 ldd r4
995: 959 0001E3CC # asm("tstl _sgl_dummy1"); /* set the PSL status */
996: 960 0001E3CC 5d effffff6d6 tstl _sgl_dummy1
997: 961 0001E3D2 # asm("movpsl _init_psl"); /* save the initial PSL */
998: 962 0001E3D2 cd effffff6d0 movpsl _init_psl
999: 963 0001E3D8 # asm("nop");
1000: 964 0001E3D8 10 nop
1001: 965 0001E3D9 # asm("cvdl r8"); /* convert the value */
1002: 966 0001E3D9 87 58 cvdl r8
1003: 967 0001E3DB # asm("nop");
1004: 968 0001E3DB 10 nop
1005: 969 0001E3DC # asm("movpsl _psl_val"); /* save the final PSL */
1006: 970 0001E3DC cd effffff6c6 movpsl _psl_val
1007: 971 0001E3E2 # asm("nop");
1008: 972 0001E3E2 10 nop
1009: 973 0001E3E3 # asm("std _dbl_st_acc"); /* save the accumulator */
1010: 974 0001E3E3 27 effffff6bf std _dbl_st_acc
1011: 975 0001E3E9 # if( force_loop )
1012: 976 0001E3E9 5d effffff6b9 tstl _force_loop
1013: 977 0001E3EF 31 02 jeql L328
1014: 978 0001E3F1 # asm("brb _cvdl_4_lp1");; /* loop on the error */
1015: 979 0001E3F1 11 c9 brb _cvdl_4_lp1
1016: 980 0001E3F3 L328:
1017: 981 0001E3F3 # /*
1018: 982 0001E3F3 # * Now compare the final PSL to the initial PSL -they should be the same
1019: 983 0001E3F3 # */
1020: 984 0001E3F3 # asm("movl r8,_sgl_value_3"); /* mave result to cache */
1021: 985 0001E3F3 0d 58 effffff6ae movl r8,_sgl_value_3
1022: 986 0001E3FA # exp_psl = init_psl; /* get the initial PSL */
1023: 987 0001E3FA 0d effffff6a8 effffff6a3 movl _init_psl,_exp_psl
1024: 988 0001E405 # exp_psl &= 0xfffffff3; /* clear ZERO, NEGATIVE */
1025: 989 0001E405 ac 88f3 effffff69b andl2 $-13,_exp_psl
1026: 990 0001E40D # if( !sgl_expected )
1027: 991 0001E40D 5d effffff695 tstl _sgl_expected
1028: 992 0001E413 21 07 jneq L329
1029: 993 0001E415 # exp_psl |= PSL_Z; /* expect ZERO bit set */
1030: 994 0001E415 8c 04 effffff68c orl2 $4,_exp_psl
1031: 995 0001E41C # if( sgl_expected < 0 )
1032: 996 0001E41C L329:
1033: 997 0001E41C 5d effffff686 tstl _sgl_expected
1034: 998 0001E422 81 07 jgeq L330
1035: 999 0001E424 # exp_psl |= PSL_N; /* expect NEG bit set */
1036: 1000 0001E424 8c 08 effffff67d orl2 $8,_exp_psl
1037: 1001 0001E42B # if( psl_val != exp_psl ) {
1038: 1002 0001E42B L330:
1039: 1003 0001E42B 1d effffff677 effffff672 cmpl _psl_val,_exp_psl
1040: 1004 0001E436 21 03 13 0126 jeql L331
1041: 1005 0001E43B # errcnt++; /* bump error count */
1042: 1006 0001E43B 6d effffff667 incl _errcnt
1043: 1007 0001E441 # if( prt_error ) {
1044: 1008 0001E441 5d effffff661 tstl _prt_error
1045: 1009 0001E447 21 03 13 00f2 jeql L332
1046: 1010 0001E44C # writes(" \n"); /* start new print line */
1047: 1011 0001E44C .data 1
1048: 1012 00000e80 * L333:
1049: 1013 00000e80 * 200A00 .ascii " \12\0"
1050: 1014 00000e83 * .text
1051: 1015 0001E44C dd 8f00000e80 pushl $L333
1052: 1016 0001E452 fe 08 effffff64f callf $8,_writes
1053: 1017 0001E459 # writes("cycle: ");
1054: 1018 0001E459 .data 1
1055: 1019 00000e83 * L334:
1056: 1020 00000e83 * 6379636C653A2000 .ascii "cycle: \0"
1057: 1021 00000e8b * .text
1058: 1022 0001E459 dd 8f00000e83 pushl $L334
1059: 1023 0001E45F fe 08 effffff642 callf $8,_writes
1060: 1024 0001E466 # writed( cycle );
1061: 1025 0001E466 dd effffff63c pushl _cycle
1062: 1026 0001E46C fe 08 effffff635 callf $8,_writed
1063: 1027 0001E473 # writes(
1064: 1028 0001E473 # " CVDL test 24, subtest 4 - INCORRECT FINAL PSL\n");
1065: 1029 0001E473 .data 1
1066: 1030 00000e8b * L335:
1067: 1031 00000e8b * 20204356444C2074657374203 .ascii " CVDL test 24, subtest 4 - INCORRECT FINAL PSL\12\0"
1068: 2342C20737562746573742034
1069: 202D20494E434F52524543542
1070: 046494E414C2050534C0A00
1071: 1032 00000ebc * .text
1072: 1033 0001E473 dd 8f00000e8b pushl $L335
1073: 1034 0001E479 fe 08 effffff628 callf $8,_writes
1074: 1035 0001E480 # print_cvdl_data(); /* print operands */
1075: 1036 0001E480 fe 04 ef000000f1 callf $4,_print_cvdl_data
1076: 1037 0001E487 # writes(", index = ");
1077: 1038 0001E487 .data 1
1078: 1039 00000ebc * L336:
1079: 1040 00000ebc * 2C202020696E646578203D200 .ascii ", index = \0"
1080: 0
1081: 1041 00000ec9 * .text
1082: 1042 0001E487 dd 8f00000ebc pushl $L336
1083: 1043 0001E48D fe 08 effffff614 callf $8,_writes
1084: 1044 0001E494 # writed( index );
1085: 1045 0001E494 dd effffff60e pushl _index
1086: 1046 0001E49A fe 08 effffff607 callf $8,_writed
1087: 1047 0001E4A1 # writec('\n');
1088: 1048 0001E4A1 dd 0a pushl $10
1089: 1049 0001E4A3 fe 08 effffff5fe callf $8,_writec
1090: 1050 0001E4AA # writes(" final Acc = ");
1091: 1051 0001E4AA .data 1
1092: 1052 00000ec9 * L337:
1093: 1053 00000ec9 * 202066696E616C20416363203 .ascii " final Acc = \0"
1094: D2000
1095: 1054 00000ed8 * .text
1096: 1055 0001E4AA dd 8f00000ec9 pushl $L337
1097: 1056 0001E4B0 fe 08 effffff5f1 callf $8,_writes
1098: 1057 0001E4B7 # write32h( dbl_st_acc.m );
1099: 1058 0001E4B7 dd effffff5eb pushl _dbl_st_acc
1100: 1059 0001E4BD fe 08 effffff5e4 callf $8,_write32h
1101: 1060 0001E4C4 # writec(' ');
1102: 1061 0001E4C4 dd 20 pushl $32
1103: 1062 0001E4C6 fe 08 effffff5db callf $8,_writec
1104: 1063 0001E4CD # write32h( dbl_st_acc.l );
1105: 1064 0001E4CD dd effffff5d9 pushl _dbl_st_acc+4
1106: 1065 0001E4D3 fe 08 effffff5ce callf $8,_write32h
1107: 1066 0001E4DA # writec('\n');
1108: 1067 0001E4DA dd 0a pushl $10
1109: 1068 0001E4DC fe 08 effffff5c5 callf $8,_writec
1110: 1069 0001E4E3 # writes("initial PSL = ");
1111: 1070 0001E4E3 .data 1
1112: 1071 00000ed8 * L338:
1113: 1072 00000ed8 * 696E697469616C2050534C203 .ascii "initial PSL = \0"
1114: D2000
1115: 1073 00000ee7 * .text
1116: 1074 0001E4E3 dd 8f00000ed8 pushl $L338
1117: 1075 0001E4E9 fe 08 effffff5b8 callf $8,_writes
1118: 1076 0001E4F0 # write32h( init_psl );
1119: 1077 0001E4F0 dd effffff5b2 pushl _init_psl
1120: 1078 0001E4F6 fe 08 effffff5ab callf $8,_write32h
1121: 1079 0001E4FD # writes(", final PSL = ");
1122: 1080 0001E4FD .data 1
1123: 1081 00000ee7 * L339:
1124: 1082 00000ee7 * 2C202066696E616C2050534C2 .ascii ", final PSL = \0"
1125: 03D2000
1126: 1083 00000ef7 * .text
1127: 1084 0001E4FD dd 8f00000ee7 pushl $L339
1128: 1085 0001E503 fe 08 effffff59e callf $8,_writes
1129: 1086 0001E50A # write32h( psl_val );
1130: 1087 0001E50A dd effffff598 pushl _psl_val
1131: 1088 0001E510 fe 08 effffff591 callf $8,_write32h
1132: 1089 0001E517 # writes(", expected PSL = ");
1133: 1090 0001E517 .data 1
1134: 1091 00000ef7 * L340:
1135: 1092 00000ef7 * 2C20206578706563746564205 .ascii ", expected PSL = \0"
1136: 0534C203D2000
1137: 1093 00000f0a * .text
1138: 1094 0001E517 dd 8f00000ef7 pushl $L340
1139: 1095 0001E51D fe 08 effffff584 callf $8,_writes
1140: 1096 0001E524 # write32h( exp_psl );
1141: 1097 0001E524 dd effffff57e pushl _exp_psl
1142: 1098 0001E52A fe 08 effffff577 callf $8,_write32h
1143: 1099 0001E531 # writes("\n");
1144: 1100 0001E531 .data 1
1145: 1101 00000f0a * L341:
1146: 1102 00000f0a * 0A00 .ascii "\12\0"
1147: 1103 00000f0c * .text
1148: 1104 0001E531 dd 8f00000f0a pushl $L341
1149: 1105 0001E537 fe 08 effffff56a callf $8,_writes
1150: 1106 0001E53E # }
1151: 1107 0001E53E # if( halt_flg )
1152: 1108 0001E53E L332:
1153: 1109 0001E53E 5d effffff564 tstl _halt_flg
1154: 1110 0001E544 31 09 jeql L342
1155: 1111 0001E546 # cvdl_er_halt( BAD_PSL_HLT ); /* halt on error */
1156: 1112 0001E546 dd 03 pushl $3
1157: 1113 0001E548 fe 08 ef0000007b callf $8,_cvdl_er_halt
1158: 1114 0001E54F # if( loop_on_err ) {
1159: 1115 0001E54F L342:
1160: 1116 0001E54F 5d effffff553 tstl _loop_on_err
1161: 1117 0001E555 31 0a jeql L343
1162: 1118 0001E557 # force_loop = TRUE; /* set force loop flag */
1163: 1119 0001E557 0d 01 effffff54a movl $1,_force_loop
1164: 1120 0001E55E # asm("brw _cvdl_4_lp1");; /* and loop on error */
1165: 1121 0001E55E 13 fe5b brw _cvdl_4_lp1
1166: 1122 0001E561 # } /* end of loop on error */
1167: 1123 0001E561 # } /* end of PSL corruption error */
1168: 1124 0001E561 L343:
1169: 1125 0001E561 # } /* end of status WHILE loop */
1170: 1126 0001E561 L331:
1171: 1127 0001E561 L325:
1172: 1128 0001E561 6d effffff541 incl _status_index
1173: 1129 0001E567 13 fe33 jbr L327
1174: 1130 0001E56A L326:
1175: 1131 0001E56A # } /* end of data WHILE loop */
1176: 1132 0001E56A L322:
1177: 1133 0001E56A 6d effffff538 incl _index
1178: 1134 0001E570 13 fdcd jbr L324
1179: 1135 0001E573 L323:
1180: 1136 0001E573 # } /* end of subtest 4 */
1181: 1137 0001E573 40 ret#2
1182: 1138 0001E574 .set L318,0x0
1183: 1139 0001E574 L320:
1184: 1140 0001E574 13 fdb6 jbr L321
1185: 1141 0001E577 .data
1186: 1142 00000c48 * .text
1187: 1143 0001E577 00 .align 1
1188: 1144 0001E578 .globl _print_cvdl_data
1189: 1145 0001E578 _print_cvdl_data:
1190: 1146 0001E578 0000 .word L344
1191: 1147 0001E57A #
1192: 1148 0001E57A #
1193: 1149 0001E57A #
1194: 1150 0001E57A # /**************************************************************************
1195: 1151 0001E57A # *
1196: 1152 0001E57A # * PRINT THE DATA AND STORE RESULTS
1197: 1153 0001E57A # *
1198: 1154 0001E57A # * initial Acc = xxxxxxxx xxxxxxxx, integer stored = xxxxxxxx
1199: 1155 0001E57A # **************************************************************************/
1200: 1156 0001E57A # print_cvdl_data()
1201: 1157 0001E57A # {
1202: 1158 0001E57A 11 4b jbr L346
1203: 1159 0001E57C L347:
1204: 1160 0001E57C # writes("initial Acc = ");
1205: 1161 0001E57C .data 1
1206: 1162 00000f0c * L348:
1207: 1163 00000f0c * 696E697469616C20416363203 .ascii "initial Acc = \0"
1208: D2000
1209: 1164 00000f1b * .text
1210: 1165 0001E57C dd 8f00000f0c pushl $L348
1211: 1166 0001E582 fe 08 effffff51f callf $8,_writes
1212: 1167 0001E589 # write32h( dbl_ld_acc.m );
1213: 1168 0001E589 dd effffff519 pushl _dbl_ld_acc
1214: 1169 0001E58F fe 08 effffff512 callf $8,_write32h
1215: 1170 0001E596 # writec(' ');
1216: 1171 0001E596 dd 20 pushl $32
1217: 1172 0001E598 fe 08 effffff509 callf $8,_writec
1218: 1173 0001E59F # write32h( dbl_ld_acc.l );
1219: 1174 0001E59F dd effffff507 pushl _dbl_ld_acc+4
1220: 1175 0001E5A5 fe 08 effffff4fc callf $8,_write32h
1221: 1176 0001E5AC # writes(", int. stored = ");
1222: 1177 0001E5AC .data 1
1223: 1178 00000f1b * L349:
1224: 1179 00000f1b * 2C20202020696E742E2073746 .ascii ", int. stored = \0"
1225: F726564203D2000
1226: 1180 00000f2f * .text
1227: 1181 0001E5AC dd 8f00000f1b pushl $L349
1228: 1182 0001E5B2 fe 08 effffff4ef callf $8,_writes
1229: 1183 0001E5B9 # write32h( sgl_value_3 );
1230: 1184 0001E5B9 dd effffff4e9 pushl _sgl_value_3
1231: 1185 0001E5BF fe 08 effffff4e2 callf $8,_write32h
1232: 1186 0001E5C6 # }
1233: 1187 0001E5C6 40 ret#2
1234: 1188 0001E5C7 .set L344,0x0
1235: 1189 0001E5C7 L346:
1236: 1190 0001E5C7 11 b3 jbr L347
1237: 1191 0001E5C9 .data
1238: 1192 00000c48 * .text
1239: 1193 0001E5C9 00 .align 1
1240: 1194 0001E5CA .globl _cvdl_er_halt
1241: 1195 0001E5CA _cvdl_er_halt:
1242: 1196 0001E5CA 0000 .word L350
1243: 1197 0001E5CC #
1244: 1198 0001E5CC #
1245: 1199 0001E5CC #
1246: 1200 0001E5CC # /**************************************************************************
1247: 1201 0001E5CC # *
1248: 1202 0001E5CC # * HALT ON ERROR ROUTINE
1249: 1203 0001E5CC # *
1250: 1204 0001E5CC # **************************************************************************/
1251: 1205 0001E5CC # cvdl_er_halt( halt_code )
1252: 1206 0001E5CC # int halt_code;
1253: 1207 0001E5CC # {
1254: 1208 0001E5CC 13 011c jbr L352
1255: 1209 0001E5CF L353:
1256: 1210 0001E5CF # sgl_value_1 = dbl_ld_acc.m;
1257: 1211 0001E5CF 0d effffff4d3 effffff4ce movl _dbl_ld_acc,_sgl_value_1
1258: 1212 0001E5DA # sgl_value_2 = dbl_ld_acc.l;
1259: 1213 0001E5DA 0d effffff4cc effffff4c3 movl _dbl_ld_acc+4,_sgl_value_2
1260: 1214 0001E5E5 # sgl_value_4 = dbl_st_acc.m;
1261: 1215 0001E5E5 0d effffff4bd effffff4b8 movl _dbl_st_acc,_sgl_value_4
1262: 1216 0001E5F0 # sgl_value_5 = dbl_st_acc.l;
1263: 1217 0001E5F0 0d effffff4b6 effffff4ad movl _dbl_st_acc+4,_sgl_value_5
1264: 1218 0001E5FB # sgl_dummy1 = halt_code; /* get the error type */
1265: 1219 0001E5FB 0d ad04 effffff4a5 movl 4(fp),_sgl_dummy1
1266: 1220 0001E603 # asm("movl _test_no,r0"); /* r0 = test number */
1267: 1221 0001E603 0d effffff49f 50 movl _test_no,r0
1268: 1222 0001E60A # asm("movl _subtest,r1"); /* r1 = subtest number */
1269: 1223 0001E60A 0d effffff498 51 movl _subtest,r1
1270: 1224 0001E611 # asm("movl _sgl_dummy1,r2"); /* r2 = error code */
1271: 1225 0001E611 0d effffff491 52 movl _sgl_dummy1,r2
1272: 1226 0001E618 # asm("movl _cycle,r3"); /* r3 = cycle count */
1273: 1227 0001E618 0d effffff48a 53 movl _cycle,r3
1274: 1228 0001E61F # asm("movl _sgl_value_1,r4"); /* r4 = MS acc loaded */
1275: 1229 0001E61F 0d effffff483 54 movl _sgl_value_1,r4
1276: 1230 0001E626 # asm("movl _sgl_value_2,r5"); /* r5 = LS acc loaded */
1277: 1231 0001E626 0d effffff47c 55 movl _sgl_value_2,r5
1278: 1232 0001E62D # asm("movl _sgl_value_4,r6"); /* r6 = MS acc stored */
1279: 1233 0001E62D 0d effffff475 56 movl _sgl_value_4,r6
1280: 1234 0001E634 # asm("movl _sgl_value_5,r7"); /* r7 = LS acc stored */
1281: 1235 0001E634 0d effffff46e 57 movl _sgl_value_5,r7
1282: 1236 0001E63B # asm("movl _sgl_value_3,r8"); /* r8 = integer stored */
1283: 1237 0001E63B 0d effffff467 58 movl _sgl_value_3,r8
1284: 1238 0001E642 # if( halt_code == BAD_ACC_HLT ) {
1285: 1239 0001E642 1d ad04 01 cmpl 4(fp),$1
1286: 1240 0001E646 21 2d jneq L354
1287: 1241 0001E648 # sgl_value_1 = dbl_expected.m;
1288: 1242 0001E648 0d effffff45a effffff455 movl _dbl_expected,_sgl_value_1
1289: 1243 0001E653 # sgl_value_2 = dbl_expected.l;
1290: 1244 0001E653 0d effffff453 effffff44a movl _dbl_expected+4,_sgl_value_2
1291: 1245 0001E65E # asm("movl _sgl_value_1,r9"); /* r9 = MS expected */
1292: 1246 0001E65E 0d effffff444 59 movl _sgl_value_1,r9
1293: 1247 0001E665 # asm("movl _sgl_value_2,r10"); /* r10 = LS expected */
1294: 1248 0001E665 0d effffff43d 5a movl _sgl_value_2,r10
1295: 1249 0001E66C # asm("movl _index,r11"); /* r11 = data index */
1296: 1250 0001E66C 0d effffff436 5b movl _index,r11
1297: 1251 0001E673 # } else
1298: 1252 0001E673 11 74 jbr L355
1299: 1253 0001E675 L354:
1300: 1254 0001E675 # if( halt_code == BAD_STORE_HLT ) {
1301: 1255 0001E675 1d ad04 09 cmpl 4(fp),$9
1302: 1256 0001E679 21 10 jneq L356
1303: 1257 0001E67B # asm("movl _sgl_expected,r9"); /* r9 = int expected */
1304: 1258 0001E67B 0d effffff427 59 movl _sgl_expected,r9
1305: 1259 0001E682 # asm("movl _index,r10"); /* r10 = data index */
1306: 1260 0001E682 0d effffff420 5a movl _index,r10
1307: 1261 0001E689 # } else
1308: 1262 0001E689 11 5e jbr L357
1309: 1263 0001E68B L356:
1310: 1264 0001E68B # if( halt_code == BAD_REG_HLT ) {
1311: 1265 0001E68B 1d ad04 02 cmpl 4(fp),$2
1312: 1266 0001E68F 21 3d jneq L358
1313: 1267 0001E691 # sgl_dummy1 = load_regs[index2];
1314: 1268 0001E691 0d effffff411 50 movl _index2,r0
1315: 1269 0001E698 0d 40effffff409 movl _load_regs[r0],_sgl_dummy1
1316: effffff404
1317: 1270 0001E6A4 # sgl_dummy2 = store_regs[index2];
1318: 1271 0001E6A4 0d effffff3fe 50 movl _index2,r0
1319: 1272 0001E6AB 0d 40effffff3f6 movl _store_regs[r0],_sgl_dummy2
1320: effffff3f1
1321: 1273 0001E6B7 # asm("movl _index2,r9"); /* r9 = bad register # */
1322: 1274 0001E6B7 0d effffff3eb 59 movl _index2,r9
1323: 1275 0001E6BE # asm("movl _sgl_dummy2,r10"); /* r10 = actual value */
1324: 1276 0001E6BE 0d effffff3e4 5a movl _sgl_dummy2,r10
1325: 1277 0001E6C5 # asm("movl _sgl_dummy1,r11"); /* r11 = expected value */
1326: 1278 0001E6C5 0d effffff3dd 5b movl _sgl_dummy1,r11
1327: 1279 0001E6CC # } else
1328: 1280 0001E6CC 11 1b jbr L359
1329: 1281 0001E6CE L358:
1330: 1282 0001E6CE # if( halt_code == BAD_PSL_HLT ) {
1331: 1283 0001E6CE 1d ad04 03 cmpl 4(fp),$3
1332: 1284 0001E6D2 21 15 jneq L360
1333: 1285 0001E6D4 # asm("movl _init_psl,r9"); /* r9 = initial PSL */
1334: 1286 0001E6D4 0d effffff3ce 59 movl _init_psl,r9
1335: 1287 0001E6DB # asm("movl _psl_val,r10"); /* r10 = final PSL */
1336: 1288 0001E6DB 0d effffff3c7 5a movl _psl_val,r10
1337: 1289 0001E6E2 # asm("movl _exp_psl,r11"); /* r11 = expected PSL */
1338: 1290 0001E6E2 0d effffff3c0 5b movl _exp_psl,r11
1339: 1291 0001E6E9 # };
1340: 1292 0001E6E9 L360:
1341: 1293 0001E6E9 L359:
1342: 1294 0001E6E9 L357:
1343: 1295 0001E6E9 L355:
1344: 1296 0001E6E9 # asm("halt"); /* HALT ... */
1345: 1297 0001E6E9 00 halt
1346: 1298 0001E6EA # }
1347: 1299 0001E6EA 40 ret#2
1348: 1300 0001E6EB .set L350,0x0
1349: 1301 0001E6EB L352:
1350: 1302 0001E6EB 13 fee1 jbr L353
1351: 1303 0001E6EE .data
1352: 1303 0003C196 .data
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