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Up to [Power 6/32 Unix Tahoe 4.2BSD] / cci / d / macro4|
Return to cvdl.lst CVS log | Up to [Power 6/32 Unix Tahoe 4.2BSD] / cci / d / macro4 |
Power 6/32 Unix version 1.21
1 00000000 LL0:
2 00000000 .data
3 00000c48 * .text
4 00000000 .align 1
5 00000000 .globl _cvdl
6 00000000 _cvdl:
7 0001DAA8 0000 .word L215
8 0001DAAA #
9 0001DAAA # #include "fpp_defs.h"
10 0001DAAA #
11 0001DAAA #
12 0001DAAA # /*****************************************************************************
13 0001DAAA # *
14 0001DAAA # * CVDL - SINGLE PRECISION FLOATING POINT CONVERT LONG TO FLOAT TEST
15 0001DAAA # *
16 0001DAAA # *****************************************************************************/
17 0001DAAA # cvdl()
18 0001DAAA # {
19 0001DAAA 11 41 jbr L217
20 0001DAAC L218:
21 0001DAAC # asm(".globl _cvdl_t");
22 0001DAAC .globl _cvdl_t
23 0001DAAC # asm("_cvdl_t:"); /* entry address */
24 0001DAAC _cvdl_t:
25 0001DAAC # if( ( cycle == 1 ) && ( prt_hdrs ) ) /* print headers on 1st cycle */
26 0001DAAC 1d effffffff6 01 cmpl _cycle,$1
27 0001DAB3 21 15 jneq L219
28 0001DAB5 5d efffffffed tstl _prt_hdrs
29 0001DABB 31 0d jeql L219
30 0001DABD # writes(" CVDL");
31 0001DABD .data 1
32 00000c48 * L221:
33 00000c48 * 204356444C00 .ascii " CVDL\0"
34 00000c4e * .text
35 0001DABD dd 8f00000c48 pushl $L221
36 0001DAC3 fe 08 efffffffde callf $8,_writes
37 0001DACA # cvdl_1(); /* load through a register */
38 0001DACA L219:
39 0001DACA fe 04 ef0000001f callf $4,_cvdl_1
40 0001DAD1 # cvdl_2(); /* load through the cache */
41 0001DAD1 fe 04 ef0000033a callf $4,_cvdl_2
42 0001DAD8 # cvdl_3(); /* register stability */
43 0001DAD8 fe 04 ef00000631 callf $4,_cvdl_3
44 0001DADF # cvdl_4(); /* PSL stability test */
45 0001DADF fe 04 ef00000842 callf $4,_cvdl_4
46 0001DAE6 # asm("jmp *return"); /* return to the test monitor */
47 0001DAE6 71 ffffffffbc jmp *return
48 0001DAEC # }
49 0001DAEC 40 ret#2
50 0001DAED .set L215,0x0
51 0001DAED L217:
52 0001DAED 11 bd jbr L218
53 0001DAEF .data
54 00000c48 * .text
55 0001DAEF 00 .align 1
56 0001DAF0 .globl _cvdl_1
57 0001DAF0 _cvdl_1:
58 0001DAF0 0000 .word L226
59 0001DAF2 #
60 0001DAF2 #
61 0001DAF2 #
62 0001DAF2 # /************************************************************************
63 0001DAF2 # *
64 0001DAF2 # * SUBTEST 1
65 0001DAF2 # *
66 0001DAF2 # ************************************************************************/
67 0001DAF2 # cvdl_1()
68 0001DAF2 # {
69 0001DAF2 13 0319 jbr L228
70 0001DAF5 L229:
71 0001DAF5 # force_loop = FALSE;
72 0001DAF5 4d efffffffad clrl _force_loop
73 0001DAFB # subtest = 1;
74 0001DAFB 0d 01 efffffffa6 movl $1,_subtest
75 0001DB02 # index = 0;
76 0001DB02 4d efffffffa0 clrl _index
77 0001DB08 # do
78 0001DB08 L232:
79 0001DB08 # {
80 0001DB08 # dbl_ld_acc = cvdl_1_data[index].ld; /* get the operand */
81 0001DB08 5c 0c efffffff99 50 mull3 $12,_index,r0
82 0001DB10 0c 8f00000000 50 addl2 $_cvdl_1_data,r0
83 0001DB17 0d a004 efffffff8d movl 4(r0),_dbl_ld_acc+4
84 0001DB1F 0d 60 efffffff82 movl (r0),_dbl_ld_acc
85 0001DB26 # sgl_expected = cvdl_1_data[index].exp; /* get expected result */
86 0001DB26 5c 0c efffffff7b 50 mull3 $12,_index,r0
87 0001DB2E 0d e000000008 efffffff6f movl _cvdl_1_data+8(r0),_sgl_expected
88 0001DB39 # sgl_value_1 = dbl_ld_acc.m; /* get an initial value */
89 0001DB39 0d efffffff69 efffffff64 movl _dbl_ld_acc,_sgl_value_1
90 0001DB44 # sgl_value_2 = dbl_ld_acc.l; /* for the accumulator */
91 0001DB44 0d efffffff62 efffffff59 movl _dbl_ld_acc+4,_sgl_value_2
92 0001DB4F # /*
93 0001DB4F # * If LOOP ON ERROR is set, this is the loop for this subtest.
94 0001DB4F # * The force loop flag is set after the first error.
95 0001DB4F # */
96 0001DB4F # asm("_cvdl_1_lp1:");
97 0001DB4F _cvdl_1_lp1:
98 0001DB4F # asm("movl _sgl_value_1,r4"); /* get the value to convert */
99 0001DB4F 0d efffffff53 54 movl _sgl_value_1,r4
100 0001DB56 # asm("movl _sgl_value_2,r5");
101 0001DB56 0d efffffff4c 55 movl _sgl_value_2,r5
102 0001DB5D # asm("ldd r4"); /* load the value to convert*/
103 0001DB5D 07 54 ldd r4
104 0001DB5F # asm("cvdl r8"); /* convert the value */
105 0001DB5F 87 58 cvdl r8
106 0001DB61 # asm("nop");
107 0001DB61 10 nop
108 0001DB62 # asm("std _dbl_st_acc"); /* save the accumulator */
109 0001DB62 27 efffffff40 std _dbl_st_acc
110 0001DB68 # if( force_loop )
111 0001DB68 5d efffffff3a tstl _force_loop
112 0001DB6E 31 02 jeql L233
113 0001DB70 # asm("brb _cvdl_1_lp1");; /* loop on the error */
114 0001DB70 11 dd brb _cvdl_1_lp1
115 0001DB72 L233:
116 0001DB72 # /*
117 0001DB72 # * end error loop - test the results
118 0001DB72 # */
119 0001DB72 # asm("movl r8,_sgl_value_3"); /* move result to cache */
120 0001DB72 0d 58 efffffff2f movl r8,_sgl_value_3
121 0001DB79 # if( sgl_value_3 != sgl_expected ) {/* COMPARE the values */
122 0001DB79 1d efffffff29 efffffff24 cmpl _sgl_value_3,_sgl_expected
123 0001DB84 21 03 13 00ff jeql L234
124 0001DB89 # errcnt++; /* bump the error count */
125 0001DB89 6d efffffff19 incl _errcnt
126 0001DB8F # if( prt_error ) {
127 0001DB8F 5d efffffff13 tstl _prt_error
128 0001DB95 21 03 13 00cb jeql L235
129 0001DB9A # writes(" \n"); /* start a new print line */
130 0001DB9A .data 1
131 00000c4e * L236:
132 00000c4e * 200A00 .ascii " \12\0"
133 00000c51 * .text
134 0001DB9A dd 8f00000c4e pushl $L236
135 0001DBA0 fe 08 efffffff01 callf $8,_writes
136 0001DBA7 # writes("cycle: ");
137 0001DBA7 .data 1
138 00000c51 * L237:
139 00000c51 * 6379636C653A2000 .ascii "cycle: \0"
140 00000c59 * .text
141 0001DBA7 dd 8f00000c51 pushl $L237
142 0001DBAD fe 08 effffffef4 callf $8,_writes
143 0001DBB4 # writed( cycle );
144 0001DBB4 dd effffffeee pushl _cycle
145 0001DBBA fe 08 effffffee7 callf $8,_writed
146 0001DBC1 # writes(" CVDL test ");
147 0001DBC1 .data 1
148 00000c59 * L239:
149 00000c59 * 20204356444C2074657374200 .ascii " CVDL test \0"
0
150 00000c66 * .text
151 0001DBC1 dd 8f00000c59 pushl $L239
152 0001DBC7 fe 08 effffffeda callf $8,_writes
153 0001DBCE # writed( test_no );
154 0001DBCE dd effffffed4 pushl _test_no
155 0001DBD4 fe 08 effffffecd callf $8,_writed
156 0001DBDB # writes(", subtest 1 (Reg. Data) - WRONG DATA STORED\n");
157 0001DBDB .data 1
158 00000c66 * L240:
159 00000c66 * 2C20737562746573742031202 .ascii ", subtest 1 (Reg. Data) - WRONG DATA STORED\12\0"
85265672E204461746129202D
2057524F4E472044415441205
3544F5245440A00
160 00000c93 * .text
161 0001DBDB dd 8f00000c66 pushl $L240
162 0001DBE1 fe 08 effffffec0 callf $8,_writes
163 0001DBE8 # print_cvdl_data();
164 0001DBE8 fe 04 ef00000989 callf $4,_print_cvdl_data
165 0001DBEF # writes(", index = ");
166 0001DBEF .data 1
167 00000c93 * L242:
168 00000c93 * 2C202020696E646578203D200 .ascii ", index = \0"
0
169 00000ca0 * .text
170 0001DBEF dd 8f00000c93 pushl $L242
171 0001DBF5 fe 08 effffffeac callf $8,_writes
172 0001DBFC # writed( index );
173 0001DBFC dd effffffea6 pushl _index
174 0001DC02 fe 08 effffffe9f callf $8,_writed
175 0001DC09 # writec('\n');
176 0001DC09 dd 0a pushl $10
177 0001DC0B fe 08 effffffe96 callf $8,_writec
178 0001DC12 # writes(" final Acc = ");
179 0001DC12 .data 1
180 00000ca0 * L244:
181 00000ca0 * 202066696E616C20416363203 .ascii " final Acc = \0"
D2000
182 00000caf * .text
183 0001DC12 dd 8f00000ca0 pushl $L244
184 0001DC18 fe 08 effffffe89 callf $8,_writes
185 0001DC1F # write32h( dbl_st_acc.m );
186 0001DC1F dd effffffe83 pushl _dbl_st_acc
187 0001DC25 fe 08 effffffe7c callf $8,_write32h
188 0001DC2C # writec(' ');
189 0001DC2C dd 20 pushl $32
190 0001DC2E fe 08 effffffe73 callf $8,_writec
191 0001DC35 # write32h( dbl_st_acc.l );
192 0001DC35 dd effffffe71 pushl _dbl_st_acc+4
193 0001DC3B fe 08 effffffe66 callf $8,_write32h
194 0001DC42 # writes(", int. expected = ");
195 0001DC42 .data 1
196 00000caf * L246:
197 00000caf * 2C2020696E742E20657870656 .ascii ", int. expected = \0"
3746564203D2000
198 00000cc3 * .text
199 0001DC42 dd 8f00000caf pushl $L246
200 0001DC48 fe 08 effffffe59 callf $8,_writes
201 0001DC4F # write32h( sgl_expected );
202 0001DC4F dd effffffe53 pushl _sgl_expected
203 0001DC55 fe 08 effffffe4c callf $8,_write32h
204 0001DC5C # writec('\n');
205 0001DC5C dd 0a pushl $10
206 0001DC5E fe 08 effffffe43 callf $8,_writec
207 0001DC65 # }
208 0001DC65 # if( halt_flg )
209 0001DC65 L235:
210 0001DC65 5d effffffe3d tstl _halt_flg
211 0001DC6B 31 09 jeql L247
212 0001DC6D # cvdl_er_halt( BAD_STORE_HLT ); /* halt on the error */
213 0001DC6D dd 09 pushl $9
214 0001DC6F fe 08 ef00000954 callf $8,_cvdl_er_halt
215 0001DC76 # if( loop_on_err ) {
216 0001DC76 L247:
217 0001DC76 5d effffffe2c tstl _loop_on_err
218 0001DC7C 31 0a jeql L249
219 0001DC7E # force_loop = TRUE; /* set the force loop flag */
220 0001DC7E 0d 01 effffffe23 movl $1,_force_loop
221 0001DC85 # asm("brw _cvdl_1_lp1");; /* and loop on the error */
222 0001DC85 13 fec7 brw _cvdl_1_lp1
223 0001DC88 # } /* end of loop on error */
224 0001DC88 # } /* end of convert compare error */
225 0001DC88 L249:
226 0001DC88 # if( dbl_ld_acc.m & 0x7f800000 ) {
227 0001DC88 L234:
228 0001DC88 3d 8f7f800000 effffffe15 bitl $2139095040,_dbl_ld_acc
229 0001DC93 31 18 jeql L250
230 0001DC95 # dbl_expected.m = dbl_ld_acc.m; /* the Acc should */
231 0001DC95 0d effffffe0d effffffe08 movl _dbl_ld_acc,_dbl_expected
232 0001DCA0 # dbl_expected.l = dbl_ld_acc.l; /* not change */
233 0001DCA0 0d effffffe06 effffffe01 movl _dbl_ld_acc+4,_dbl_expected+4
234 0001DCAB # } else {
235 0001DCAB 11 0c jbr L251
236 0001DCAD L250:
237 0001DCAD # dbl_expected.m = 0; /* expect a '0' final Acc */
238 0001DCAD 4d effffffdf5 clrl _dbl_expected
239 0001DCB3 # dbl_expected.l = 0;
240 0001DCB3 4d effffffdf3 clrl _dbl_expected+4
241 0001DCB9 # }
242 0001DCB9 L251:
243 0001DCB9 # if( ( dbl_st_acc.m != dbl_expected.m ) ||
244 0001DCB9 # ( dbl_st_acc.l != dbl_expected.l ) ) { /* COMPARE values */
245 0001DCB9 1d effffffde9 effffffde4 cmpl _dbl_st_acc,_dbl_expected
246 0001DCC4 21 10 jneq L9999
247 0001DCC6 1d effffffde0 effffffddb cmpl _dbl_st_acc+4,_dbl_expected+4
248 0001DCD1 21 03 13 011e jeql L252
249 0001DCD6 L9999:
250 0001DCD6 # errcnt++; /* bump the error count */
251 0001DCD6 6d effffffdcc incl _errcnt
252 0001DCDC # if( prt_error ) {
253 0001DCDC 5d effffffdc6 tstl _prt_error
254 0001DCE2 21 03 13 00ea jeql L253
255 0001DCE7 # writes(" \n"); /* start a new print line */
256 0001DCE7 .data 1
257 00000cc3 * L254:
258 00000cc3 * 200A00 .ascii " \12\0"
259 00000cc6 * .text
260 0001DCE7 dd 8f00000cc3 pushl $L254
261 0001DCED fe 08 effffffdb4 callf $8,_writes
262 0001DCF4 # writes("cycle: ");
263 0001DCF4 .data 1
264 00000cc6 * L255:
265 00000cc6 * 6379636C653A2000 .ascii "cycle: \0"
266 00000cce * .text
267 0001DCF4 dd 8f00000cc6 pushl $L255
268 0001DCFA fe 08 effffffda7 callf $8,_writes
269 0001DD01 # writed( cycle );
270 0001DD01 dd effffffda1 pushl _cycle
271 0001DD07 fe 08 effffffd9a callf $8,_writed
272 0001DD0E # writes(" CVDL test ");
273 0001DD0E .data 1
274 00000cce * L256:
275 00000cce * 20204356444C2074657374200 .ascii " CVDL test \0"
0
276 00000cdb * .text
277 0001DD0E dd 8f00000cce pushl $L256
278 0001DD14 fe 08 effffffd8d callf $8,_writes
279 0001DD1B # writed( test_no );
280 0001DD1B dd effffffd87 pushl _test_no
281 0001DD21 fe 08 effffffd80 callf $8,_writed
282 0001DD28 # writes(", subtest 1 (Reg. Data) - BAD FINAL ACC\n");
283 0001DD28 .data 1
284 00000cdb * L257:
285 00000cdb * 2C20737562746573742031202 .ascii ", subtest 1 (Reg. Data) - BAD FINAL ACC\12\0"
85265672E204461746129202D
204241442046494E414C20414
3430A00
286 00000d04 * .text
287 0001DD28 dd 8f00000cdb pushl $L257
288 0001DD2E fe 08 effffffd73 callf $8,_writes
289 0001DD35 # print_cvdl_data();
290 0001DD35 fe 04 ef0000083c callf $4,_print_cvdl_data
291 0001DD3C # writes(", index = ");
292 0001DD3C .data 1
293 00000d04 * L258:
294 00000d04 * 2C202020696E646578203D200 .ascii ", index = \0"
0
295 00000d11 * .text
296 0001DD3C dd 8f00000d04 pushl $L258
297 0001DD42 fe 08 effffffd5f callf $8,_writes
298 0001DD49 # writed( index );
299 0001DD49 dd effffffd59 pushl _index
300 0001DD4F fe 08 effffffd52 callf $8,_writed
301 0001DD56 # writec('\n');
302 0001DD56 dd 0a pushl $10
303 0001DD58 fe 08 effffffd49 callf $8,_writec
304 0001DD5F # writes(" final Acc = ");
305 0001DD5F .data 1
306 00000d11 * L259:
307 00000d11 * 202066696E616C20416363203 .ascii " final Acc = \0"
D2000
308 00000d20 * .text
309 0001DD5F dd 8f00000d11 pushl $L259
310 0001DD65 fe 08 effffffd3c callf $8,_writes
311 0001DD6C # write32h( dbl_st_acc.m );
312 0001DD6C dd effffffd36 pushl _dbl_st_acc
313 0001DD72 fe 08 effffffd2f callf $8,_write32h
314 0001DD79 # writec(' ');
315 0001DD79 dd 20 pushl $32
316 0001DD7B fe 08 effffffd26 callf $8,_writec
317 0001DD82 # write32h( dbl_st_acc.l );
318 0001DD82 dd effffffd24 pushl _dbl_st_acc+4
319 0001DD88 fe 08 effffffd19 callf $8,_write32h
320 0001DD8F # writec('\n');
321 0001DD8F dd 0a pushl $10
322 0001DD91 fe 08 effffffd10 callf $8,_writec
323 0001DD98 # writes(" expected = ");
324 0001DD98 .data 1
325 00000d20 * L260:
326 00000d20 * 2020206578706563746564203 .ascii " expected = \0"
D2000
327 00000d2f * .text
328 0001DD98 dd 8f00000d20 pushl $L260
329 0001DD9E fe 08 effffffd03 callf $8,_writes
330 0001DDA5 # write32h( dbl_expected.m );
331 0001DDA5 dd effffffcfd pushl _dbl_expected
332 0001DDAB fe 08 effffffcf6 callf $8,_write32h
333 0001DDB2 # writec(' ');
334 0001DDB2 dd 20 pushl $32
335 0001DDB4 fe 08 effffffced callf $8,_writec
336 0001DDBB # write32h( dbl_expected.l );
337 0001DDBB dd effffffceb pushl _dbl_expected+4
338 0001DDC1 fe 08 effffffce0 callf $8,_write32h
339 0001DDC8 # writec('\n');
340 0001DDC8 dd 0a pushl $10
341 0001DDCA fe 08 effffffcd7 callf $8,_writec
342 0001DDD1 # }
343 0001DDD1 # if( halt_flg )
344 0001DDD1 L253:
345 0001DDD1 5d effffffcd1 tstl _halt_flg
346 0001DDD7 31 09 jeql L261
347 0001DDD9 # cvdl_er_halt( BAD_ACC_HLT ); /* halt on the error */
348 0001DDD9 dd 01 pushl $1
349 0001DDDB fe 08 ef000007e8 callf $8,_cvdl_er_halt
350 0001DDE2 # if( loop_on_err ) {
351 0001DDE2 L261:
352 0001DDE2 5d effffffcc0 tstl _loop_on_err
353 0001DDE8 31 0a jeql L262
354 0001DDEA # force_loop = TRUE; /* set the force loop flag */
355 0001DDEA 0d 01 effffffcb7 movl $1,_force_loop
356 0001DDF1 # asm("brw _cvdl_1_lp1");; /* and loop on the error */
357 0001DDF1 13 fd5b brw _cvdl_1_lp1
358 0001DDF4 # } /* end of loop on error */
359 0001DDF4 # } /* end of ACC compare error */
360 0001DDF4 L262:
361 0001DDF4 # } while( index++ < max_cvdl_1_index ); /* end of WHILE loop */
362 0001DDF4 L252:
363 0001DDF4 L231:
364 0001DDF4 0d effffffcae 50 movl _index,r0
365 0001DDFB 6d effffffca7 incl _index
366 0001DE01 1d 50 effffffca0 cmpl r0,_max_cvdl_1_index
367 0001DE08 81 03 13 fcfb jlss L232
368 0001DE0D L230:
369 0001DE0D # } /* end of subtest 1 */
370 0001DE0D 40 ret#2
371 0001DE0E .set L226,0x0
372 0001DE0E L228:
373 0001DE0E 13 fce4 jbr L229
374 0001DE11 .data
375 00000c48 * .text
376 0001DE11 00 .align 1
377 0001DE12 .globl _cvdl_2
378 0001DE12 _cvdl_2:
379 0001DE12 0000 .word L263
380 0001DE14 #
381 0001DE14 #
382 0001DE14 #
383 0001DE14 # /************************************************************************
384 0001DE14 # *
385 0001DE14 # * SUBTEST 2 - convert through memory
386 0001DE14 # *
387 0001DE14 # ************************************************************************/
388 0001DE14 # cvdl_2()
389 0001DE14 # {
390 0001DE14 13 02f6 jbr L265
391 0001DE17 L266:
392 0001DE17 # force_loop = FALSE;
393 0001DE17 4d effffffc8b clrl _force_loop
394 0001DE1D # subtest = 2;
395 0001DE1D 0d 02 effffffc84 movl $2,_subtest
396 0001DE24 # index = 0;
397 0001DE24 4d effffffc7e clrl _index
398 0001DE2A # do
399 0001DE2A L269:
400 0001DE2A # {
401 0001DE2A # dbl_ld_acc = cvdl_1_data[index].ld; /* get the operand */
402 0001DE2A 5c 0c effffffc77 50 mull3 $12,_index,r0
403 0001DE32 0c 8f00000000 50 addl2 $_cvdl_1_data,r0
404 0001DE39 0d a004 effffffc6b movl 4(r0),_dbl_ld_acc+4
405 0001DE41 0d 60 effffffc60 movl (r0),_dbl_ld_acc
406 0001DE48 # sgl_expected = cvdl_1_data[index].exp; /* get expected result */
407 0001DE48 5c 0c effffffc59 50 mull3 $12,_index,r0
408 0001DE50 0d e000000008 effffffc4d movl _cvdl_1_data+8(r0),_sgl_expected
409 0001DE5B # /*
410 0001DE5B # * If LOOP ON ERROR is set, this is the loop for this subtest.
411 0001DE5B # * The force loop flag is set after the first error.
412 0001DE5B # */
413 0001DE5B # asm("_cvdl_2_lp1:");
414 0001DE5B _cvdl_2_lp1:
415 0001DE5B # asm("ldd _dbl_ld_acc"); /* load the background */
416 0001DE5B 07 effffffc47 ldd _dbl_ld_acc
417 0001DE61 # asm("cvdl _sgl_value_3"); /* convert the value */
418 0001DE61 87 effffffc41 cvdl _sgl_value_3
419 0001DE67 # asm("nop");
420 0001DE67 10 nop
421 0001DE68 # asm("std _dbl_st_acc"); /* save the accumulator */
422 0001DE68 27 effffffc3a std _dbl_st_acc
423 0001DE6E # if( force_loop )
424 0001DE6E 5d effffffc34 tstl _force_loop
425 0001DE74 31 02 jeql L270
426 0001DE76 # asm("brb _cvdl_2_lp1");; /* loop on the error */
427 0001DE76 11 e3 brb _cvdl_2_lp1
428 0001DE78 L270:
429 0001DE78 # /*
430 0001DE78 # * end error loop - test the results
431 0001DE78 # */
432 0001DE78 # if( sgl_value_3 != sgl_expected ) {/* COMPARE the values */
433 0001DE78 1d effffffc2a effffffc25 cmpl _sgl_value_3,_sgl_expected
434 0001DE83 21 03 13 00ff jeql L271
435 0001DE88 # errcnt++; /* bump the error count */
436 0001DE88 6d effffffc1a incl _errcnt
437 0001DE8E # if( prt_error ) {
438 0001DE8E 5d effffffc14 tstl _prt_error
439 0001DE94 21 03 13 00cb jeql L272
440 0001DE99 # writes(" \n"); /* start a new print line */
441 0001DE99 .data 1
442 00000d2f * L273:
443 00000d2f * 200A00 .ascii " \12\0"
444 00000d32 * .text
445 0001DE99 dd 8f00000d2f pushl $L273
446 0001DE9F fe 08 effffffc02 callf $8,_writes
447 0001DEA6 # writes("cycle: ");
448 0001DEA6 .data 1
449 00000d32 * L274:
450 00000d32 * 6379636C653A2000 .ascii "cycle: \0"
451 00000d3a * .text
452 0001DEA6 dd 8f00000d32 pushl $L274
453 0001DEAC fe 08 effffffbf5 callf $8,_writes
454 0001DEB3 # writed( cycle );
455 0001DEB3 dd effffffbef pushl _cycle
456 0001DEB9 fe 08 effffffbe8 callf $8,_writed
457 0001DEC0 # writes(" CVDL test ");
458 0001DEC0 .data 1
459 00000d3a * L275:
460 00000d3a * 20204356444C2074657374200 .ascii " CVDL test \0"
0
461 00000d47 * .text
462 0001DEC0 dd 8f00000d3a pushl $L275
463 0001DEC6 fe 08 effffffbdb callf $8,_writes
464 0001DECD # writed( test_no );
465 0001DECD dd effffffbd5 pushl _test_no
466 0001DED3 fe 08 effffffbce callf $8,_writed
467 0001DEDA # writes(", subtest 2 (Cache Data) - WRONG DATA STORED\n");
468 0001DEDA .data 1
469 00000d47 * L276:
470 00000d47 * 2C20737562746573742032202 .ascii ", subtest 2 (Cache Data) - WRONG DATA STORED\12\0"
8436163686520446174612920
2D2057524F4E4720444154412
053544F5245440A00
471 00000d75 * .text
472 0001DEDA dd 8f00000d47 pushl $L276
473 0001DEE0 fe 08 effffffbc1 callf $8,_writes
474 0001DEE7 # print_cvdl_data();
475 0001DEE7 fe 04 ef0000068a callf $4,_print_cvdl_data
476 0001DEEE # writes(", index = ");
477 0001DEEE .data 1
478 00000d75 * L277:
479 00000d75 * 2C202020696E646578203D200 .ascii ", index = \0"
0
480 00000d82 * .text
481 0001DEEE dd 8f00000d75 pushl $L277
482 0001DEF4 fe 08 effffffbad callf $8,_writes
483 0001DEFB # writed( index );
484 0001DEFB dd effffffba7 pushl _index
485 0001DF01 fe 08 effffffba0 callf $8,_writed
486 0001DF08 # writec('\n');
487 0001DF08 dd 0a pushl $10
488 0001DF0A fe 08 effffffb97 callf $8,_writec
489 0001DF11 # writes(" final Acc = ");
490 0001DF11 .data 1
491 00000d82 * L278:
492 00000d82 * 202066696E616C20416363203 .ascii " final Acc = \0"
D2000
493 00000d91 * .text
494 0001DF11 dd 8f00000d82 pushl $L278
495 0001DF17 fe 08 effffffb8a callf $8,_writes
496 0001DF1E # write32h( dbl_st_acc.m );
497 0001DF1E dd effffffb84 pushl _dbl_st_acc
498 0001DF24 fe 08 effffffb7d callf $8,_write32h
499 0001DF2B # writec(' ');
500 0001DF2B dd 20 pushl $32
501 0001DF2D fe 08 effffffb74 callf $8,_writec
502 0001DF34 # write32h( dbl_st_acc.l );
503 0001DF34 dd effffffb72 pushl _dbl_st_acc+4
504 0001DF3A fe 08 effffffb67 callf $8,_write32h
505 0001DF41 # writes(", int. expected = ");
506 0001DF41 .data 1
507 00000d91 * L279:
508 00000d91 * 2C2020696E742E20657870656 .ascii ", int. expected = \0"
3746564203D2000
509 00000da5 * .text
510 0001DF41 dd 8f00000d91 pushl $L279
511 0001DF47 fe 08 effffffb5a callf $8,_writes
512 0001DF4E # write32h( sgl_expected );
513 0001DF4E dd effffffb54 pushl _sgl_expected
514 0001DF54 fe 08 effffffb4d callf $8,_write32h
515 0001DF5B # writec('\n');
516 0001DF5B dd 0a pushl $10
517 0001DF5D fe 08 effffffb44 callf $8,_writec
518 0001DF64 # }
519 0001DF64 # if( halt_flg )
520 0001DF64 L272:
521 0001DF64 5d effffffb3e tstl _halt_flg
522 0001DF6A 31 09 jeql L280
523 0001DF6C # cvdl_er_halt( BAD_STORE_HLT ); /* halt on the error */
524 0001DF6C dd 09 pushl $9
525 0001DF6E fe 08 ef00000655 callf $8,_cvdl_er_halt
526 0001DF75 # if( loop_on_err ) {
527 0001DF75 L280:
528 0001DF75 5d effffffb2d tstl _loop_on_err
529 0001DF7B 31 0a jeql L281
530 0001DF7D # force_loop = TRUE; /* set the force loop flag */
531 0001DF7D 0d 01 effffffb24 movl $1,_force_loop
532 0001DF84 # asm("brw _cvdl_2_lp1");; /* and loop on the error */
533 0001DF84 13 fed4 brw _cvdl_2_lp1
534 0001DF87 # } /* end of loop on error */
535 0001DF87 # } /* end of convert compare error */
536 0001DF87 L281:
537 0001DF87 # if( dbl_ld_acc.m & 0x7f800000 ) {
538 0001DF87 L271:
539 0001DF87 3d 8f7f800000 effffffb16 bitl $2139095040,_dbl_ld_acc
540 0001DF92 31 18 jeql L282
541 0001DF94 # dbl_expected.m = dbl_ld_acc.m; /* the Acc should */
542 0001DF94 0d effffffb0e effffffb09 movl _dbl_ld_acc,_dbl_expected
543 0001DF9F # dbl_expected.l = dbl_ld_acc.l; /* not change */
544 0001DF9F 0d effffffb07 effffffb02 movl _dbl_ld_acc+4,_dbl_expected+4
545 0001DFAA # } else {
546 0001DFAA 11 0c jbr L283
547 0001DFAC L282:
548 0001DFAC # dbl_expected.m = 0; /* expect a '0' final Acc */
549 0001DFAC 4d effffffaf6 clrl _dbl_expected
550 0001DFB2 # dbl_expected.l = 0;
551 0001DFB2 4d effffffaf4 clrl _dbl_expected+4
552 0001DFB8 # }
553 0001DFB8 L283:
554 0001DFB8 # if( ( dbl_st_acc.m != dbl_expected.m ) ||
555 0001DFB8 # ( dbl_st_acc.l != dbl_expected.l ) ) { /* COMPARE values */
556 0001DFB8 1d effffffaea effffffae5 cmpl _dbl_st_acc,_dbl_expected
557 0001DFC3 21 10 jneq L9998
558 0001DFC5 1d effffffae1 effffffadc cmpl _dbl_st_acc+4,_dbl_expected+4
559 0001DFD0 21 03 13 011e jeql L284
560 0001DFD5 L9998:
561 0001DFD5 # errcnt++; /* bump the error count */
562 0001DFD5 6d effffffacd incl _errcnt
563 0001DFDB # if( prt_error ) {
564 0001DFDB 5d effffffac7 tstl _prt_error
565 0001DFE1 21 03 13 00ea jeql L285
566 0001DFE6 # writes(" \n"); /* start a new print line */
567 0001DFE6 .data 1
568 00000da5 * L286:
569 00000da5 * 200A00 .ascii " \12\0"
570 00000da8 * .text
571 0001DFE6 dd 8f00000da5 pushl $L286
572 0001DFEC fe 08 effffffab5 callf $8,_writes
573 0001DFF3 # writes("cycle: ");
574 0001DFF3 .data 1
575 00000da8 * L287:
576 00000da8 * 6379636C653A2000 .ascii "cycle: \0"
577 00000db0 * .text
578 0001DFF3 dd 8f00000da8 pushl $L287
579 0001DFF9 fe 08 effffffaa8 callf $8,_writes
580 0001E000 # writed( cycle );
581 0001E000 dd effffffaa2 pushl _cycle
582 0001E006 fe 08 effffffa9b callf $8,_writed
583 0001E00D # writes(" CVDL test ");
584 0001E00D .data 1
585 00000db0 * L288:
586 00000db0 * 20204356444C2074657374200 .ascii " CVDL test \0"
0
587 00000dbd * .text
588 0001E00D dd 8f00000db0 pushl $L288
589 0001E013 fe 08 effffffa8e callf $8,_writes
590 0001E01A # writed( test_no );
591 0001E01A dd effffffa88 pushl _test_no
592 0001E020 fe 08 effffffa81 callf $8,_writed
593 0001E027 # writes(", subtest 2 (Cache Data) - BAD FINAL ACC\n");
594 0001E027 .data 1
595 00000dbd * L289:
596 00000dbd * 2C20737562746573742032202 .ascii ", subtest 2 (Cache Data) - BAD FINAL ACC\12\0"
8436163686520446174612920
2D204241442046494E414C204
143430A00
597 00000de7 * .text
598 0001E027 dd 8f00000dbd pushl $L289
599 0001E02D fe 08 effffffa74 callf $8,_writes
600 0001E034 # print_cvdl_data();
601 0001E034 fe 04 ef0000053d callf $4,_print_cvdl_data
602 0001E03B # writes(", index = ");
603 0001E03B .data 1
604 00000de7 * L290:
605 00000de7 * 2C202020696E646578203D200 .ascii ", index = \0"
0
606 00000df4 * .text
607 0001E03B dd 8f00000de7 pushl $L290
608 0001E041 fe 08 effffffa60 callf $8,_writes
609 0001E048 # writed( index );
610 0001E048 dd effffffa5a pushl _index
611 0001E04E fe 08 effffffa53 callf $8,_writed
612 0001E055 # writec('\n');
613 0001E055 dd 0a pushl $10
614 0001E057 fe 08 effffffa4a callf $8,_writec
615 0001E05E # writes(" final Acc = ");
616 0001E05E .data 1
617 00000df4 * L291:
618 00000df4 * 202066696E616C20416363203 .ascii " final Acc = \0"
D2000
619 00000e03 * .text
620 0001E05E dd 8f00000df4 pushl $L291
621 0001E064 fe 08 effffffa3d callf $8,_writes
622 0001E06B # write32h( dbl_st_acc.m );
623 0001E06B dd effffffa37 pushl _dbl_st_acc
624 0001E071 fe 08 effffffa30 callf $8,_write32h
625 0001E078 # writec(' ');
626 0001E078 dd 20 pushl $32
627 0001E07A fe 08 effffffa27 callf $8,_writec
628 0001E081 # write32h( dbl_st_acc.l );
629 0001E081 dd effffffa25 pushl _dbl_st_acc+4
630 0001E087 fe 08 effffffa1a callf $8,_write32h
631 0001E08E # writec('\n');
632 0001E08E dd 0a pushl $10
633 0001E090 fe 08 effffffa11 callf $8,_writec
634 0001E097 # writes(" expected = ");
635 0001E097 .data 1
636 00000e03 * L292:
637 00000e03 * 2020206578706563746564203 .ascii " expected = \0"
D2000
638 00000e12 * .text
639 0001E097 dd 8f00000e03 pushl $L292
640 0001E09D fe 08 effffffa04 callf $8,_writes
641 0001E0A4 # write32h( dbl_expected.m );
642 0001E0A4 dd effffff9fe pushl _dbl_expected
643 0001E0AA fe 08 effffff9f7 callf $8,_write32h
644 0001E0B1 # writec(' ');
645 0001E0B1 dd 20 pushl $32
646 0001E0B3 fe 08 effffff9ee callf $8,_writec
647 0001E0BA # write32h( dbl_expected.l );
648 0001E0BA dd effffff9ec pushl _dbl_expected+4
649 0001E0C0 fe 08 effffff9e1 callf $8,_write32h
650 0001E0C7 # writec('\n');
651 0001E0C7 dd 0a pushl $10
652 0001E0C9 fe 08 effffff9d8 callf $8,_writec
653 0001E0D0 # }
654 0001E0D0 # if( halt_flg )
655 0001E0D0 L285:
656 0001E0D0 5d effffff9d2 tstl _halt_flg
657 0001E0D6 31 09 jeql L293
658 0001E0D8 # cvdl_er_halt( BAD_ACC_HLT ); /* halt on the error */
659 0001E0D8 dd 01 pushl $1
660 0001E0DA fe 08 ef000004e9 callf $8,_cvdl_er_halt
661 0001E0E1 # if( loop_on_err ) {
662 0001E0E1 L293:
663 0001E0E1 5d effffff9c1 tstl _loop_on_err
664 0001E0E7 31 0a jeql L294
665 0001E0E9 # force_loop = TRUE; /* set the force loop flag */
666 0001E0E9 0d 01 effffff9b8 movl $1,_force_loop
667 0001E0F0 # asm("brw _cvdl_1_lp1");; /* and loop on the error */
668 0001E0F0 13 fa5c brw _cvdl_1_lp1
669 0001E0F3 # } /* end of loop on error */
670 0001E0F3 # } /* end of ACC compare error */
671 0001E0F3 L294:
672 0001E0F3 # } while( index++ < max_cvdl_1_index ); /* end of WHILE loop */
673 0001E0F3 L284:
674 0001E0F3 L268:
675 0001E0F3 0d effffff9af 50 movl _index,r0
676 0001E0FA 6d effffff9a8 incl _index
677 0001E100 1d 50 effffff9a1 cmpl r0,_max_cvdl_1_index
678 0001E107 81 03 13 fd1e jlss L269
679 0001E10C L267:
680 0001E10C # } /* end of subtest 2 */
681 0001E10C 40 ret#2
682 0001E10D .set L263,0x0
683 0001E10D L265:
684 0001E10D 13 fd07 jbr L266
685 0001E110 .data
686 00000c48 * .text
687 0001E110 .align 1
688 0001E110 .globl _cvdl_3
689 0001E110 _cvdl_3:
690 0001E110 0000 .word L295
691 0001E112 #
692 0001E112 #
693 0001E112 #
694 0001E112 # /************************************************************************
695 0001E112 # *
696 0001E112 # * SUBTEST 3 - Check for register corruption
697 0001E112 # *
698 0001E112 # ************************************************************************/
699 0001E112 # cvdl_3()
700 0001E112 # {
701 0001E112 13 0210 jbr L297
702 0001E115 L298:
703 0001E115 # force_loop = FALSE; /* clear force_loop flg */
704 0001E115 4d effffff98d clrl _force_loop
705 0001E11B # subtest = 3;
706 0001E11B 0d 03 effffff986 movl $3,_subtest
707 0001E122 # fill_reg_buf( load_regs ); /* get patterns for regs */
708 0001E122 dd 8f00000000 pushl $_load_regs
709 0001E128 fe 08 effffff979 callf $8,_fill_reg_buf
710 0001E12F # index = 0;
711 0001E12F 4d effffff973 clrl _index
712 0001E135 # dbl_ld_acc = cvdl_1_data[index].ld; /* get the operand */
713 0001E135 5c 0c effffff96c 50 mull3 $12,_index,r0
714 0001E13D 0c 8f00000000 50 addl2 $_cvdl_1_data,r0
715 0001E144 0d a004 effffff960 movl 4(r0),_dbl_ld_acc+4
716 0001E14C 0d 60 effffff955 movl (r0),_dbl_ld_acc
717 0001E153 # sgl_expected = cvdl_1_data[index].exp; /* get expected result */
718 0001E153 5c 0c effffff94e 50 mull3 $12,_index,r0
719 0001E15B 0d e000000008 effffff942 movl _cvdl_1_data+8(r0),_sgl_expected
720 0001E166 # /*
721 0001E166 # * If LOOP ON ERROR is set, this is the loop for this subtest.
722 0001E166 # * The force loop flag is set after the first error.
723 0001E166 # */
724 0001E166 # asm("_cvdl_3_lp1:");
725 0001E166 _cvdl_3_lp1:
726 0001E166 # asm("ldd _dbl_ld_acc"); /* load base value */
727 0001E166 07 effffff93c ldd _dbl_ld_acc
728 0001E16C # asm("loadr $0x1fff,_load_regs"); /* load regs 0 - 12 */
729 0001E16C ab 891fff effffff933 loadr $0x1fff,_load_regs
730 0001E175 # asm("nop");
731 0001E175 10 nop
732 0001E176 # asm("cvdl _sgl_value_3"); /* convert the value */
733 0001E176 87 effffff92c cvdl _sgl_value_3
734 0001E17C # asm("nop");
735 0001E17C 10 nop
736 0001E17D # asm("storer $0x1fff,_store_regs"); /* store regs 0 - 12 */
737 0001E17D bb 891fff effffff922 storer $0x1fff,_store_regs
738 0001E186 # asm("std _dbl_st_acc"); /* save the accumulator */
739 0001E186 27 effffff91c std _dbl_st_acc
740 0001E18C # if( force_loop )
741 0001E18C 5d effffff916 tstl _force_loop
742 0001E192 31 02 jeql L300
743 0001E194 # asm("brb _cvdl_3_lp1");; /* loop on the error */
744 0001E194 11 d0 brb _cvdl_3_lp1
745 0001E196 L300:
746 0001E196 # /*
747 0001E196 # * Now compare the stored register values to those that were loaded
748 0001E196 # */
749 0001E196 # index2 = 0;
750 0001E196 4d effffff90c clrl _index2
751 0001E19C # while( (load_regs[index2] == store_regs[index2]) && (index2 < 13) )
752 0001E19C L301:
753 0001E19C 0d effffff906 50 movl _index2,r0
754 0001E1A3 0d effffff8ff 51 movl _index2,r1
755 0001E1AA 1d 40effffff8f7 cmpl _load_regs[r0],_store_regs[r1]
41effffff8f1
756 0001E1B7 21 11 jneq L302
757 0001E1B9 1d effffff8e9 0d cmpl _index2,$13
758 0001E1C0 81 08 jgeq L302
759 0001E1C2 # index2++; /* check reg values */
760 0001E1C2 6d effffff8e0 incl _index2
761 0001E1C8 11 d2 jbr L301
762 0001E1CA L302:
763 0001E1CA # if( index2 < 13 ) { /* error if index2 < 13 */
764 0001E1CA 1d effffff8d8 0d cmpl _index2,$13
765 0001E1D1 91 03 13 0136 jgeq L303
766 0001E1D6 # errcnt++; /* bump the error count */
767 0001E1D6 6d effffff8cc incl _errcnt
768 0001E1DC # if( prt_error ) {
769 0001E1DC 5d effffff8c6 tstl _prt_error
770 0001E1E2 21 03 13 0102 jeql L304
771 0001E1E7 # writes(" \n"); /* start a new print line */
772 0001E1E7 .data 1
773 00000e12 * L305:
774 00000e12 * 200A00 .ascii " \12\0"
775 00000e15 * .text
776 0001E1E7 dd 8f00000e12 pushl $L305
777 0001E1ED fe 08 effffff8b4 callf $8,_writes
778 0001E1F4 # writes("cycle: ");
779 0001E1F4 .data 1
780 00000e15 * L306:
781 00000e15 * 6379636C653A2000 .ascii "cycle: \0"
782 00000e1d * .text
783 0001E1F4 dd 8f00000e15 pushl $L306
784 0001E1FA fe 08 effffff8a7 callf $8,_writes
785 0001E201 # writed( cycle );
786 0001E201 dd effffff8a1 pushl _cycle
787 0001E207 fe 08 effffff89a callf $8,_writed
788 0001E20E # writes(" CVDL test ");
789 0001E20E .data 1
790 00000e1d * L307:
791 00000e1d * 20204356444C2074657374200 .ascii " CVDL test \0"
0
792 00000e2a * .text
793 0001E20E dd 8f00000e1d pushl $L307
794 0001E214 fe 08 effffff88d callf $8,_writes
795 0001E21B # writed( test_no );
796 0001E21B dd effffff887 pushl _test_no
797 0001E221 fe 08 effffff880 callf $8,_writed
798 0001E228 # writes(", subtest 3 - A REGISTER WAS MODIFIED\n");
799 0001E228 .data 1
800 00000e2a * L308:
801 00000e2a * 2C20737562746573742033202 .ascii ", subtest 3 - A REGISTER WAS MODIFIED\12\0"
D204120524547495354455220
574153204D4F4449464945440
A00
802 00000e51 * .text
803 0001E228 dd 8f00000e2a pushl $L308
804 0001E22E fe 08 effffff873 callf $8,_writes
805 0001E235 # print_cvdl_data(); /* print the operands */
806 0001E235 fe 04 ef0000033c callf $4,_print_cvdl_data
807 0001E23C # writec('\n');
808 0001E23C dd 0a pushl $10
809 0001E23E fe 08 effffff863 callf $8,_writec
810 0001E245 # writes(" final Acc = ");
811 0001E245 .data 1
812 00000e51 * L309:
813 00000e51 * 202066696E616C20416363203 .ascii " final Acc = \0"
D2000
814 00000e60 * .text
815 0001E245 dd 8f00000e51 pushl $L309
816 0001E24B fe 08 effffff856 callf $8,_writes
817 0001E252 # write32h( dbl_st_acc.m );
818 0001E252 dd effffff850 pushl _dbl_st_acc
819 0001E258 fe 08 effffff849 callf $8,_write32h
820 0001E25F # writec(' ');
821 0001E25F dd 20 pushl $32
822 0001E261 fe 08 effffff840 callf $8,_writec
823 0001E268 # write32h( dbl_st_acc.l );
824 0001E268 dd effffff83e pushl _dbl_st_acc+4
825 0001E26E fe 08 effffff833 callf $8,_write32h
826 0001E275 # writec('\n');
827 0001E275 dd 0a pushl $10
828 0001E277 fe 08 effffff82a callf $8,_writec
829 0001E27E # writes("register "); /* print the information */
830 0001E27E .data 1
831 00000e60 * L310:
832 00000e60 * 72656769737465722000 .ascii "register \0"
833 00000e6a * .text
834 0001E27E dd 8f00000e60 pushl $L310
835 0001E284 fe 08 effffff81d callf $8,_writes
836 0001E28B # writed( index2 ); /* about the corrupted */
837 0001E28B dd effffff817 pushl _index2
838 0001E291 fe 08 effffff810 callf $8,_writed
839 0001E298 # writes(" = "); /* register */
840 0001E298 .data 1
841 00000e6a * L311:
842 00000e6a * 203D2000 .ascii " = \0"
843 00000e6e * .text
844 0001E298 dd 8f00000e6a pushl $L311
845 0001E29E fe 08 effffff803 callf $8,_writes
846 0001E2A5 # write32h( store_regs[index2] );
847 0001E2A5 0d effffff7fd 50 movl _index2,r0
848 0001E2AC dd 40effffff7f5 pushl _store_regs[r0]
849 0001E2B3 fe 08 effffff7ee callf $8,_write32h
850 0001E2BA # writes(", should be = ");
851 0001E2BA .data 1
852 00000e6e * L312:
853 00000e6e * 2C202073686F756C642062652 .ascii ", should be = \0"
03D2000
854 00000e7e * .text
855 0001E2BA dd 8f00000e6e pushl $L312
856 0001E2C0 fe 08 effffff7e1 callf $8,_writes
857 0001E2C7 # write32h( load_regs[index2] );
858 0001E2C7 0d effffff7db 50 movl _index2,r0
859 0001E2CE dd 40effffff7d3 pushl _load_regs[r0]
860 0001E2D5 fe 08 effffff7cc callf $8,_write32h
861 0001E2DC # writes("\n");
862 0001E2DC .data 1
863 00000e7e * L313:
864 00000e7e * 0A00 .ascii "\12\0"
865 00000e80 * .text
866 0001E2DC dd 8f00000e7e pushl $L313
867 0001E2E2 fe 08 effffff7bf callf $8,_writes
868 0001E2E9 # }
869 0001E2E9 # if( halt_flg )
870 0001E2E9 L304:
871 0001E2E9 5d effffff7b9 tstl _halt_flg
872 0001E2EF 31 09 jeql L314
873 0001E2F1 # cvdl_er_halt( BAD_REG_HLT ); /* halt on the error */
874 0001E2F1 dd 02 pushl $2
875 0001E2F3 fe 08 ef000002d0 callf $8,_cvdl_er_halt
876 0001E2FA # if( loop_on_err ) {
877 0001E2FA L314:
878 0001E2FA 5d effffff7a8 tstl _loop_on_err
879 0001E300 31 0a jeql L315
880 0001E302 # force_loop = TRUE; /* set the force loop flag */
881 0001E302 0d 01 effffff79f movl $1,_force_loop
882 0001E309 # asm("brw _cvdl_3_lp1");; /* and loop on the error */
883 0001E309 13 fe5a brw _cvdl_3_lp1
884 0001E30C # } /* end of loop on error */
885 0001E30C # } while( index++ < max_cvdl_1_index );/* end of reg corruption error */
886 0001E30C L315:
887 0001E30C L303:
888 0001E30C L316:
889 0001E30C 0d effffff796 50 movl _index,r0
890 0001E313 6d effffff78f incl _index
891 0001E319 1d 50 effffff788 cmpl r0,_max_cvdl_1_index
892 0001E320 81 02 jgeq L317
893 0001E322 11 e8 jbr L316
894 0001E324 L317:
895 0001E324 # } /* end of subtest 3 */
896 0001E324 40 ret#2
897 0001E325 .set L295,0x0
898 0001E325 L297:
899 0001E325 13 fded jbr L298
900 0001E328 .data
901 00000c48 * .text
902 0001E328 .align 1
903 0001E328 .globl _cvdl_4
904 0001E328 _cvdl_4:
905 0001E328 0000 .word L318
906 0001E32A #
907 0001E32A #
908 0001E32A #
909 0001E32A # /************************************************************************
910 0001E32A # *
911 0001E32A # * SUBTEST 4 - Check for PSL corruption
912 0001E32A # *
913 0001E32A # ************************************************************************/
914 0001E32A # cvdl_4()
915 0001E32A # {
916 0001E32A 13 0247 jbr L320
917 0001E32D L321:
918 0001E32D # force_loop = FALSE; /* clear force_loop flg */
919 0001E32D 4d effffff775 clrl _force_loop
920 0001E333 # subtest = 4;
921 0001E333 0d 04 effffff76e movl $4,_subtest
922 0001E33A # for( index = 0; index < max_cvdl_1_index; index++ ) {
923 0001E33A 4d effffff768 clrl _index
924 0001E340 L324:
925 0001E340 1d effffff762 effffff75d cmpl _index,_max_cvdl_1_index
926 0001E34B 91 03 13 0223 jgeq L323
927 0001E350 # dbl_ld_acc = cvdl_1_data[index].ld; /* get the operand */
928 0001E350 5c 0c effffff751 50 mull3 $12,_index,r0
929 0001E358 0c 8f00000000 50 addl2 $_cvdl_1_data,r0
930 0001E35F 0d a004 effffff745 movl 4(r0),_dbl_ld_acc+4
931 0001E367 0d 60 effffff73a movl (r0),_dbl_ld_acc
932 0001E36E # sgl_expected = cvdl_1_data[index].exp; /* get expected */
933 0001E36E 5c 0c effffff733 50 mull3 $12,_index,r0
934 0001E376 0d e000000008 effffff727 movl _cvdl_1_data+8(r0),_sgl_expected
935 0001E381 # sgl_value_1 = dbl_ld_acc.m;
936 0001E381 0d effffff721 effffff71c movl _dbl_ld_acc,_sgl_value_1
937 0001E38C # sgl_value_2 = dbl_ld_acc.l;
938 0001E38C 0d effffff71a effffff711 movl _dbl_ld_acc+4,_sgl_value_2
939 0001E397 # for( status_index = 0; status_index < 3; status_index++ ) {
940 0001E397 4d effffff70b clrl _status_index
941 0001E39D L327:
942 0001E39D 1d effffff705 03 cmpl _status_index,$3
943 0001E3A4 91 03 13 01c1 jgeq L326
944 0001E3A9 # sgl_dummy1 = status_array[status_index];/* status = +, -, 0 */
945 0001E3A9 0d effffff6f9 50 movl _status_index,r0
946 0001E3B0 0d 40effffff6f1 movl _status_array[r0],_sgl_dummy1
effffff6ec
947 0001E3BC # /*
948 0001E3BC # * If LOOP ON ERROR is set, this is the loop for this subtest.
949 0001E3BC # * The force loop flag is set after the first error.
950 0001E3BC # */
951 0001E3BC # asm("_cvdl_4_lp1:");
952 0001E3BC _cvdl_4_lp1:
953 0001E3BC # asm("movl _sgl_value_1,r4"); /* put MS value in r4 */
954 0001E3BC 0d effffff6e6 54 movl _sgl_value_1,r4
955 0001E3C3 # asm("movl _sgl_value_2,r5"); /* put LS value in r5 */
956 0001E3C3 0d effffff6df 55 movl _sgl_value_2,r5
957 0001E3CA # asm("ldd r4"); /* load the acc */
958 0001E3CA 07 54 ldd r4
959 0001E3CC # asm("tstl _sgl_dummy1"); /* set the PSL status */
960 0001E3CC 5d effffff6d6 tstl _sgl_dummy1
961 0001E3D2 # asm("movpsl _init_psl"); /* save the initial PSL */
962 0001E3D2 cd effffff6d0 movpsl _init_psl
963 0001E3D8 # asm("nop");
964 0001E3D8 10 nop
965 0001E3D9 # asm("cvdl r8"); /* convert the value */
966 0001E3D9 87 58 cvdl r8
967 0001E3DB # asm("nop");
968 0001E3DB 10 nop
969 0001E3DC # asm("movpsl _psl_val"); /* save the final PSL */
970 0001E3DC cd effffff6c6 movpsl _psl_val
971 0001E3E2 # asm("nop");
972 0001E3E2 10 nop
973 0001E3E3 # asm("std _dbl_st_acc"); /* save the accumulator */
974 0001E3E3 27 effffff6bf std _dbl_st_acc
975 0001E3E9 # if( force_loop )
976 0001E3E9 5d effffff6b9 tstl _force_loop
977 0001E3EF 31 02 jeql L328
978 0001E3F1 # asm("brb _cvdl_4_lp1");; /* loop on the error */
979 0001E3F1 11 c9 brb _cvdl_4_lp1
980 0001E3F3 L328:
981 0001E3F3 # /*
982 0001E3F3 # * Now compare the final PSL to the initial PSL -they should be the same
983 0001E3F3 # */
984 0001E3F3 # asm("movl r8,_sgl_value_3"); /* mave result to cache */
985 0001E3F3 0d 58 effffff6ae movl r8,_sgl_value_3
986 0001E3FA # exp_psl = init_psl; /* get the initial PSL */
987 0001E3FA 0d effffff6a8 effffff6a3 movl _init_psl,_exp_psl
988 0001E405 # exp_psl &= 0xfffffff3; /* clear ZERO, NEGATIVE */
989 0001E405 ac 88f3 effffff69b andl2 $-13,_exp_psl
990 0001E40D # if( !sgl_expected )
991 0001E40D 5d effffff695 tstl _sgl_expected
992 0001E413 21 07 jneq L329
993 0001E415 # exp_psl |= PSL_Z; /* expect ZERO bit set */
994 0001E415 8c 04 effffff68c orl2 $4,_exp_psl
995 0001E41C # if( sgl_expected < 0 )
996 0001E41C L329:
997 0001E41C 5d effffff686 tstl _sgl_expected
998 0001E422 81 07 jgeq L330
999 0001E424 # exp_psl |= PSL_N; /* expect NEG bit set */
1000 0001E424 8c 08 effffff67d orl2 $8,_exp_psl
1001 0001E42B # if( psl_val != exp_psl ) {
1002 0001E42B L330:
1003 0001E42B 1d effffff677 effffff672 cmpl _psl_val,_exp_psl
1004 0001E436 21 03 13 0126 jeql L331
1005 0001E43B # errcnt++; /* bump error count */
1006 0001E43B 6d effffff667 incl _errcnt
1007 0001E441 # if( prt_error ) {
1008 0001E441 5d effffff661 tstl _prt_error
1009 0001E447 21 03 13 00f2 jeql L332
1010 0001E44C # writes(" \n"); /* start new print line */
1011 0001E44C .data 1
1012 00000e80 * L333:
1013 00000e80 * 200A00 .ascii " \12\0"
1014 00000e83 * .text
1015 0001E44C dd 8f00000e80 pushl $L333
1016 0001E452 fe 08 effffff64f callf $8,_writes
1017 0001E459 # writes("cycle: ");
1018 0001E459 .data 1
1019 00000e83 * L334:
1020 00000e83 * 6379636C653A2000 .ascii "cycle: \0"
1021 00000e8b * .text
1022 0001E459 dd 8f00000e83 pushl $L334
1023 0001E45F fe 08 effffff642 callf $8,_writes
1024 0001E466 # writed( cycle );
1025 0001E466 dd effffff63c pushl _cycle
1026 0001E46C fe 08 effffff635 callf $8,_writed
1027 0001E473 # writes(
1028 0001E473 # " CVDL test 24, subtest 4 - INCORRECT FINAL PSL\n");
1029 0001E473 .data 1
1030 00000e8b * L335:
1031 00000e8b * 20204356444C2074657374203 .ascii " CVDL test 24, subtest 4 - INCORRECT FINAL PSL\12\0"
2342C20737562746573742034
202D20494E434F52524543542
046494E414C2050534C0A00
1032 00000ebc * .text
1033 0001E473 dd 8f00000e8b pushl $L335
1034 0001E479 fe 08 effffff628 callf $8,_writes
1035 0001E480 # print_cvdl_data(); /* print operands */
1036 0001E480 fe 04 ef000000f1 callf $4,_print_cvdl_data
1037 0001E487 # writes(", index = ");
1038 0001E487 .data 1
1039 00000ebc * L336:
1040 00000ebc * 2C202020696E646578203D200 .ascii ", index = \0"
0
1041 00000ec9 * .text
1042 0001E487 dd 8f00000ebc pushl $L336
1043 0001E48D fe 08 effffff614 callf $8,_writes
1044 0001E494 # writed( index );
1045 0001E494 dd effffff60e pushl _index
1046 0001E49A fe 08 effffff607 callf $8,_writed
1047 0001E4A1 # writec('\n');
1048 0001E4A1 dd 0a pushl $10
1049 0001E4A3 fe 08 effffff5fe callf $8,_writec
1050 0001E4AA # writes(" final Acc = ");
1051 0001E4AA .data 1
1052 00000ec9 * L337:
1053 00000ec9 * 202066696E616C20416363203 .ascii " final Acc = \0"
D2000
1054 00000ed8 * .text
1055 0001E4AA dd 8f00000ec9 pushl $L337
1056 0001E4B0 fe 08 effffff5f1 callf $8,_writes
1057 0001E4B7 # write32h( dbl_st_acc.m );
1058 0001E4B7 dd effffff5eb pushl _dbl_st_acc
1059 0001E4BD fe 08 effffff5e4 callf $8,_write32h
1060 0001E4C4 # writec(' ');
1061 0001E4C4 dd 20 pushl $32
1062 0001E4C6 fe 08 effffff5db callf $8,_writec
1063 0001E4CD # write32h( dbl_st_acc.l );
1064 0001E4CD dd effffff5d9 pushl _dbl_st_acc+4
1065 0001E4D3 fe 08 effffff5ce callf $8,_write32h
1066 0001E4DA # writec('\n');
1067 0001E4DA dd 0a pushl $10
1068 0001E4DC fe 08 effffff5c5 callf $8,_writec
1069 0001E4E3 # writes("initial PSL = ");
1070 0001E4E3 .data 1
1071 00000ed8 * L338:
1072 00000ed8 * 696E697469616C2050534C203 .ascii "initial PSL = \0"
D2000
1073 00000ee7 * .text
1074 0001E4E3 dd 8f00000ed8 pushl $L338
1075 0001E4E9 fe 08 effffff5b8 callf $8,_writes
1076 0001E4F0 # write32h( init_psl );
1077 0001E4F0 dd effffff5b2 pushl _init_psl
1078 0001E4F6 fe 08 effffff5ab callf $8,_write32h
1079 0001E4FD # writes(", final PSL = ");
1080 0001E4FD .data 1
1081 00000ee7 * L339:
1082 00000ee7 * 2C202066696E616C2050534C2 .ascii ", final PSL = \0"
03D2000
1083 00000ef7 * .text
1084 0001E4FD dd 8f00000ee7 pushl $L339
1085 0001E503 fe 08 effffff59e callf $8,_writes
1086 0001E50A # write32h( psl_val );
1087 0001E50A dd effffff598 pushl _psl_val
1088 0001E510 fe 08 effffff591 callf $8,_write32h
1089 0001E517 # writes(", expected PSL = ");
1090 0001E517 .data 1
1091 00000ef7 * L340:
1092 00000ef7 * 2C20206578706563746564205 .ascii ", expected PSL = \0"
0534C203D2000
1093 00000f0a * .text
1094 0001E517 dd 8f00000ef7 pushl $L340
1095 0001E51D fe 08 effffff584 callf $8,_writes
1096 0001E524 # write32h( exp_psl );
1097 0001E524 dd effffff57e pushl _exp_psl
1098 0001E52A fe 08 effffff577 callf $8,_write32h
1099 0001E531 # writes("\n");
1100 0001E531 .data 1
1101 00000f0a * L341:
1102 00000f0a * 0A00 .ascii "\12\0"
1103 00000f0c * .text
1104 0001E531 dd 8f00000f0a pushl $L341
1105 0001E537 fe 08 effffff56a callf $8,_writes
1106 0001E53E # }
1107 0001E53E # if( halt_flg )
1108 0001E53E L332:
1109 0001E53E 5d effffff564 tstl _halt_flg
1110 0001E544 31 09 jeql L342
1111 0001E546 # cvdl_er_halt( BAD_PSL_HLT ); /* halt on error */
1112 0001E546 dd 03 pushl $3
1113 0001E548 fe 08 ef0000007b callf $8,_cvdl_er_halt
1114 0001E54F # if( loop_on_err ) {
1115 0001E54F L342:
1116 0001E54F 5d effffff553 tstl _loop_on_err
1117 0001E555 31 0a jeql L343
1118 0001E557 # force_loop = TRUE; /* set force loop flag */
1119 0001E557 0d 01 effffff54a movl $1,_force_loop
1120 0001E55E # asm("brw _cvdl_4_lp1");; /* and loop on error */
1121 0001E55E 13 fe5b brw _cvdl_4_lp1
1122 0001E561 # } /* end of loop on error */
1123 0001E561 # } /* end of PSL corruption error */
1124 0001E561 L343:
1125 0001E561 # } /* end of status WHILE loop */
1126 0001E561 L331:
1127 0001E561 L325:
1128 0001E561 6d effffff541 incl _status_index
1129 0001E567 13 fe33 jbr L327
1130 0001E56A L326:
1131 0001E56A # } /* end of data WHILE loop */
1132 0001E56A L322:
1133 0001E56A 6d effffff538 incl _index
1134 0001E570 13 fdcd jbr L324
1135 0001E573 L323:
1136 0001E573 # } /* end of subtest 4 */
1137 0001E573 40 ret#2
1138 0001E574 .set L318,0x0
1139 0001E574 L320:
1140 0001E574 13 fdb6 jbr L321
1141 0001E577 .data
1142 00000c48 * .text
1143 0001E577 00 .align 1
1144 0001E578 .globl _print_cvdl_data
1145 0001E578 _print_cvdl_data:
1146 0001E578 0000 .word L344
1147 0001E57A #
1148 0001E57A #
1149 0001E57A #
1150 0001E57A # /**************************************************************************
1151 0001E57A # *
1152 0001E57A # * PRINT THE DATA AND STORE RESULTS
1153 0001E57A # *
1154 0001E57A # * initial Acc = xxxxxxxx xxxxxxxx, integer stored = xxxxxxxx
1155 0001E57A # **************************************************************************/
1156 0001E57A # print_cvdl_data()
1157 0001E57A # {
1158 0001E57A 11 4b jbr L346
1159 0001E57C L347:
1160 0001E57C # writes("initial Acc = ");
1161 0001E57C .data 1
1162 00000f0c * L348:
1163 00000f0c * 696E697469616C20416363203 .ascii "initial Acc = \0"
D2000
1164 00000f1b * .text
1165 0001E57C dd 8f00000f0c pushl $L348
1166 0001E582 fe 08 effffff51f callf $8,_writes
1167 0001E589 # write32h( dbl_ld_acc.m );
1168 0001E589 dd effffff519 pushl _dbl_ld_acc
1169 0001E58F fe 08 effffff512 callf $8,_write32h
1170 0001E596 # writec(' ');
1171 0001E596 dd 20 pushl $32
1172 0001E598 fe 08 effffff509 callf $8,_writec
1173 0001E59F # write32h( dbl_ld_acc.l );
1174 0001E59F dd effffff507 pushl _dbl_ld_acc+4
1175 0001E5A5 fe 08 effffff4fc callf $8,_write32h
1176 0001E5AC # writes(", int. stored = ");
1177 0001E5AC .data 1
1178 00000f1b * L349:
1179 00000f1b * 2C20202020696E742E2073746 .ascii ", int. stored = \0"
F726564203D2000
1180 00000f2f * .text
1181 0001E5AC dd 8f00000f1b pushl $L349
1182 0001E5B2 fe 08 effffff4ef callf $8,_writes
1183 0001E5B9 # write32h( sgl_value_3 );
1184 0001E5B9 dd effffff4e9 pushl _sgl_value_3
1185 0001E5BF fe 08 effffff4e2 callf $8,_write32h
1186 0001E5C6 # }
1187 0001E5C6 40 ret#2
1188 0001E5C7 .set L344,0x0
1189 0001E5C7 L346:
1190 0001E5C7 11 b3 jbr L347
1191 0001E5C9 .data
1192 00000c48 * .text
1193 0001E5C9 00 .align 1
1194 0001E5CA .globl _cvdl_er_halt
1195 0001E5CA _cvdl_er_halt:
1196 0001E5CA 0000 .word L350
1197 0001E5CC #
1198 0001E5CC #
1199 0001E5CC #
1200 0001E5CC # /**************************************************************************
1201 0001E5CC # *
1202 0001E5CC # * HALT ON ERROR ROUTINE
1203 0001E5CC # *
1204 0001E5CC # **************************************************************************/
1205 0001E5CC # cvdl_er_halt( halt_code )
1206 0001E5CC # int halt_code;
1207 0001E5CC # {
1208 0001E5CC 13 011c jbr L352
1209 0001E5CF L353:
1210 0001E5CF # sgl_value_1 = dbl_ld_acc.m;
1211 0001E5CF 0d effffff4d3 effffff4ce movl _dbl_ld_acc,_sgl_value_1
1212 0001E5DA # sgl_value_2 = dbl_ld_acc.l;
1213 0001E5DA 0d effffff4cc effffff4c3 movl _dbl_ld_acc+4,_sgl_value_2
1214 0001E5E5 # sgl_value_4 = dbl_st_acc.m;
1215 0001E5E5 0d effffff4bd effffff4b8 movl _dbl_st_acc,_sgl_value_4
1216 0001E5F0 # sgl_value_5 = dbl_st_acc.l;
1217 0001E5F0 0d effffff4b6 effffff4ad movl _dbl_st_acc+4,_sgl_value_5
1218 0001E5FB # sgl_dummy1 = halt_code; /* get the error type */
1219 0001E5FB 0d ad04 effffff4a5 movl 4(fp),_sgl_dummy1
1220 0001E603 # asm("movl _test_no,r0"); /* r0 = test number */
1221 0001E603 0d effffff49f 50 movl _test_no,r0
1222 0001E60A # asm("movl _subtest,r1"); /* r1 = subtest number */
1223 0001E60A 0d effffff498 51 movl _subtest,r1
1224 0001E611 # asm("movl _sgl_dummy1,r2"); /* r2 = error code */
1225 0001E611 0d effffff491 52 movl _sgl_dummy1,r2
1226 0001E618 # asm("movl _cycle,r3"); /* r3 = cycle count */
1227 0001E618 0d effffff48a 53 movl _cycle,r3
1228 0001E61F # asm("movl _sgl_value_1,r4"); /* r4 = MS acc loaded */
1229 0001E61F 0d effffff483 54 movl _sgl_value_1,r4
1230 0001E626 # asm("movl _sgl_value_2,r5"); /* r5 = LS acc loaded */
1231 0001E626 0d effffff47c 55 movl _sgl_value_2,r5
1232 0001E62D # asm("movl _sgl_value_4,r6"); /* r6 = MS acc stored */
1233 0001E62D 0d effffff475 56 movl _sgl_value_4,r6
1234 0001E634 # asm("movl _sgl_value_5,r7"); /* r7 = LS acc stored */
1235 0001E634 0d effffff46e 57 movl _sgl_value_5,r7
1236 0001E63B # asm("movl _sgl_value_3,r8"); /* r8 = integer stored */
1237 0001E63B 0d effffff467 58 movl _sgl_value_3,r8
1238 0001E642 # if( halt_code == BAD_ACC_HLT ) {
1239 0001E642 1d ad04 01 cmpl 4(fp),$1
1240 0001E646 21 2d jneq L354
1241 0001E648 # sgl_value_1 = dbl_expected.m;
1242 0001E648 0d effffff45a effffff455 movl _dbl_expected,_sgl_value_1
1243 0001E653 # sgl_value_2 = dbl_expected.l;
1244 0001E653 0d effffff453 effffff44a movl _dbl_expected+4,_sgl_value_2
1245 0001E65E # asm("movl _sgl_value_1,r9"); /* r9 = MS expected */
1246 0001E65E 0d effffff444 59 movl _sgl_value_1,r9
1247 0001E665 # asm("movl _sgl_value_2,r10"); /* r10 = LS expected */
1248 0001E665 0d effffff43d 5a movl _sgl_value_2,r10
1249 0001E66C # asm("movl _index,r11"); /* r11 = data index */
1250 0001E66C 0d effffff436 5b movl _index,r11
1251 0001E673 # } else
1252 0001E673 11 74 jbr L355
1253 0001E675 L354:
1254 0001E675 # if( halt_code == BAD_STORE_HLT ) {
1255 0001E675 1d ad04 09 cmpl 4(fp),$9
1256 0001E679 21 10 jneq L356
1257 0001E67B # asm("movl _sgl_expected,r9"); /* r9 = int expected */
1258 0001E67B 0d effffff427 59 movl _sgl_expected,r9
1259 0001E682 # asm("movl _index,r10"); /* r10 = data index */
1260 0001E682 0d effffff420 5a movl _index,r10
1261 0001E689 # } else
1262 0001E689 11 5e jbr L357
1263 0001E68B L356:
1264 0001E68B # if( halt_code == BAD_REG_HLT ) {
1265 0001E68B 1d ad04 02 cmpl 4(fp),$2
1266 0001E68F 21 3d jneq L358
1267 0001E691 # sgl_dummy1 = load_regs[index2];
1268 0001E691 0d effffff411 50 movl _index2,r0
1269 0001E698 0d 40effffff409 movl _load_regs[r0],_sgl_dummy1
effffff404
1270 0001E6A4 # sgl_dummy2 = store_regs[index2];
1271 0001E6A4 0d effffff3fe 50 movl _index2,r0
1272 0001E6AB 0d 40effffff3f6 movl _store_regs[r0],_sgl_dummy2
effffff3f1
1273 0001E6B7 # asm("movl _index2,r9"); /* r9 = bad register # */
1274 0001E6B7 0d effffff3eb 59 movl _index2,r9
1275 0001E6BE # asm("movl _sgl_dummy2,r10"); /* r10 = actual value */
1276 0001E6BE 0d effffff3e4 5a movl _sgl_dummy2,r10
1277 0001E6C5 # asm("movl _sgl_dummy1,r11"); /* r11 = expected value */
1278 0001E6C5 0d effffff3dd 5b movl _sgl_dummy1,r11
1279 0001E6CC # } else
1280 0001E6CC 11 1b jbr L359
1281 0001E6CE L358:
1282 0001E6CE # if( halt_code == BAD_PSL_HLT ) {
1283 0001E6CE 1d ad04 03 cmpl 4(fp),$3
1284 0001E6D2 21 15 jneq L360
1285 0001E6D4 # asm("movl _init_psl,r9"); /* r9 = initial PSL */
1286 0001E6D4 0d effffff3ce 59 movl _init_psl,r9
1287 0001E6DB # asm("movl _psl_val,r10"); /* r10 = final PSL */
1288 0001E6DB 0d effffff3c7 5a movl _psl_val,r10
1289 0001E6E2 # asm("movl _exp_psl,r11"); /* r11 = expected PSL */
1290 0001E6E2 0d effffff3c0 5b movl _exp_psl,r11
1291 0001E6E9 # };
1292 0001E6E9 L360:
1293 0001E6E9 L359:
1294 0001E6E9 L357:
1295 0001E6E9 L355:
1296 0001E6E9 # asm("halt"); /* HALT ... */
1297 0001E6E9 00 halt
1298 0001E6EA # }
1299 0001E6EA 40 ret#2
1300 0001E6EB .set L350,0x0
1301 0001E6EB L352:
1302 0001E6EB 13 fee1 jbr L353
1303 0001E6EE .data
1303 0003C196 .data
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