![[BACK]](/cvsweb/icons/back.gif){kind=icon}
Return to cvfl.c CVS log ![[TXT]](/cvsweb/icons/text.gif){kind=icon}
![[DIR]](/cvsweb/icons/dir.gif){kind=icon}
Up to [Power 6/32 Unix Tahoe 4.2BSD] / cci / d / macro4|
Return to cvfl.c CVS log | Up to [Power 6/32 Unix Tahoe 4.2BSD] / cci / d / macro4 |
1.1 root 1:
2: #include "fpp_defs.h"
3:
4:
5: /*****************************************************************************
6: *
7: * CVFL - CONVERT SINGLE PRECISION TO LONGWORD INTEGER
8: *
9: *****************************************************************************/
10: cvfl()
11: {
12: asm(".globl _cvfl_t");
13: asm("_cvfl_t:"); /* entry address */
14: if( ( cycle == 1 ) && ( prt_hdrs ) ) /* print headers on 1st cycle */
15: writes(" CVFL");
16: cvfl_1(); /* load through a register */
17: cvfl_2(); /* load through the cache */
18: cvfl_3(); /* register stability */
19: cvfl_4(); /* PSL stability test */
20: cvfl_5(); /* pipelined entry test */
21: if( !no_fpp_wcs )
22: cvfl_6();; /* pipelined exit test */
23: asm("jmp *return"); /* return to the test monitor */
24: }
25:
26:
27:
28: /************************************************************************
29: *
30: * SUBTEST 1 - convert through a register
31: *
32: ************************************************************************/
33: cvfl_1()
34: {
35: force_loop = FALSE;
36: subtest = 1;
37: for( index = 0; index < max_cvfl_1_index; index++ ) {
38: sgl_ld_acc = cvfl_1_data[index].ld; /* get value to negate */
39: sgl_expected = cvfl_1_data[index].exp; /* get expected result */
40: /*
41: * If LOOP ON ERROR is set, this is the loop for this subtest.
42: * The force loop flag is set after the first error.
43: */
44: asm("_cvfl_1_lp1:");
45: asm("movl _sgl_ld_acc,r4"); /* get the value to convert */
46: asm("ldf r4"); /* load the value */
47: asm("cvfl r5"); /* store the result in R5 */
48: asm("stf _sgl_st_acc"); /* save the acc */
49: if( force_loop )
50: asm("brb _cvfl_1_lp1");; /* loop on the error */
51: /*
52: * end error loop - test the results
53: */
54: asm("movl r5,_sgl_value_1"); /* move R5 data to cache */
55: if( sgl_value_1 != sgl_expected ) {/* COMPARE the values */
56: errcnt++; /* bump the error count */
57: if( prt_error ) {
58: writes(" \n"); /* start a new print line */
59: writes("cycle: ");
60: writed( cycle );
61: writes(" CVFL test ");
62: writed( test_no );
63: writes(", subtest 1 (Reg. Data) - WRONG DATA STORED\n");
64: print_cvfl_data();
65: writes(", data index = ");
66: writed( index );
67: writec('\n');
68: writes(" final Acc = ");
69: write32h( sgl_st_acc );
70: writes(", int. expected = ");
71: write32h( sgl_expected );
72: writec('\n');
73: }
74: if( halt_flg )
75: cvfl_er_halt( BAD_STORE_HLT ); /* halt on the error */
76: if( loop_on_err ) {
77: force_loop = TRUE; /* set the force loop flag */
78: asm("brw _cvfl_1_lp1");; /* and loop on the error */
79: } /* end of loop on error */
80: } /* end of wrong data compare error */
81: } /* end of WHILE loop */
82: } /* end of subtest 1 */
83:
84:
85:
86: /************************************************************************
87: *
88: * SUBTEST 2 - convert through memory
89: *
90: ************************************************************************/
91: cvfl_2()
92: {
93: force_loop = FALSE;
94: subtest = 2;
95: for( index = 0; index < max_cvfl_1_index; index++ ) {
96: sgl_ld_acc = cvfl_1_data[index].ld; /* get value to convert */
97: sgl_expected = cvfl_1_data[index].exp; /* get expected result */
98: /*
99: * If LOOP ON ERROR is set, this is the loop for this subtest.
100: * The force loop flag is set after the first error.
101: */
102: asm("_cvfl_2_lp1:");
103: asm("ldf _sgl_ld_acc"); /* load the base value */
104: asm("cvfl _sgl_value_1"); /* store the result */
105: asm("stf _sgl_st_acc"); /* save the acc */
106: if( force_loop )
107: asm("brb _cvfl_2_lp1");; /* loop on the error */
108: /*
109: * end error loop - test the results
110: */
111: if( sgl_value_1 != sgl_expected ) {/* COMPARE the values */
112: errcnt++; /* bump the error count */
113: if( prt_error ) {
114: writes(" \n"); /* start a new print line */
115: writes("cycle: ");
116: writed( cycle );
117: writes(" CVFL test ");
118: writed( test_no );
119: writes(
120: ", subtest 2 (Cache Data) - WRONG DATA STORED\n");
121: print_cvfl_data();
122: writes(", data index = ");
123: writed( index );
124: writec('\n');
125: writes(" final Acc = ");
126: write32h( sgl_value_1 );
127: writes(", int. expected = ");
128: write32h( sgl_expected );
129: writec('\n');
130: }
131: if( halt_flg )
132: cvfl_er_halt( BAD_STORE_HLT ); /* halt on the error */
133: if( loop_on_err ) {
134: force_loop = TRUE; /* set the force loop flag */
135: asm("brw _cvfl_1_lp1");; /* and loop on the error */
136: } /* end of loop on error */
137: } /* end of compare error */
138: } /* end of WHILE loop */
139: } /* end of subtest 2 */
140:
141:
142:
143: /************************************************************************
144: *
145: * SUBTEST 3 - Check for register corruption
146: *
147: ************************************************************************/
148: cvfl_3()
149: {
150: force_loop = FALSE; /* clear force_loop flg */
151: subtest = 3;
152: fill_reg_buf( load_regs ); /* get patterns for regs */
153: index = 0;
154: sgl_ld_acc = cvfl_1_data[0].ld; /* get value to convert */
155: sgl_expected = cvfl_1_data[0].exp; /* get expected result */
156: /*
157: * If LOOP ON ERROR is set, this is the loop for this subtest.
158: * The force loop flag is set after the first error.
159: */
160: asm("_cvfl_3_lp1:");
161: asm("ldf _sgl_ld_acc"); /* load base value */
162: asm("loadr $0x1fff,_load_regs"); /* load regs 0 - 12 */
163: asm("nop");
164: asm("cvfl _sgl_value_1"); /* convert the value */
165: asm("nop");
166: asm("stf _sgl_st_acc"); /* store the result */
167: asm("nop");
168: asm("storer $0x1fff,_store_regs"); /* store regs 0 - 12 */
169: if( force_loop )
170: asm("brb _cvfl_3_lp1");; /* loop on the error */
171: /*
172: * Now compare the stored register values to those that were loaded
173: */
174: index2 = 0;
175: while( (load_regs[index2] == store_regs[index2]) && (index2 < 13) )
176: index2++; /* check reg values */
177: if( index2 < 13 ) { /* error if index2 < 13 */
178: errcnt++; /* bump the error count */
179: if( prt_error ) {
180: writes(" \n"); /* start a new print line */
181: writes("cycle: ");
182: writed( cycle );
183: writes(" CVFL test ");
184: writed( test_no );
185: writes(", subtest 3 - A REGISTER WAS MODIFIED\n");
186: print_cvfl_data(); /* print the operands */
187: writes("\n");
188: writes(" final Acc = "); /* print the information */
189: write32h( sgl_value_1 );
190: writes("\n");
191: writes("register ");
192: writed( index2 ); /* about the corrupted */
193: writes(" = "); /* register */
194: write32h( store_regs[index2] );
195: writes(", should be = ");
196: write32h( load_regs[index2] );
197: writes("\n");
198: }
199: if( halt_flg )
200: cvfl_er_halt( BAD_REG_HLT ); /* halt on the error */
201: if( loop_on_err ) {
202: force_loop = TRUE; /* set the force loop flag */
203: asm("brw _cvfl_3_lp1");; /* and loop on the error */
204: } /* end of loop on error */
205: } /* end of register corruption error */
206: } /* end of subtest 3 */
207:
208:
209:
210: /************************************************************************
211: *
212: * SUBTEST 4 - Check for PSL corruption
213: *
214: ************************************************************************/
215: cvfl_4()
216: {
217: force_loop = FALSE; /* clear force_loop flg */
218: subtest = 4;
219: for( index = 0; index < max_cvfl_1_index; index++ ) {
220: sgl_ld_acc = cvfl_1_data[index].ld; /* get value to convert */
221: sgl_expected = cvfl_1_data[index].exp; /* get expected */
222: for( status_index = 0; status_index < 3; status_index++ ) {
223: sgl_dummy1 = status_array[status_index];/* status = +, -, 0 */
224: /*
225: * If LOOP ON ERROR is set, this is the loop for this subtest.
226: * The force loop flag is set after the first error.
227: */
228: asm("_cvfl_4_lp1:");
229: asm("movl _sgl_ld_acc,r4"); /* move operand to r4 */
230: asm("ldf r4"); /* load the operand */
231: asm("tstl _sgl_dummy1"); /* set the PSL status */
232: asm("movpsl _init_psl"); /* save the initial PSL */
233: asm("nop");
234: asm("cvfl r8"); /* convert the value */
235: asm("nop");
236: asm("movpsl _psl_val"); /* save the final PSL */
237: asm("nop");
238: asm("stf _sgl_st_acc"); /* store the result */
239: if( force_loop )
240: asm("brb _cvfl_4_lp1");; /* loop on the error */
241: /*
242: * Now compare the final PSL to the initial PSL -they should be the same
243: */
244: asm("movl r8,_sgl_value_1"); /* save the converted int*/
245: exp_psl = init_psl;
246: exp_psl &= 0xfffffff3; /* clear ZERO, NEGATIVE */
247: if( !sgl_expected )
248: exp_psl |= PSL_Z; /* expect the ZERO bit set */
249: if( sgl_expected < 0 )
250: exp_psl |= PSL_N; /* expect the NEG bit set */
251: if( psl_val != exp_psl ) {
252: errcnt++; /* bump the error count */
253: if( prt_error ) {
254: writes(" \n"); /* start a new print line */
255: writes("cycle: ");
256: writed( cycle );
257: writes(" CVFL test ");
258: writed( test_no );
259: writes(", subtest 4 - INCORRECT FINAL PSL\n");
260: print_cvfl_data(); /* print operands */
261: writes("\n");
262: writes(" final Acc = ");
263: write32h( sgl_st_acc );
264: writes("\n");
265: writes("initial PSL = ");
266: write32h( init_psl );
267: writes(", final PSL = ");
268: write32h( psl_val );
269: writes(", expected PSL = ");
270: write32h( exp_psl );
271: writes("\n");
272: }
273: if( halt_flg )
274: cvfl_er_halt( BAD_PSL_HLT ); /* halt on error */
275: if( loop_on_err ) {
276: force_loop = TRUE; /* set force loop flag */
277: asm("brw _cvfl_4_lp1");;/* and loop on error */
278: } /* end of loop on error */
279: } /* end of PSL corruption error */
280: } /* end of status WHILE loop */
281: } /* end of data WHILE loop */
282: } /* end of subtest 4 */
283:
284:
285:
286: /************************************************************************
287: *
288: * SUBTEST 5 - accumulator corruption
289: *
290: ************************************************************************/
291: cvfl_5()
292: {
293: force_loop = FALSE;
294: subtest = 5;
295: for( index = 0; index < max_cvfl_1_index; index++ ) {
296: sgl_ld_acc = cvfl_1_data[index].ld; /* get value to convert */
297: if( sgl_ld_acc & 0x7f800000 )
298: sgl_expected = sgl_ld_acc;
299: else
300: sgl_expected = 0;
301: /*
302: * If LOOP ON ERROR is set, this is the loop for this subtest.
303: * The force loop flag is set after the first error.
304: */
305: asm("_cvfl_5_lp1:");
306: asm("ldf _sgl_ld_acc"); /* load the base value */
307: asm("cvfl _sgl_value_1"); /* store the result */
308: asm("stf _sgl_st_acc"); /* store the result */
309: if( force_loop )
310: asm("brb _cvfl_5_lp1");; /* loop on the error */
311: /*
312: * end error loop - test the results
313: */
314: if( sgl_st_acc != sgl_expected ) { /* COMPARE the values */
315: errcnt++; /* bump the error count */
316: if( prt_error ) {
317: writes(" \n"); /* start a new print line */
318: writes("cycle: ");
319: writed( cycle );
320: writes(" CVFL test ");
321: writed( test_no );
322: writes(", subtest 5 (Cache Data) - BAD_FINAL_ACC\n");
323: print_cvfl_data();
324: writec('\n');
325: writes(" final Acc = ");
326: write32h( sgl_value_1 );
327: writes(", expected Acc = ");
328: write32h( sgl_ld_acc );
329: writec('\n');
330: }
331: if( halt_flg )
332: cvfl_er_halt( BAD_ACC_HLT ); /* halt on the error */
333: if( loop_on_err ) {
334: force_loop = TRUE; /* set the force loop flag */
335: asm("brw _cvfl_1_lp1");; /* and loop on the error */
336: } /* end of loop on error */
337: } /* end of compare error */
338: } /* end of WHILE loop */
339: } /* end of subtest 5 */
340:
341:
342:
343: /************************************************************************
344: *
345: * SUBTEST 6 - pipelined entry test
346: *
347: ************************************************************************/
348: cvfl_6()
349: {
350: force_loop = FALSE;
351: subtest = 6;
352: for( index = 0; index < max_cvfl_1_index; index++ ) {
353: sgl_ld_acc = cvfl_1_data[index].ld; /* get value to convert */
354: if( sgl_ld_acc & 0x7f800000 )
355: sgl_expected = sgl_ld_acc; /* expected = loaded */
356: else
357: sgl_expected = 0; /* expect a '0' */
358: /*
359: * If LOOP ON ERROR is set, this is the loop for this subtest.
360: * The force loop flag is set after the first error.
361: */
362: asm("_cvfl_6_lp1:");
363: asm("movl $0,r0"); /* clear r0 */
364: asm("ldf r0"); /* load the Acc. with 0.0 */
365: asm("addf _sgl_ld_acc"); /* add the base value */
366: asm("cvfl _sgl_value_1"); /* convert the value */
367: asm("stf _sgl_st_acc"); /* store the result */
368: if( force_loop )
369: asm("brb _cvfl_6_lp1");; /* loop on the error */
370: /*
371: * end error loop - test the results
372: */
373: if( sgl_st_acc != sgl_expected ) { /* COMPARE the values */
374: errcnt++; /* bump the error count */
375: if( prt_error ) {
376: writes(" \n"); /* start a new print line */
377: writes("cycle: ");
378: writed( cycle );
379: writes(" CVFL test ");
380: writed( test_no );
381: writes(", subtest 6 (Piped Entry) - BAD_FINAL_ACC\n");
382: print_cvfl_data();
383: writec('\n');
384: writes(" final Acc = ");
385: write32h( sgl_value_1 );
386: writes(", expected Acc = ");
387: write32h( sgl_ld_acc );
388: writec('\n');
389: }
390: if( halt_flg )
391: cvfl_er_halt( BAD_ACC_HLT ); /* halt on the error */
392: if( loop_on_err ) {
393: force_loop = TRUE; /* set the force loop flag */
394: asm("brw _cvfl_6_lp1");; /* and loop on the error */
395: } /* end of loop on error */
396: } /* end of compare error */
397: } /* end of WHILE loop */
398: } /* end of subtest 6 */
399:
400:
401:
402: /************************************************************************
403: *
404: * SUBTEST 7 - pipelined exit test
405: *
406: ************************************************************************/
407: cvfl_7()
408: {
409: force_loop = FALSE;
410: subtest = 7;
411: for( index = 0; index < max_cvfl_1_index; index++ ) {
412: sgl_ld_acc = cvfl_1_data[index].ld; /* get value to negate */
413: if( sgl_ld_acc & 0x7f800000 )
414: sgl_expected = sgl_ld_acc; /* expected = loaded */
415: else
416: sgl_expected = 0; /* expect a '0' */
417: /*
418: * If LOOP ON ERROR is set, this is the loop for this subtest.
419: * The force loop flag is set after the first error.
420: */
421: asm("_cvfl_7_lp1:");
422: asm("movl $0,r0"); /* clear r0 */
423: asm("ldf _sgl_ld_acc"); /* load the value */
424: asm("cvfl _sgl_value_1"); /* convert the value */
425: asm("addf r0"); /* add a zero to the acc */
426: asm("stf _sgl_st_acc"); /* store the result */
427: if( force_loop )
428: asm("brb _cvfl_7_lp1");; /* loop on the error */
429: /*
430: * end error loop - test the results
431: */
432: if( sgl_st_acc != sgl_expected ) { /* COMPARE the values */
433: errcnt++; /* bump the error count */
434: if( prt_error ) {
435: writes(" \n"); /* start a new print line */
436: writes("cycle: ");
437: writed( cycle );
438: writes(" CVFL test ");
439: writed( test_no );
440: writes(", subtest 7 (piped exit) - BAD_FINAL_ACC\n");
441: print_cvfl_data();
442: writes(" final Acc = ");
443: write32h( sgl_st_acc );
444: writes(", expected Acc = ");
445: if( sgl_ld_acc & 0x7f800000 )
446: write32h( sgl_ld_acc );
447: else
448: write32h( 0 );
449: writec('\n');
450: }
451: if( halt_flg )
452: cvfl_er_halt( BAD_ACC_HLT ); /* halt on the error */
453: if( loop_on_err ) {
454: force_loop = TRUE; /* set the force loop flag */
455: asm("brw _cvfl_7_lp1");; /* and loop on the error */
456: } /* end of loop on error */
457: } /* end of compare error */
458: } /* end of WHILE loop */
459: } /* end of subtest 7 */
460:
461:
462:
463: /**************************************************************************
464: *
465: * PRINT THE DATA AND STORE RESULTS
466: *
467: * initial Acc = xxxxxxxx, int. stored = xxxxxxxx, data index = xx
468: **************************************************************************/
469: print_cvfl_data()
470: {
471: writes("initial Acc = ");
472: write32h( sgl_ld_acc );
473: writes(", int. stored = ");
474: write32h( sgl_value_1 );
475: }
476:
477:
478:
479: /**************************************************************************
480: *
481: * HALT ON ERROR ROUTINE
482: *
483: **************************************************************************/
484: cvfl_er_halt( halt_code )
485: int halt_code;
486: {
487: sgl_dummy1 = halt_code; /* get the error type */
488: asm("movl _test_no,r0"); /* r0 = test number */
489: asm("movl _subtest,r1"); /* r1 = subtest number */
490: asm("movl _sgl_dummy1,r2"); /* r2 = error code */
491: asm("movl _cycle,r3"); /* r3 = cycle count */
492: asm("movl _sgl_ld_acc,r4"); /* r4 = initial data */
493: asm("movl _sgl_value_1,r5"); /* r5 = final acc */
494: asm("movl _sgl_st_acc,r6"); /* r6 = integer stored */
495: if( halt_code == BAD_ACC_HLT ) {
496: asm("movl _sgl_ld_acc,r7"); /* r7 = expected acc */
497: asm("movl _index,r8"); /* r8 = data index */
498: } else
499: if( halt_code == BAD_REG_HLT ) {
500: sgl_dummy1 = load_regs[index2];
501: sgl_dummy2 = store_regs[index2];
502: asm("movl _index2,r7"); /* r7 = bad register # */
503: asm("movl _sgl_dummy2,r8"); /* r8 = final reg value */
504: asm("movl _sgl_dummy1,r9"); /* r9 = init reg value */
505: } else
506: if( halt_code == BAD_PSL_HLT ) {
507: asm("movl _init_psl,r7"); /* r7 = initial PSL */
508: asm("movl _psl_val,r8"); /* r8 = final PSL */
509: asm("movl _exp_psl,r9"); /* r9 = expected PSL */
510: } else
511: if( halt_code == BAD_STORE_HLT ) {
512: asm("movl _sgl_expected,r7"); /* r7 = data expectd */
513: asm("movl _index,r8"); /* r8 = data index */
514: };
515: asm("halt"); /* HALT ... */
516: }
This archive runs on limited infrastructure. Preserving old code on modern bandwidth. Automated agents are requested to crawl responsibly.