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Power 6/32 Unix version 1.21
#include "fpp_defs.h"
/*****************************************************************************
*
* CVFL - CONVERT SINGLE PRECISION TO LONGWORD INTEGER
*
*****************************************************************************/
cvfl()
{
asm(".globl _cvfl_t");
asm("_cvfl_t:"); /* entry address */
if( ( cycle == 1 ) && ( prt_hdrs ) ) /* print headers on 1st cycle */
writes(" CVFL");
cvfl_1(); /* load through a register */
cvfl_2(); /* load through the cache */
cvfl_3(); /* register stability */
cvfl_4(); /* PSL stability test */
cvfl_5(); /* pipelined entry test */
if( !no_fpp_wcs )
cvfl_6();; /* pipelined exit test */
asm("jmp *return"); /* return to the test monitor */
}
/************************************************************************
*
* SUBTEST 1 - convert through a register
*
************************************************************************/
cvfl_1()
{
force_loop = FALSE;
subtest = 1;
for( index = 0; index < max_cvfl_1_index; index++ ) {
sgl_ld_acc = cvfl_1_data[index].ld; /* get value to negate */
sgl_expected = cvfl_1_data[index].exp; /* get expected result */
/*
* If LOOP ON ERROR is set, this is the loop for this subtest.
* The force loop flag is set after the first error.
*/
asm("_cvfl_1_lp1:");
asm("movl _sgl_ld_acc,r4"); /* get the value to convert */
asm("ldf r4"); /* load the value */
asm("cvfl r5"); /* store the result in R5 */
asm("stf _sgl_st_acc"); /* save the acc */
if( force_loop )
asm("brb _cvfl_1_lp1");; /* loop on the error */
/*
* end error loop - test the results
*/
asm("movl r5,_sgl_value_1"); /* move R5 data to cache */
if( sgl_value_1 != sgl_expected ) {/* COMPARE the values */
errcnt++; /* bump the error count */
if( prt_error ) {
writes(" \n"); /* start a new print line */
writes("cycle: ");
writed( cycle );
writes(" CVFL test ");
writed( test_no );
writes(", subtest 1 (Reg. Data) - WRONG DATA STORED\n");
print_cvfl_data();
writes(", data index = ");
writed( index );
writec('\n');
writes(" final Acc = ");
write32h( sgl_st_acc );
writes(", int. expected = ");
write32h( sgl_expected );
writec('\n');
}
if( halt_flg )
cvfl_er_halt( BAD_STORE_HLT ); /* halt on the error */
if( loop_on_err ) {
force_loop = TRUE; /* set the force loop flag */
asm("brw _cvfl_1_lp1");; /* and loop on the error */
} /* end of loop on error */
} /* end of wrong data compare error */
} /* end of WHILE loop */
} /* end of subtest 1 */
/************************************************************************
*
* SUBTEST 2 - convert through memory
*
************************************************************************/
cvfl_2()
{
force_loop = FALSE;
subtest = 2;
for( index = 0; index < max_cvfl_1_index; index++ ) {
sgl_ld_acc = cvfl_1_data[index].ld; /* get value to convert */
sgl_expected = cvfl_1_data[index].exp; /* get expected result */
/*
* If LOOP ON ERROR is set, this is the loop for this subtest.
* The force loop flag is set after the first error.
*/
asm("_cvfl_2_lp1:");
asm("ldf _sgl_ld_acc"); /* load the base value */
asm("cvfl _sgl_value_1"); /* store the result */
asm("stf _sgl_st_acc"); /* save the acc */
if( force_loop )
asm("brb _cvfl_2_lp1");; /* loop on the error */
/*
* end error loop - test the results
*/
if( sgl_value_1 != sgl_expected ) {/* COMPARE the values */
errcnt++; /* bump the error count */
if( prt_error ) {
writes(" \n"); /* start a new print line */
writes("cycle: ");
writed( cycle );
writes(" CVFL test ");
writed( test_no );
writes(
", subtest 2 (Cache Data) - WRONG DATA STORED\n");
print_cvfl_data();
writes(", data index = ");
writed( index );
writec('\n');
writes(" final Acc = ");
write32h( sgl_value_1 );
writes(", int. expected = ");
write32h( sgl_expected );
writec('\n');
}
if( halt_flg )
cvfl_er_halt( BAD_STORE_HLT ); /* halt on the error */
if( loop_on_err ) {
force_loop = TRUE; /* set the force loop flag */
asm("brw _cvfl_1_lp1");; /* and loop on the error */
} /* end of loop on error */
} /* end of compare error */
} /* end of WHILE loop */
} /* end of subtest 2 */
/************************************************************************
*
* SUBTEST 3 - Check for register corruption
*
************************************************************************/
cvfl_3()
{
force_loop = FALSE; /* clear force_loop flg */
subtest = 3;
fill_reg_buf( load_regs ); /* get patterns for regs */
index = 0;
sgl_ld_acc = cvfl_1_data[0].ld; /* get value to convert */
sgl_expected = cvfl_1_data[0].exp; /* get expected result */
/*
* If LOOP ON ERROR is set, this is the loop for this subtest.
* The force loop flag is set after the first error.
*/
asm("_cvfl_3_lp1:");
asm("ldf _sgl_ld_acc"); /* load base value */
asm("loadr $0x1fff,_load_regs"); /* load regs 0 - 12 */
asm("nop");
asm("cvfl _sgl_value_1"); /* convert the value */
asm("nop");
asm("stf _sgl_st_acc"); /* store the result */
asm("nop");
asm("storer $0x1fff,_store_regs"); /* store regs 0 - 12 */
if( force_loop )
asm("brb _cvfl_3_lp1");; /* loop on the error */
/*
* Now compare the stored register values to those that were loaded
*/
index2 = 0;
while( (load_regs[index2] == store_regs[index2]) && (index2 < 13) )
index2++; /* check reg values */
if( index2 < 13 ) { /* error if index2 < 13 */
errcnt++; /* bump the error count */
if( prt_error ) {
writes(" \n"); /* start a new print line */
writes("cycle: ");
writed( cycle );
writes(" CVFL test ");
writed( test_no );
writes(", subtest 3 - A REGISTER WAS MODIFIED\n");
print_cvfl_data(); /* print the operands */
writes("\n");
writes(" final Acc = "); /* print the information */
write32h( sgl_value_1 );
writes("\n");
writes("register ");
writed( index2 ); /* about the corrupted */
writes(" = "); /* register */
write32h( store_regs[index2] );
writes(", should be = ");
write32h( load_regs[index2] );
writes("\n");
}
if( halt_flg )
cvfl_er_halt( BAD_REG_HLT ); /* halt on the error */
if( loop_on_err ) {
force_loop = TRUE; /* set the force loop flag */
asm("brw _cvfl_3_lp1");; /* and loop on the error */
} /* end of loop on error */
} /* end of register corruption error */
} /* end of subtest 3 */
/************************************************************************
*
* SUBTEST 4 - Check for PSL corruption
*
************************************************************************/
cvfl_4()
{
force_loop = FALSE; /* clear force_loop flg */
subtest = 4;
for( index = 0; index < max_cvfl_1_index; index++ ) {
sgl_ld_acc = cvfl_1_data[index].ld; /* get value to convert */
sgl_expected = cvfl_1_data[index].exp; /* get expected */
for( status_index = 0; status_index < 3; status_index++ ) {
sgl_dummy1 = status_array[status_index];/* status = +, -, 0 */
/*
* If LOOP ON ERROR is set, this is the loop for this subtest.
* The force loop flag is set after the first error.
*/
asm("_cvfl_4_lp1:");
asm("movl _sgl_ld_acc,r4"); /* move operand to r4 */
asm("ldf r4"); /* load the operand */
asm("tstl _sgl_dummy1"); /* set the PSL status */
asm("movpsl _init_psl"); /* save the initial PSL */
asm("nop");
asm("cvfl r8"); /* convert the value */
asm("nop");
asm("movpsl _psl_val"); /* save the final PSL */
asm("nop");
asm("stf _sgl_st_acc"); /* store the result */
if( force_loop )
asm("brb _cvfl_4_lp1");; /* loop on the error */
/*
* Now compare the final PSL to the initial PSL -they should be the same
*/
asm("movl r8,_sgl_value_1"); /* save the converted int*/
exp_psl = init_psl;
exp_psl &= 0xfffffff3; /* clear ZERO, NEGATIVE */
if( !sgl_expected )
exp_psl |= PSL_Z; /* expect the ZERO bit set */
if( sgl_expected < 0 )
exp_psl |= PSL_N; /* expect the NEG bit set */
if( psl_val != exp_psl ) {
errcnt++; /* bump the error count */
if( prt_error ) {
writes(" \n"); /* start a new print line */
writes("cycle: ");
writed( cycle );
writes(" CVFL test ");
writed( test_no );
writes(", subtest 4 - INCORRECT FINAL PSL\n");
print_cvfl_data(); /* print operands */
writes("\n");
writes(" final Acc = ");
write32h( sgl_st_acc );
writes("\n");
writes("initial PSL = ");
write32h( init_psl );
writes(", final PSL = ");
write32h( psl_val );
writes(", expected PSL = ");
write32h( exp_psl );
writes("\n");
}
if( halt_flg )
cvfl_er_halt( BAD_PSL_HLT ); /* halt on error */
if( loop_on_err ) {
force_loop = TRUE; /* set force loop flag */
asm("brw _cvfl_4_lp1");;/* and loop on error */
} /* end of loop on error */
} /* end of PSL corruption error */
} /* end of status WHILE loop */
} /* end of data WHILE loop */
} /* end of subtest 4 */
/************************************************************************
*
* SUBTEST 5 - accumulator corruption
*
************************************************************************/
cvfl_5()
{
force_loop = FALSE;
subtest = 5;
for( index = 0; index < max_cvfl_1_index; index++ ) {
sgl_ld_acc = cvfl_1_data[index].ld; /* get value to convert */
if( sgl_ld_acc & 0x7f800000 )
sgl_expected = sgl_ld_acc;
else
sgl_expected = 0;
/*
* If LOOP ON ERROR is set, this is the loop for this subtest.
* The force loop flag is set after the first error.
*/
asm("_cvfl_5_lp1:");
asm("ldf _sgl_ld_acc"); /* load the base value */
asm("cvfl _sgl_value_1"); /* store the result */
asm("stf _sgl_st_acc"); /* store the result */
if( force_loop )
asm("brb _cvfl_5_lp1");; /* loop on the error */
/*
* end error loop - test the results
*/
if( sgl_st_acc != sgl_expected ) { /* COMPARE the values */
errcnt++; /* bump the error count */
if( prt_error ) {
writes(" \n"); /* start a new print line */
writes("cycle: ");
writed( cycle );
writes(" CVFL test ");
writed( test_no );
writes(", subtest 5 (Cache Data) - BAD_FINAL_ACC\n");
print_cvfl_data();
writec('\n');
writes(" final Acc = ");
write32h( sgl_value_1 );
writes(", expected Acc = ");
write32h( sgl_ld_acc );
writec('\n');
}
if( halt_flg )
cvfl_er_halt( BAD_ACC_HLT ); /* halt on the error */
if( loop_on_err ) {
force_loop = TRUE; /* set the force loop flag */
asm("brw _cvfl_1_lp1");; /* and loop on the error */
} /* end of loop on error */
} /* end of compare error */
} /* end of WHILE loop */
} /* end of subtest 5 */
/************************************************************************
*
* SUBTEST 6 - pipelined entry test
*
************************************************************************/
cvfl_6()
{
force_loop = FALSE;
subtest = 6;
for( index = 0; index < max_cvfl_1_index; index++ ) {
sgl_ld_acc = cvfl_1_data[index].ld; /* get value to convert */
if( sgl_ld_acc & 0x7f800000 )
sgl_expected = sgl_ld_acc; /* expected = loaded */
else
sgl_expected = 0; /* expect a '0' */
/*
* If LOOP ON ERROR is set, this is the loop for this subtest.
* The force loop flag is set after the first error.
*/
asm("_cvfl_6_lp1:");
asm("movl $0,r0"); /* clear r0 */
asm("ldf r0"); /* load the Acc. with 0.0 */
asm("addf _sgl_ld_acc"); /* add the base value */
asm("cvfl _sgl_value_1"); /* convert the value */
asm("stf _sgl_st_acc"); /* store the result */
if( force_loop )
asm("brb _cvfl_6_lp1");; /* loop on the error */
/*
* end error loop - test the results
*/
if( sgl_st_acc != sgl_expected ) { /* COMPARE the values */
errcnt++; /* bump the error count */
if( prt_error ) {
writes(" \n"); /* start a new print line */
writes("cycle: ");
writed( cycle );
writes(" CVFL test ");
writed( test_no );
writes(", subtest 6 (Piped Entry) - BAD_FINAL_ACC\n");
print_cvfl_data();
writec('\n');
writes(" final Acc = ");
write32h( sgl_value_1 );
writes(", expected Acc = ");
write32h( sgl_ld_acc );
writec('\n');
}
if( halt_flg )
cvfl_er_halt( BAD_ACC_HLT ); /* halt on the error */
if( loop_on_err ) {
force_loop = TRUE; /* set the force loop flag */
asm("brw _cvfl_6_lp1");; /* and loop on the error */
} /* end of loop on error */
} /* end of compare error */
} /* end of WHILE loop */
} /* end of subtest 6 */
/************************************************************************
*
* SUBTEST 7 - pipelined exit test
*
************************************************************************/
cvfl_7()
{
force_loop = FALSE;
subtest = 7;
for( index = 0; index < max_cvfl_1_index; index++ ) {
sgl_ld_acc = cvfl_1_data[index].ld; /* get value to negate */
if( sgl_ld_acc & 0x7f800000 )
sgl_expected = sgl_ld_acc; /* expected = loaded */
else
sgl_expected = 0; /* expect a '0' */
/*
* If LOOP ON ERROR is set, this is the loop for this subtest.
* The force loop flag is set after the first error.
*/
asm("_cvfl_7_lp1:");
asm("movl $0,r0"); /* clear r0 */
asm("ldf _sgl_ld_acc"); /* load the value */
asm("cvfl _sgl_value_1"); /* convert the value */
asm("addf r0"); /* add a zero to the acc */
asm("stf _sgl_st_acc"); /* store the result */
if( force_loop )
asm("brb _cvfl_7_lp1");; /* loop on the error */
/*
* end error loop - test the results
*/
if( sgl_st_acc != sgl_expected ) { /* COMPARE the values */
errcnt++; /* bump the error count */
if( prt_error ) {
writes(" \n"); /* start a new print line */
writes("cycle: ");
writed( cycle );
writes(" CVFL test ");
writed( test_no );
writes(", subtest 7 (piped exit) - BAD_FINAL_ACC\n");
print_cvfl_data();
writes(" final Acc = ");
write32h( sgl_st_acc );
writes(", expected Acc = ");
if( sgl_ld_acc & 0x7f800000 )
write32h( sgl_ld_acc );
else
write32h( 0 );
writec('\n');
}
if( halt_flg )
cvfl_er_halt( BAD_ACC_HLT ); /* halt on the error */
if( loop_on_err ) {
force_loop = TRUE; /* set the force loop flag */
asm("brw _cvfl_7_lp1");; /* and loop on the error */
} /* end of loop on error */
} /* end of compare error */
} /* end of WHILE loop */
} /* end of subtest 7 */
/**************************************************************************
*
* PRINT THE DATA AND STORE RESULTS
*
* initial Acc = xxxxxxxx, int. stored = xxxxxxxx, data index = xx
**************************************************************************/
print_cvfl_data()
{
writes("initial Acc = ");
write32h( sgl_ld_acc );
writes(", int. stored = ");
write32h( sgl_value_1 );
}
/**************************************************************************
*
* HALT ON ERROR ROUTINE
*
**************************************************************************/
cvfl_er_halt( halt_code )
int halt_code;
{
sgl_dummy1 = halt_code; /* get the error type */
asm("movl _test_no,r0"); /* r0 = test number */
asm("movl _subtest,r1"); /* r1 = subtest number */
asm("movl _sgl_dummy1,r2"); /* r2 = error code */
asm("movl _cycle,r3"); /* r3 = cycle count */
asm("movl _sgl_ld_acc,r4"); /* r4 = initial data */
asm("movl _sgl_value_1,r5"); /* r5 = final acc */
asm("movl _sgl_st_acc,r6"); /* r6 = integer stored */
if( halt_code == BAD_ACC_HLT ) {
asm("movl _sgl_ld_acc,r7"); /* r7 = expected acc */
asm("movl _index,r8"); /* r8 = data index */
} else
if( halt_code == BAD_REG_HLT ) {
sgl_dummy1 = load_regs[index2];
sgl_dummy2 = store_regs[index2];
asm("movl _index2,r7"); /* r7 = bad register # */
asm("movl _sgl_dummy2,r8"); /* r8 = final reg value */
asm("movl _sgl_dummy1,r9"); /* r9 = init reg value */
} else
if( halt_code == BAD_PSL_HLT ) {
asm("movl _init_psl,r7"); /* r7 = initial PSL */
asm("movl _psl_val,r8"); /* r8 = final PSL */
asm("movl _exp_psl,r9"); /* r9 = expected PSL */
} else
if( halt_code == BAD_STORE_HLT ) {
asm("movl _sgl_expected,r7"); /* r7 = data expectd */
asm("movl _index,r8"); /* r8 = data index */
};
asm("halt"); /* HALT ... */
}
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