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1.1 ! root 1: ! 2: #include "fpp_defs.h" ! 3: ! 4: ! 5: /***************************************************************************** ! 6: * ! 7: * CVLD - SINGLE PRECISION FLOATING POINT CONVERT LONG TO FLOAT TEST ! 8: * ! 9: *****************************************************************************/ ! 10: cvld() ! 11: { ! 12: asm(".globl _cvld_t"); ! 13: asm("_cvld_t:"); /* entry address */ ! 14: if( ( cycle ==1 ) && ( prt_hdrs ) ) /* print headers on 1st pass */ ! 15: writes(" CVLD"); ! 16: cvld_1(); /* load through a register */ ! 17: cvld_2(); /* load through the cache */ ! 18: cvld_3(); /* register stability */ ! 19: cvld_4(); /* PSL stability test */ ! 20: asm("jmp *return"); /* return to the test monitor */ ! 21: } ! 22: ! 23: ! 24: ! 25: /************************************************************************ ! 26: * ! 27: * SUBTEST 1 ! 28: * ! 29: ************************************************************************/ ! 30: cvld_1() ! 31: { ! 32: force_loop = FALSE; ! 33: subtest = 1; ! 34: index = 0; ! 35: do ! 36: { ! 37: sgl_value_2 = 0xffffffff; /* get an initial value */ ! 38: sgl_value_3 = 0xfff0fff0; /* for the accumulator */ ! 39: sgl_value_1 = cvld_1_data[index].ld; /* get the operand */ ! 40: dbl_expected = cvld_1_data[index].exp; /* get expected result */ ! 41: /* ! 42: * If LOOP ON ERROR is set, this is the loop for this subtest. ! 43: * The force loop flag is set after the first error. ! 44: */ ! 45: asm("_cvld_1_lp1:"); ! 46: asm("movl _sgl_value_2,r4"); /* move background data */ ! 47: asm("movl _sgl_value_3,r5"); ! 48: asm("movl _sgl_value_1,r6"); /* move the operand to r6 */ ! 49: asm("ldd r4"); /* load the background data */ ! 50: asm("cvld r6"); /* convert the value */ ! 51: asm("std r8"); /* store the result in R8 */ ! 52: if( force_loop ) ! 53: asm("brb _cvld_1_lp1");; /* loop on the error */ ! 54: /* ! 55: * end error loop - test the results ! 56: */ ! 57: asm("movl r8,_dbl_st_acc"); /* move MSW to cache */ ! 58: asm("movl r9,_dbl_st_acc+4"); /* move LSW to cache */ ! 59: if( ( dbl_st_acc.m != dbl_expected.m ) || /* COMPARE the values */ ! 60: ( dbl_st_acc.l != dbl_expected.l ) ){ ! 61: errcnt++; /* bump the error count */ ! 62: if( prt_error ) { ! 63: writes(" \n"); /* start a new print line */ ! 64: writes("cycle: "); ! 65: writed( cycle ); ! 66: writes(" CVLD test "); ! 67: writed( test_no ); ! 68: writes(", subtest 1 (Reg. Data) - BAD FINAL ACC\n"); ! 69: print_cvld_data(); ! 70: writes(", index = "); ! 71: writed( index ); ! 72: writec('\n'); ! 73: writes(" operand = "); ! 74: write32h( sgl_value_1 ); ! 75: writes(" expected Acc = "); ! 76: write32h( dbl_expected.m ); ! 77: writec(' '); ! 78: write32h( dbl_expected.l ); ! 79: writec('\n'); ! 80: } ! 81: if( halt_flg ) ! 82: cvld_er_halt( BAD_ACC_HLT ); /* halt on the error */ ! 83: if( loop_on_err ) { ! 84: force_loop = TRUE; /* set the force loop flag */ ! 85: asm("brw _cvld_1_lp1");; /* and loop on the error */ ! 86: } /* end of loop on error */ ! 87: } /* end of compare error */ ! 88: } while( index++ < max_cvld_1_index ); /* end of WHILE loop */ ! 89: } /* end of subtest 1 */ ! 90: ! 91: ! 92: ! 93: /************************************************************************ ! 94: * ! 95: * SUBTEST 2 - convert through memory ! 96: * ! 97: ************************************************************************/ ! 98: cvld_2() ! 99: { ! 100: force_loop = FALSE; ! 101: subtest = 2; ! 102: index = 0; ! 103: do ! 104: { ! 105: dbl_ld_acc.m = 0xffffffff; /* get an initial value */ ! 106: dbl_ld_acc.l = 0xfff0fff0; /* for the accumulator */ ! 107: sgl_value_1 = cvld_1_data[index].ld; /* get the operand */ ! 108: dbl_expected = cvld_1_data[index].exp; /* get expected result */ ! 109: /* ! 110: * If LOOP ON ERROR is set, this is the loop for this subtest. ! 111: * The force loop flag is set after the first error. ! 112: */ ! 113: asm("_cvld_2_lp1:"); ! 114: asm("ldd _dbl_ld_acc"); /* load the base value */ ! 115: asm("cvld _sgl_value_1"); /* convert the value */ ! 116: asm("std _dbl_st_acc"); /* store the result */ ! 117: if( force_loop ) ! 118: asm("brb _cvld_2_lp1");; /* loop on the error */ ! 119: /* ! 120: * end error loop - test the results ! 121: */ ! 122: if( ( dbl_st_acc.m != dbl_expected.m ) || /* COMPARE the values */ ! 123: ( dbl_st_acc.l != dbl_expected.l ) ){ ! 124: errcnt++; /* bump the error count */ ! 125: if( prt_error ) { ! 126: writes(" \n"); /* start a new print line */ ! 127: writes("cycle: "); ! 128: writed( cycle ); ! 129: writes(" CVLD test "); ! 130: writed( test_no ); ! 131: writes(", subtest 2 (Cache Data) - BAD FINAL ACC\n"); ! 132: print_cvld_data(); ! 133: writes(", index = "); ! 134: writed( index ); ! 135: writec('\n'); ! 136: writes(" operand = "); ! 137: write32h( sgl_value_1 ); ! 138: writes(" expected Acc = "); ! 139: write32h( dbl_expected.m ); ! 140: writec(' '); ! 141: write32h( dbl_expected.l ); ! 142: writec('\n'); ! 143: } ! 144: if( halt_flg ) ! 145: cvld_er_halt( BAD_ACC_HLT ); /* halt on the error */ ! 146: if( loop_on_err ) { ! 147: force_loop = TRUE; /* set the force loop flag */ ! 148: asm("brw _cvld_2_lp1");; /* and loop on the error */ ! 149: } /* end of loop on error */ ! 150: } /* end of compare error */ ! 151: } while( index++ < max_cvld_1_index ); /* end of WHILE loop */ ! 152: } /* end of subtest 2 */ ! 153: ! 154: ! 155: ! 156: /************************************************************************ ! 157: * ! 158: * SUBTEST 3 - Check for register corruption ! 159: * ! 160: ************************************************************************/ ! 161: cvld_3() ! 162: { ! 163: force_loop = FALSE; /* clear force_loop flg */ ! 164: subtest = 3; ! 165: fill_reg_buf( load_regs ); /* get patterns for regs */ ! 166: index = 0; ! 167: dbl_ld_acc.m = 0xffffffff; /* get an initial value */ ! 168: dbl_ld_acc.l = 0xfff0fff0; /* for the accumulator */ ! 169: sgl_value_1 = cvld_1_data[index].ld; /* get the operand */ ! 170: dbl_expected = cvld_1_data[index].exp; /* get expected result */ ! 171: /* ! 172: * If LOOP ON ERROR is set, this is the loop for this subtest. ! 173: * The force loop flag is set after the first error. ! 174: */ ! 175: asm("_cvld_3_lp1:"); ! 176: asm("ldd _dbl_ld_acc"); /* load base value */ ! 177: asm("loadr $0x1fff,_load_regs"); /* load regs 0 - 12 */ ! 178: asm("nop"); ! 179: asm("cvld _sgl_value_1"); /* convert the value */ ! 180: asm("nop"); ! 181: asm("storer $0x1fff,_store_regs"); /* store regs 0 - 12 */ ! 182: asm("std _dbl_st_acc"); /* save the accumulator */ ! 183: if( force_loop ) ! 184: asm("brb _cvld_3_lp1");; /* loop on the error */ ! 185: /* ! 186: * Now compare the stored register values to those that were loaded ! 187: */ ! 188: index2 = 0; ! 189: while( (load_regs[index2] == store_regs[index2]) && (index2 < 13) ) ! 190: index2++; /* check reg values */ ! 191: if( index2 < 13 ) { /* error if index2 < 13 */ ! 192: errcnt++; /* bump the error count */ ! 193: if( prt_error ) { ! 194: writes(" \n"); /* start a new print line */ ! 195: writes("cycle: "); ! 196: writed( cycle ); ! 197: writes(" CVLD test "); ! 198: writed( test_no ); ! 199: writes(", subtest 3 - A REGISTER WAS MODIFIED\n"); ! 200: print_cvld_data(); ! 201: writec('\n'); ! 202: writes(" operand = "); ! 203: write32h( sgl_value_1 ); ! 204: writec('\n'); ! 205: writes("register "); /* print the information */ ! 206: writed( index2 ); /* about the corrupted */ ! 207: writes(" = "); /* register */ ! 208: write32h( store_regs[index2] ); ! 209: writes(", should be = "); ! 210: write32h( load_regs[index2] ); ! 211: writec('\n'); ! 212: } ! 213: if( halt_flg ) ! 214: cvld_er_halt( BAD_REG_HLT ); /* halt on the error */ ! 215: if( loop_on_err ) { ! 216: force_loop = TRUE; /* set the force loop flag */ ! 217: asm("brw _cvld_3_lp1");; /* and loop on the error */ ! 218: } /* end of loop on error */ ! 219: } /* end of register corruption error */ ! 220: } /* end of subtest 3 */ ! 221: ! 222: ! 223: ! 224: /************************************************************************ ! 225: * ! 226: * SUBTEST 4 - Check for PSL corruption ! 227: * ! 228: ************************************************************************/ ! 229: cvld_4() ! 230: { ! 231: force_loop = FALSE; /* clear force_loop flg */ ! 232: subtest = 4; ! 233: fill_reg_buf( load_regs ); /* get patterns for regs */ ! 234: for( index = 0; index < 3; index++ ) { ! 235: dbl_ld_acc.m = 0xffffffff; /* get an initial value */ ! 236: dbl_ld_acc.l = 0xfff0fff0; /* for the accumulator */ ! 237: sgl_value_1 = cvld_1_data[index].ld; /* get the operand */ ! 238: dbl_expected = cvld_1_data[index].exp; /* get expected */ ! 239: sgl_dummy1 = status_array[status_index]; /* status = +, -, 0 */ ! 240: /* ! 241: * If LOOP ON ERROR is set, this is the loop for this subtest. ! 242: * The force loop flag is set after the first error. ! 243: */ ! 244: asm("_cvld_4_lp1:"); ! 245: asm("ldd _dbl_ld_acc"); /* load the base value */ ! 246: asm("tstl _sgl_dummy1"); /* set the PSL status */ ! 247: asm("movpsl _init_psl"); /* save the initial PSL */ ! 248: asm("nop"); ! 249: asm("cvld _sgl_value_1"); /* convert the value */ ! 250: asm("nop"); ! 251: asm("movpsl _psl_val"); /* save the final PSL */ ! 252: asm("std _dbl_st_acc"); /* save the accumulator */ ! 253: if( force_loop ) ! 254: asm("brb _cvld_4_lp1");; /* loop on the error */ ! 255: /* ! 256: * Now compare the final PSL to the initial PSL -they should be the same ! 257: */ ! 258: if( psl_val != init_psl ) { ! 259: errcnt++; /* bump the error count */ ! 260: if( prt_error ) { ! 261: writes(" \n"); /* start a new print line */ ! 262: writes("cycle: "); ! 263: writed( cycle ); ! 264: writes(" CVLD test "); ! 265: writed( test_no ); ! 266: writes(", subtest 4 - INCORRECT FINAL PSL\n"); ! 267: print_cvld_data(); /* print the operands */ ! 268: writec('\n'); ! 269: writes(" operand = "); ! 270: write32h( sgl_value_1 ); ! 271: writec('\n'); ! 272: writes("initial PSL = "); ! 273: write32h( init_psl ); ! 274: writes(", final PSL = "); ! 275: write32h( psl_val ); ! 276: writes(", expected PSL = "); ! 277: write32h( psl_val ); ! 278: writes("\n"); ! 279: } ! 280: if( halt_flg ) ! 281: cvld_er_halt( BAD_PSL_HLT ); /* halt on the error */ ! 282: if( loop_on_err ) { ! 283: force_loop = TRUE; /* set the force loop flag */ ! 284: asm("brw _cvld_4_lp1");; /* and loop on the error */ ! 285: } /* end of loop on error */ ! 286: } /* end of PSL corruption error */ ! 287: } /* end of WHILE loop */ ! 288: } /* end of subtest 4 */ ! 289: ! 290: ! 291: ! 292: /************************************************************************** ! 293: * ! 294: * PRINT THE DATA AND STORE RESULTS ! 295: * ! 296: * initial Acc = xxxxxxxx xxxxxxxx, final Acc = xxxxxxxx xxxxxxxx ! 297: **************************************************************************/ ! 298: print_cvld_data() ! 299: { ! 300: writes("initial Acc = "); ! 301: write32h( dbl_ld_acc.m ); ! 302: writec(' '); ! 303: write32h( dbl_ld_acc.l ); ! 304: writes(", final Acc = "); ! 305: write32h( dbl_st_acc.m ); ! 306: writec(' '); ! 307: write32h( dbl_st_acc.l ); ! 308: } ! 309: ! 310: ! 311: ! 312: /************************************************************************** ! 313: * ! 314: * HALT ON ERROR ROUTINE ! 315: * ! 316: **************************************************************************/ ! 317: cvld_er_halt( halt_code ) ! 318: int halt_code; ! 319: { ! 320: sgl_value_1 = dbl_ld_acc.m; ! 321: sgl_value_2 = dbl_ld_acc.l; ! 322: sgl_value_3 = sgl_value_1; ! 323: sgl_value_4 = dbl_st_acc.m; ! 324: sgl_value_5 = dbl_st_acc.l; ! 325: sgl_dummy1 = halt_code; /* get the error type */ ! 326: asm("movl _test_no,r0"); /* r0 = test number */ ! 327: asm("movl _subtest,r1"); /* r1 = subtest number */ ! 328: asm("movl _sgl_dummy1,r2"); /* r2 = error code */ ! 329: asm("movl _cycle,r3"); /* r3 = cycle count */ ! 330: asm("movl _sgl_value_1,r4"); /* r4 = MS operand 1 */ ! 331: asm("movl _sgl_value_2,r5"); /* r5 = LS operand 1 */ ! 332: asm("movl _sgl_value_3,r6"); /* r6 = operand 2 */ ! 333: asm("movl _sgl_value_4,r7"); /* r7 = MS stored */ ! 334: asm("movl _sgl_value_5,r8"); /* r8 = LS stored */ ! 335: if( halt_code == BAD_ACC_HLT ) { ! 336: sgl_value_1 = dbl_expected.m; ! 337: sgl_value_2 = dbl_expected.l; ! 338: asm("movl _sgl_value_1,r9"); /* r9 = MS expected */ ! 339: asm("movl _sgl_value_2,r10"); /* r10 = LS expected */ ! 340: asm("movl _index2,r11"); /* r11 = data index */ ! 341: } else ! 342: if( halt_code == BAD_REG_HLT ) { ! 343: sgl_dummy1 = load_regs[index2]; ! 344: sgl_dummy2 = store_regs[index2]; ! 345: asm("movl _index2,r9"); /* r9 = bad register # */ ! 346: asm("movl _sgl_dummy2,r10"); /* r10 = actual value */ ! 347: asm("movl _sgl_dummy1,r11"); /* r11 = expected value */ ! 348: } else ! 349: if( halt_code == BAD_PSL_HLT ) { ! 350: asm("movl _init_psl,r9"); /* r9 = initial PSL */ ! 351: asm("movl _psl_val,r10"); /* r10 = final PSL */ ! 352: asm("movl _exp_psl,r11"); /* r11 = expected PSL */ ! 353: }; ! 354: asm("halt"); /* HALT ... */ ! 355: }
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