![[BACK]](/cvsweb/icons/back.gif){kind=icon}
Return to cvld.lst CVS log ![[TXT]](/cvsweb/icons/text.gif){kind=icon}
![[DIR]](/cvsweb/icons/dir.gif){kind=icon}
Up to [Power 6/32 Unix Tahoe 4.2BSD] / cci / d / macro4|
Return to cvld.lst CVS log | Up to [Power 6/32 Unix Tahoe 4.2BSD] / cci / d / macro4 |
1.1 root 1: 1 00000000 LL0:
2: 2 00000000 .data
3: 3 00000920 * .text
4: 4 00000000 .align 1
5: 5 00000000 .globl _cvld
6: 6 00000000 _cvld:
7: 7 0001D188 0000 .word L215
8: 8 0001D18A #
9: 9 0001D18A # #include "fpp_defs.h"
10: 10 0001D18A #
11: 11 0001D18A #
12: 12 0001D18A # /*****************************************************************************
13: 13 0001D18A # *
14: 14 0001D18A # * CVLD - SINGLE PRECISION FLOATING POINT CONVERT LONG TO FLOAT TEST
15: 15 0001D18A # *
16: 16 0001D18A # *****************************************************************************/
17: 17 0001D18A # cvld()
18: 18 0001D18A # {
19: 19 0001D18A 11 41 jbr L217
20: 20 0001D18C L218:
21: 21 0001D18C # asm(".globl _cvld_t");
22: 22 0001D18C .globl _cvld_t
23: 23 0001D18C # asm("_cvld_t:"); /* entry address */
24: 24 0001D18C _cvld_t:
25: 25 0001D18C # if( ( cycle ==1 ) && ( prt_hdrs ) ) /* print headers on 1st pass */
26: 26 0001D18C 1d effffffff6 01 cmpl _cycle,$1
27: 27 0001D193 21 15 jneq L219
28: 28 0001D195 5d efffffffed tstl _prt_hdrs
29: 29 0001D19B 31 0d jeql L219
30: 30 0001D19D # writes(" CVLD");
31: 31 0001D19D .data 1
32: 32 00000920 * L221:
33: 33 00000920 * 2043564C4400 .ascii " CVLD\0"
34: 34 00000926 * .text
35: 35 0001D19D dd 8f00000920 pushl $L221
36: 36 0001D1A3 fe 08 efffffffde callf $8,_writes
37: 37 0001D1AA # cvld_1(); /* load through a register */
38: 38 0001D1AA L219:
39: 39 0001D1AA fe 04 ef0000001f callf $4,_cvld_1
40: 40 0001D1B1 # cvld_2(); /* load through the cache */
41: 41 0001D1B1 fe 04 ef000001e0 callf $4,_cvld_2
42: 42 0001D1B8 # cvld_3(); /* register stability */
43: 43 0001D1B8 fe 04 ef00000389 callf $4,_cvld_3
44: 44 0001D1BF # cvld_4(); /* PSL stability test */
45: 45 0001D1BF fe 04 ef0000057a callf $4,_cvld_4
46: 46 0001D1C6 # asm("jmp *return"); /* return to the test monitor */
47: 47 0001D1C6 71 ffffffffbc jmp *return
48: 48 0001D1CC # }
49: 49 0001D1CC 40 ret#2
50: 50 0001D1CD .set L215,0x0
51: 51 0001D1CD L217:
52: 52 0001D1CD 11 bd jbr L218
53: 53 0001D1CF .data
54: 54 00000920 * .text
55: 55 0001D1CF 00 .align 1
56: 56 0001D1D0 .globl _cvld_1
57: 57 0001D1D0 _cvld_1:
58: 58 0001D1D0 0000 .word L226
59: 59 0001D1D2 #
60: 60 0001D1D2 #
61: 61 0001D1D2 #
62: 62 0001D1D2 # /************************************************************************
63: 63 0001D1D2 # *
64: 64 0001D1D2 # * SUBTEST 1
65: 65 0001D1D2 # *
66: 66 0001D1D2 # ************************************************************************/
67: 67 0001D1D2 # cvld_1()
68: 68 0001D1D2 # {
69: 69 0001D1D2 13 01bf jbr L228
70: 70 0001D1D5 L229:
71: 71 0001D1D5 # force_loop = FALSE;
72: 72 0001D1D5 4d efffffffad clrl _force_loop
73: 73 0001D1DB # subtest = 1;
74: 74 0001D1DB 0d 01 efffffffa6 movl $1,_subtest
75: 75 0001D1E2 # index = 0;
76: 76 0001D1E2 4d efffffffa0 clrl _index
77: 77 0001D1E8 # do
78: 78 0001D1E8 L232:
79: 79 0001D1E8 # {
80: 80 0001D1E8 # sgl_value_2 = 0xffffffff; /* get an initial value */
81: 81 0001D1E8 ec 01 efffffff99 mnegl $1,_sgl_value_2
82: 82 0001D1EF # sgl_value_3 = 0xfff0fff0; /* for the accumulator */
83: 83 0001D1EF 0d 8ffff0fff0 efffffff8e movl $-983056,_sgl_value_3
84: 84 0001D1FA # sgl_value_1 = cvld_1_data[index].ld; /* get the operand */
85: 85 0001D1FA 5c 0c efffffff87 50 mull3 $12,_index,r0
86: 86 0001D202 0d e000000000 efffffff7b movl _cvld_1_data(r0),_sgl_value_1
87: 87 0001D20D # dbl_expected = cvld_1_data[index].exp; /* get expected result */
88: 88 0001D20D 5c 0c efffffff74 50 mull3 $12,_index,r0
89: 89 0001D215 0c 8f00000004 50 addl2 $_cvld_1_data+4,r0
90: 90 0001D21C 0d a004 efffffff68 movl 4(r0),_dbl_expected+4
91: 91 0001D224 0d 60 efffffff5d movl (r0),_dbl_expected
92: 92 0001D22B # /*
93: 93 0001D22B # * If LOOP ON ERROR is set, this is the loop for this subtest.
94: 94 0001D22B # * The force loop flag is set after the first error.
95: 95 0001D22B # */
96: 96 0001D22B # asm("_cvld_1_lp1:");
97: 97 0001D22B _cvld_1_lp1:
98: 98 0001D22B # asm("movl _sgl_value_2,r4"); /* move background data */
99: 99 0001D22B 0d efffffff57 54 movl _sgl_value_2,r4
100: 100 0001D232 # asm("movl _sgl_value_3,r5");
101: 101 0001D232 0d efffffff50 55 movl _sgl_value_3,r5
102: 102 0001D239 # asm("movl _sgl_value_1,r6"); /* move the operand to r6 */
103: 103 0001D239 0d efffffff49 56 movl _sgl_value_1,r6
104: 104 0001D240 # asm("ldd r4"); /* load the background data */
105: 105 0001D240 07 54 ldd r4
106: 106 0001D242 # asm("cvld r6"); /* convert the value */
107: 107 0001D242 77 56 cvld r6
108: 108 0001D244 # asm("std r8"); /* store the result in R8 */
109: 109 0001D244 27 58 std r8
110: 110 0001D246 # if( force_loop )
111: 111 0001D246 5d efffffff3c tstl _force_loop
112: 112 0001D24C 31 02 jeql L233
113: 113 0001D24E # asm("brb _cvld_1_lp1");; /* loop on the error */
114: 114 0001D24E 11 db brb _cvld_1_lp1
115: 115 0001D250 L233:
116: 116 0001D250 # /*
117: 117 0001D250 # * end error loop - test the results
118: 118 0001D250 # */
119: 119 0001D250 # asm("movl r8,_dbl_st_acc"); /* move MSW to cache */
120: 120 0001D250 0d 58 efffffff31 movl r8,_dbl_st_acc
121: 121 0001D257 # asm("movl r9,_dbl_st_acc+4"); /* move LSW to cache */
122: 122 0001D257 0d 59 efffffff2e movl r9,_dbl_st_acc+4
123: 123 0001D25E # if( ( dbl_st_acc.m != dbl_expected.m ) || /* COMPARE the values */
124: 124 0001D25E # ( dbl_st_acc.l != dbl_expected.l ) ){
125: 125 0001D25E 1d efffffff24 efffffff1f cmpl _dbl_st_acc,_dbl_expected
126: 126 0001D269 21 10 jneq L9999
127: 127 0001D26B 1d efffffff1b efffffff16 cmpl _dbl_st_acc+4,_dbl_expected+4
128: 128 0001D276 21 03 13 00ff jeql L234
129: 129 0001D27B L9999:
130: 130 0001D27B # errcnt++; /* bump the error count */
131: 131 0001D27B 6d efffffff07 incl _errcnt
132: 132 0001D281 # if( prt_error ) {
133: 133 0001D281 5d efffffff01 tstl _prt_error
134: 134 0001D287 21 03 13 00cb jeql L235
135: 135 0001D28C # writes(" \n"); /* start a new print line */
136: 136 0001D28C .data 1
137: 137 00000926 * L236:
138: 138 00000926 * 200A00 .ascii " \12\0"
139: 139 00000929 * .text
140: 140 0001D28C dd 8f00000926 pushl $L236
141: 141 0001D292 fe 08 effffffeef callf $8,_writes
142: 142 0001D299 # writes("cycle: ");
143: 143 0001D299 .data 1
144: 144 00000929 * L237:
145: 145 00000929 * 6379636C653A2000 .ascii "cycle: \0"
146: 146 00000931 * .text
147: 147 0001D299 dd 8f00000929 pushl $L237
148: 148 0001D29F fe 08 effffffee2 callf $8,_writes
149: 149 0001D2A6 # writed( cycle );
150: 150 0001D2A6 dd effffffedc pushl _cycle
151: 151 0001D2AC fe 08 effffffed5 callf $8,_writed
152: 152 0001D2B3 # writes(" CVLD test ");
153: 153 0001D2B3 .data 1
154: 154 00000931 * L239:
155: 155 00000931 * 202043564C442074657374200 .ascii " CVLD test \0"
156: 0
157: 156 0000093e * .text
158: 157 0001D2B3 dd 8f00000931 pushl $L239
159: 158 0001D2B9 fe 08 effffffec8 callf $8,_writes
160: 159 0001D2C0 # writed( test_no );
161: 160 0001D2C0 dd effffffec2 pushl _test_no
162: 161 0001D2C6 fe 08 effffffebb callf $8,_writed
163: 162 0001D2CD # writes(", subtest 1 (Reg. Data) - BAD FINAL ACC\n");
164: 163 0001D2CD .data 1
165: 164 0000093e * L240:
166: 165 0000093e * 2C20737562746573742031202 .ascii ", subtest 1 (Reg. Data) - BAD FINAL ACC\12\0"
167: 85265672E204461746129202D
168: 204241442046494E414C20414
169: 3430A00
170: 166 00000967 * .text
171: 167 0001D2CD dd 8f0000093e pushl $L240
172: 168 0001D2D3 fe 08 effffffeae callf $8,_writes
173: 169 0001D2DA # print_cvld_data();
174: 170 0001D2DA fe 04 ef00000643 callf $4,_print_cvld_data
175: 171 0001D2E1 # writes(", index = ");
176: 172 0001D2E1 .data 1
177: 173 00000967 * L242:
178: 174 00000967 * 2C202020696E646578203D200 .ascii ", index = \0"
179: 0
180: 175 00000974 * .text
181: 176 0001D2E1 dd 8f00000967 pushl $L242
182: 177 0001D2E7 fe 08 effffffe9a callf $8,_writes
183: 178 0001D2EE # writed( index );
184: 179 0001D2EE dd effffffe94 pushl _index
185: 180 0001D2F4 fe 08 effffffe8d callf $8,_writed
186: 181 0001D2FB # writec('\n');
187: 182 0001D2FB dd 0a pushl $10
188: 183 0001D2FD fe 08 effffffe84 callf $8,_writec
189: 184 0001D304 # writes(" operand = ");
190: 185 0001D304 .data 1
191: 186 00000974 * L244:
192: 187 00000974 * 202020206F706572616E64203 .ascii " operand = \0"
193: D2000
194: 188 00000983 * .text
195: 189 0001D304 dd 8f00000974 pushl $L244
196: 190 0001D30A fe 08 effffffe77 callf $8,_writes
197: 191 0001D311 # write32h( sgl_value_1 );
198: 192 0001D311 dd effffffe71 pushl _sgl_value_1
199: 193 0001D317 fe 08 effffffe6a callf $8,_write32h
200: 194 0001D31E # writes(" expected Acc = ");
201: 195 0001D31E .data 1
202: 196 00000983 * L246:
203: 197 00000983 * 2020202020202020202065787 .ascii " expected Acc = \0"
204: 0656374656420416363203D20
205: 00
206: 198 0000099d * .text
207: 199 0001D31E dd 8f00000983 pushl $L246
208: 200 0001D324 fe 08 effffffe5d callf $8,_writes
209: 201 0001D32B # write32h( dbl_expected.m );
210: 202 0001D32B dd effffffe57 pushl _dbl_expected
211: 203 0001D331 fe 08 effffffe50 callf $8,_write32h
212: 204 0001D338 # writec(' ');
213: 205 0001D338 dd 20 pushl $32
214: 206 0001D33A fe 08 effffffe47 callf $8,_writec
215: 207 0001D341 # write32h( dbl_expected.l );
216: 208 0001D341 dd effffffe45 pushl _dbl_expected+4
217: 209 0001D347 fe 08 effffffe3a callf $8,_write32h
218: 210 0001D34E # writec('\n');
219: 211 0001D34E dd 0a pushl $10
220: 212 0001D350 fe 08 effffffe31 callf $8,_writec
221: 213 0001D357 # }
222: 214 0001D357 # if( halt_flg )
223: 215 0001D357 L235:
224: 216 0001D357 5d effffffe2b tstl _halt_flg
225: 217 0001D35D 31 09 jeql L247
226: 218 0001D35F # cvld_er_halt( BAD_ACC_HLT ); /* halt on the error */
227: 219 0001D35F dd 01 pushl $1
228: 220 0001D361 fe 08 ef00000624 callf $8,_cvld_er_halt
229: 221 0001D368 # if( loop_on_err ) {
230: 222 0001D368 L247:
231: 223 0001D368 5d effffffe1a tstl _loop_on_err
232: 224 0001D36E 31 0a jeql L249
233: 225 0001D370 # force_loop = TRUE; /* set the force loop flag */
234: 226 0001D370 0d 01 effffffe11 movl $1,_force_loop
235: 227 0001D377 # asm("brw _cvld_1_lp1");; /* and loop on the error */
236: 228 0001D377 13 feb1 brw _cvld_1_lp1
237: 229 0001D37A # } /* end of loop on error */
238: 230 0001D37A # } /* end of compare error */
239: 231 0001D37A L249:
240: 232 0001D37A # } while( index++ < max_cvld_1_index ); /* end of WHILE loop */
241: 233 0001D37A L234:
242: 234 0001D37A L231:
243: 235 0001D37A 0d effffffe08 50 movl _index,r0
244: 236 0001D381 6d effffffe01 incl _index
245: 237 0001D387 1d 50 effffffdfa cmpl r0,_max_cvld_1_index
246: 238 0001D38E 81 03 13 fe55 jlss L232
247: 239 0001D393 L230:
248: 240 0001D393 # } /* end of subtest 1 */
249: 241 0001D393 40 ret#2
250: 242 0001D394 .set L226,0x0
251: 243 0001D394 L228:
252: 244 0001D394 13 fe3e jbr L229
253: 245 0001D397 .data
254: 246 00000920 * .text
255: 247 0001D397 00 .align 1
256: 248 0001D398 .globl _cvld_2
257: 249 0001D398 _cvld_2:
258: 250 0001D398 0000 .word L250
259: 251 0001D39A #
260: 252 0001D39A #
261: 253 0001D39A #
262: 254 0001D39A # /************************************************************************
263: 255 0001D39A # *
264: 256 0001D39A # * SUBTEST 2 - convert through memory
265: 257 0001D39A # *
266: 258 0001D39A # ************************************************************************/
267: 259 0001D39A # cvld_2()
268: 260 0001D39A # {
269: 261 0001D39A 13 01a8 jbr L252
270: 262 0001D39D L253:
271: 263 0001D39D # force_loop = FALSE;
272: 264 0001D39D 4d effffffde5 clrl _force_loop
273: 265 0001D3A3 # subtest = 2;
274: 266 0001D3A3 0d 02 effffffdde movl $2,_subtest
275: 267 0001D3AA # index = 0;
276: 268 0001D3AA 4d effffffdd8 clrl _index
277: 269 0001D3B0 # do
278: 270 0001D3B0 L256:
279: 271 0001D3B0 # {
280: 272 0001D3B0 # dbl_ld_acc.m = 0xffffffff; /* get an initial value */
281: 273 0001D3B0 ec 01 effffffdd1 mnegl $1,_dbl_ld_acc
282: 274 0001D3B7 # dbl_ld_acc.l = 0xfff0fff0; /* for the accumulator */
283: 275 0001D3B7 0d 8ffff0fff0 effffffdca movl $-983056,_dbl_ld_acc+4
284: 276 0001D3C2 # sgl_value_1 = cvld_1_data[index].ld; /* get the operand */
285: 277 0001D3C2 5c 0c effffffdbf 50 mull3 $12,_index,r0
286: 278 0001D3CA 0d e000000000 effffffdb3 movl _cvld_1_data(r0),_sgl_value_1
287: 279 0001D3D5 # dbl_expected = cvld_1_data[index].exp; /* get expected result */
288: 280 0001D3D5 5c 0c effffffdac 50 mull3 $12,_index,r0
289: 281 0001D3DD 0c 8f00000004 50 addl2 $_cvld_1_data+4,r0
290: 282 0001D3E4 0d a004 effffffda0 movl 4(r0),_dbl_expected+4
291: 283 0001D3EC 0d 60 effffffd95 movl (r0),_dbl_expected
292: 284 0001D3F3 # /*
293: 285 0001D3F3 # * If LOOP ON ERROR is set, this is the loop for this subtest.
294: 286 0001D3F3 # * The force loop flag is set after the first error.
295: 287 0001D3F3 # */
296: 288 0001D3F3 # asm("_cvld_2_lp1:");
297: 289 0001D3F3 _cvld_2_lp1:
298: 290 0001D3F3 # asm("ldd _dbl_ld_acc"); /* load the base value */
299: 291 0001D3F3 07 effffffd8f ldd _dbl_ld_acc
300: 292 0001D3F9 # asm("cvld _sgl_value_1"); /* convert the value */
301: 293 0001D3F9 77 effffffd89 cvld _sgl_value_1
302: 294 0001D3FF # asm("std _dbl_st_acc"); /* store the result */
303: 295 0001D3FF 27 effffffd83 std _dbl_st_acc
304: 296 0001D405 # if( force_loop )
305: 297 0001D405 5d effffffd7d tstl _force_loop
306: 298 0001D40B 31 02 jeql L257
307: 299 0001D40D # asm("brb _cvld_2_lp1");; /* loop on the error */
308: 300 0001D40D 11 e4 brb _cvld_2_lp1
309: 301 0001D40F L257:
310: 302 0001D40F # /*
311: 303 0001D40F # * end error loop - test the results
312: 304 0001D40F # */
313: 305 0001D40F # if( ( dbl_st_acc.m != dbl_expected.m ) || /* COMPARE the values */
314: 306 0001D40F # ( dbl_st_acc.l != dbl_expected.l ) ){
315: 307 0001D40F 1d effffffd73 effffffd6e cmpl _dbl_st_acc,_dbl_expected
316: 308 0001D41A 21 10 jneq L9998
317: 309 0001D41C 1d effffffd6a effffffd65 cmpl _dbl_st_acc+4,_dbl_expected+4
318: 310 0001D427 21 03 13 00ff jeql L258
319: 311 0001D42C L9998:
320: 312 0001D42C # errcnt++; /* bump the error count */
321: 313 0001D42C 6d effffffd56 incl _errcnt
322: 314 0001D432 # if( prt_error ) {
323: 315 0001D432 5d effffffd50 tstl _prt_error
324: 316 0001D438 21 03 13 00cb jeql L259
325: 317 0001D43D # writes(" \n"); /* start a new print line */
326: 318 0001D43D .data 1
327: 319 0000099d * L260:
328: 320 0000099d * 200A00 .ascii " \12\0"
329: 321 000009a0 * .text
330: 322 0001D43D dd 8f0000099d pushl $L260
331: 323 0001D443 fe 08 effffffd3e callf $8,_writes
332: 324 0001D44A # writes("cycle: ");
333: 325 0001D44A .data 1
334: 326 000009a0 * L261:
335: 327 000009a0 * 6379636C653A2000 .ascii "cycle: \0"
336: 328 000009a8 * .text
337: 329 0001D44A dd 8f000009a0 pushl $L261
338: 330 0001D450 fe 08 effffffd31 callf $8,_writes
339: 331 0001D457 # writed( cycle );
340: 332 0001D457 dd effffffd2b pushl _cycle
341: 333 0001D45D fe 08 effffffd24 callf $8,_writed
342: 334 0001D464 # writes(" CVLD test ");
343: 335 0001D464 .data 1
344: 336 000009a8 * L262:
345: 337 000009a8 * 202043564C442074657374200 .ascii " CVLD test \0"
346: 0
347: 338 000009b5 * .text
348: 339 0001D464 dd 8f000009a8 pushl $L262
349: 340 0001D46A fe 08 effffffd17 callf $8,_writes
350: 341 0001D471 # writed( test_no );
351: 342 0001D471 dd effffffd11 pushl _test_no
352: 343 0001D477 fe 08 effffffd0a callf $8,_writed
353: 344 0001D47E # writes(", subtest 2 (Cache Data) - BAD FINAL ACC\n");
354: 345 0001D47E .data 1
355: 346 000009b5 * L263:
356: 347 000009b5 * 2C20737562746573742032202 .ascii ", subtest 2 (Cache Data) - BAD FINAL ACC\12\0"
357: 8436163686520446174612920
358: 2D204241442046494E414C204
359: 143430A00
360: 348 000009df * .text
361: 349 0001D47E dd 8f000009b5 pushl $L263
362: 350 0001D484 fe 08 effffffcfd callf $8,_writes
363: 351 0001D48B # print_cvld_data();
364: 352 0001D48B fe 04 ef00000492 callf $4,_print_cvld_data
365: 353 0001D492 # writes(", index = ");
366: 354 0001D492 .data 1
367: 355 000009df * L264:
368: 356 000009df * 2C202020696E646578203D200 .ascii ", index = \0"
369: 0
370: 357 000009ec * .text
371: 358 0001D492 dd 8f000009df pushl $L264
372: 359 0001D498 fe 08 effffffce9 callf $8,_writes
373: 360 0001D49F # writed( index );
374: 361 0001D49F dd effffffce3 pushl _index
375: 362 0001D4A5 fe 08 effffffcdc callf $8,_writed
376: 363 0001D4AC # writec('\n');
377: 364 0001D4AC dd 0a pushl $10
378: 365 0001D4AE fe 08 effffffcd3 callf $8,_writec
379: 366 0001D4B5 # writes(" operand = ");
380: 367 0001D4B5 .data 1
381: 368 000009ec * L265:
382: 369 000009ec * 202020206F706572616E64203 .ascii " operand = \0"
383: D2000
384: 370 000009fb * .text
385: 371 0001D4B5 dd 8f000009ec pushl $L265
386: 372 0001D4BB fe 08 effffffcc6 callf $8,_writes
387: 373 0001D4C2 # write32h( sgl_value_1 );
388: 374 0001D4C2 dd effffffcc0 pushl _sgl_value_1
389: 375 0001D4C8 fe 08 effffffcb9 callf $8,_write32h
390: 376 0001D4CF # writes(" expected Acc = ");
391: 377 0001D4CF .data 1
392: 378 000009fb * L266:
393: 379 000009fb * 2020202020202020202065787 .ascii " expected Acc = \0"
394: 0656374656420416363203D20
395: 00
396: 380 00000a15 * .text
397: 381 0001D4CF dd 8f000009fb pushl $L266
398: 382 0001D4D5 fe 08 effffffcac callf $8,_writes
399: 383 0001D4DC # write32h( dbl_expected.m );
400: 384 0001D4DC dd effffffca6 pushl _dbl_expected
401: 385 0001D4E2 fe 08 effffffc9f callf $8,_write32h
402: 386 0001D4E9 # writec(' ');
403: 387 0001D4E9 dd 20 pushl $32
404: 388 0001D4EB fe 08 effffffc96 callf $8,_writec
405: 389 0001D4F2 # write32h( dbl_expected.l );
406: 390 0001D4F2 dd effffffc94 pushl _dbl_expected+4
407: 391 0001D4F8 fe 08 effffffc89 callf $8,_write32h
408: 392 0001D4FF # writec('\n');
409: 393 0001D4FF dd 0a pushl $10
410: 394 0001D501 fe 08 effffffc80 callf $8,_writec
411: 395 0001D508 # }
412: 396 0001D508 # if( halt_flg )
413: 397 0001D508 L259:
414: 398 0001D508 5d effffffc7a tstl _halt_flg
415: 399 0001D50E 31 09 jeql L267
416: 400 0001D510 # cvld_er_halt( BAD_ACC_HLT ); /* halt on the error */
417: 401 0001D510 dd 01 pushl $1
418: 402 0001D512 fe 08 ef00000473 callf $8,_cvld_er_halt
419: 403 0001D519 # if( loop_on_err ) {
420: 404 0001D519 L267:
421: 405 0001D519 5d effffffc69 tstl _loop_on_err
422: 406 0001D51F 31 0a jeql L268
423: 407 0001D521 # force_loop = TRUE; /* set the force loop flag */
424: 408 0001D521 0d 01 effffffc60 movl $1,_force_loop
425: 409 0001D528 # asm("brw _cvld_2_lp1");; /* and loop on the error */
426: 410 0001D528 13 fec8 brw _cvld_2_lp1
427: 411 0001D52B # } /* end of loop on error */
428: 412 0001D52B # } /* end of compare error */
429: 413 0001D52B L268:
430: 414 0001D52B # } while( index++ < max_cvld_1_index ); /* end of WHILE loop */
431: 415 0001D52B L258:
432: 416 0001D52B L255:
433: 417 0001D52B 0d effffffc57 50 movl _index,r0
434: 418 0001D532 6d effffffc50 incl _index
435: 419 0001D538 1d 50 effffffc49 cmpl r0,_max_cvld_1_index
436: 420 0001D53F 81 03 13 fe6c jlss L256
437: 421 0001D544 L254:
438: 422 0001D544 # } /* end of subtest 2 */
439: 423 0001D544 40 ret#2
440: 424 0001D545 .set L250,0x0
441: 425 0001D545 L252:
442: 426 0001D545 13 fe55 jbr L253
443: 427 0001D548 .data
444: 428 00000920 * .text
445: 429 0001D548 .align 1
446: 430 0001D548 .globl _cvld_3
447: 431 0001D548 _cvld_3:
448: 432 0001D548 0000 .word L269
449: 433 0001D54A #
450: 434 0001D54A #
451: 435 0001D54A #
452: 436 0001D54A # /************************************************************************
453: 437 0001D54A # *
454: 438 0001D54A # * SUBTEST 3 - Check for register corruption
455: 439 0001D54A # *
456: 440 0001D54A # ************************************************************************/
457: 441 0001D54A # cvld_3()
458: 442 0001D54A # {
459: 443 0001D54A 13 01f0 jbr L271
460: 444 0001D54D L272:
461: 445 0001D54D # force_loop = FALSE; /* clear force_loop flg */
462: 446 0001D54D 4d effffffc35 clrl _force_loop
463: 447 0001D553 # subtest = 3;
464: 448 0001D553 0d 03 effffffc2e movl $3,_subtest
465: 449 0001D55A # fill_reg_buf( load_regs ); /* get patterns for regs */
466: 450 0001D55A dd 8f00000000 pushl $_load_regs
467: 451 0001D560 fe 08 effffffc21 callf $8,_fill_reg_buf
468: 452 0001D567 # index = 0;
469: 453 0001D567 4d effffffc1b clrl _index
470: 454 0001D56D # dbl_ld_acc.m = 0xffffffff; /* get an initial value */
471: 455 0001D56D ec 01 effffffc14 mnegl $1,_dbl_ld_acc
472: 456 0001D574 # dbl_ld_acc.l = 0xfff0fff0; /* for the accumulator */
473: 457 0001D574 0d 8ffff0fff0 effffffc0d movl $-983056,_dbl_ld_acc+4
474: 458 0001D57F # sgl_value_1 = cvld_1_data[index].ld; /* get the operand */
475: 459 0001D57F 5c 0c effffffc02 50 mull3 $12,_index,r0
476: 460 0001D587 0d e000000000 effffffbf6 movl _cvld_1_data(r0),_sgl_value_1
477: 461 0001D592 # dbl_expected = cvld_1_data[index].exp; /* get expected result */
478: 462 0001D592 5c 0c effffffbef 50 mull3 $12,_index,r0
479: 463 0001D59A 0c 8f00000004 50 addl2 $_cvld_1_data+4,r0
480: 464 0001D5A1 0d a004 effffffbe3 movl 4(r0),_dbl_expected+4
481: 465 0001D5A9 0d 60 effffffbd8 movl (r0),_dbl_expected
482: 466 0001D5B0 # /*
483: 467 0001D5B0 # * If LOOP ON ERROR is set, this is the loop for this subtest.
484: 468 0001D5B0 # * The force loop flag is set after the first error.
485: 469 0001D5B0 # */
486: 470 0001D5B0 # asm("_cvld_3_lp1:");
487: 471 0001D5B0 _cvld_3_lp1:
488: 472 0001D5B0 # asm("ldd _dbl_ld_acc"); /* load base value */
489: 473 0001D5B0 07 effffffbd2 ldd _dbl_ld_acc
490: 474 0001D5B6 # asm("loadr $0x1fff,_load_regs"); /* load regs 0 - 12 */
491: 475 0001D5B6 ab 891fff effffffbc9 loadr $0x1fff,_load_regs
492: 476 0001D5BF # asm("nop");
493: 477 0001D5BF 10 nop
494: 478 0001D5C0 # asm("cvld _sgl_value_1"); /* convert the value */
495: 479 0001D5C0 77 effffffbc2 cvld _sgl_value_1
496: 480 0001D5C6 # asm("nop");
497: 481 0001D5C6 10 nop
498: 482 0001D5C7 # asm("storer $0x1fff,_store_regs"); /* store regs 0 - 12 */
499: 483 0001D5C7 bb 891fff effffffbb8 storer $0x1fff,_store_regs
500: 484 0001D5D0 # asm("std _dbl_st_acc"); /* save the accumulator */
501: 485 0001D5D0 27 effffffbb2 std _dbl_st_acc
502: 486 0001D5D6 # if( force_loop )
503: 487 0001D5D6 5d effffffbac tstl _force_loop
504: 488 0001D5DC 31 02 jeql L274
505: 489 0001D5DE # asm("brb _cvld_3_lp1");; /* loop on the error */
506: 490 0001D5DE 11 d0 brb _cvld_3_lp1
507: 491 0001D5E0 L274:
508: 492 0001D5E0 # /*
509: 493 0001D5E0 # * Now compare the stored register values to those that were loaded
510: 494 0001D5E0 # */
511: 495 0001D5E0 # index2 = 0;
512: 496 0001D5E0 4d effffffba2 clrl _index2
513: 497 0001D5E6 # while( (load_regs[index2] == store_regs[index2]) && (index2 < 13) )
514: 498 0001D5E6 L275:
515: 499 0001D5E6 0d effffffb9c 50 movl _index2,r0
516: 500 0001D5ED 0d effffffb95 51 movl _index2,r1
517: 501 0001D5F4 1d 40effffffb8d cmpl _load_regs[r0],_store_regs[r1]
518: 41effffffb87
519: 502 0001D601 21 11 jneq L276
520: 503 0001D603 1d effffffb7f 0d cmpl _index2,$13
521: 504 0001D60A 81 08 jgeq L276
522: 505 0001D60C # index2++; /* check reg values */
523: 506 0001D60C 6d effffffb76 incl _index2
524: 507 0001D612 11 d2 jbr L275
525: 508 0001D614 L276:
526: 509 0001D614 # if( index2 < 13 ) { /* error if index2 < 13 */
527: 510 0001D614 1d effffffb6e 0d cmpl _index2,$13
528: 511 0001D61B 91 03 13 011c jgeq L277
529: 512 0001D620 # errcnt++; /* bump the error count */
530: 513 0001D620 6d effffffb62 incl _errcnt
531: 514 0001D626 # if( prt_error ) {
532: 515 0001D626 5d effffffb5c tstl _prt_error
533: 516 0001D62C 21 03 13 00e8 jeql L278
534: 517 0001D631 # writes(" \n"); /* start a new print line */
535: 518 0001D631 .data 1
536: 519 00000a15 * L279:
537: 520 00000a15 * 200A00 .ascii " \12\0"
538: 521 00000a18 * .text
539: 522 0001D631 dd 8f00000a15 pushl $L279
540: 523 0001D637 fe 08 effffffb4a callf $8,_writes
541: 524 0001D63E # writes("cycle: ");
542: 525 0001D63E .data 1
543: 526 00000a18 * L280:
544: 527 00000a18 * 6379636C653A2000 .ascii "cycle: \0"
545: 528 00000a20 * .text
546: 529 0001D63E dd 8f00000a18 pushl $L280
547: 530 0001D644 fe 08 effffffb3d callf $8,_writes
548: 531 0001D64B # writed( cycle );
549: 532 0001D64B dd effffffb37 pushl _cycle
550: 533 0001D651 fe 08 effffffb30 callf $8,_writed
551: 534 0001D658 # writes(" CVLD test ");
552: 535 0001D658 .data 1
553: 536 00000a20 * L281:
554: 537 00000a20 * 202043564C442074657374200 .ascii " CVLD test \0"
555: 0
556: 538 00000a2d * .text
557: 539 0001D658 dd 8f00000a20 pushl $L281
558: 540 0001D65E fe 08 effffffb23 callf $8,_writes
559: 541 0001D665 # writed( test_no );
560: 542 0001D665 dd effffffb1d pushl _test_no
561: 543 0001D66B fe 08 effffffb16 callf $8,_writed
562: 544 0001D672 # writes(", subtest 3 - A REGISTER WAS MODIFIED\n");
563: 545 0001D672 .data 1
564: 546 00000a2d * L282:
565: 547 00000a2d * 2C20737562746573742033202 .ascii ", subtest 3 - A REGISTER WAS MODIFIED\12\0"
566: D204120524547495354455220
567: 574153204D4F4449464945440
568: A00
569: 548 00000a54 * .text
570: 549 0001D672 dd 8f00000a2d pushl $L282
571: 550 0001D678 fe 08 effffffb09 callf $8,_writes
572: 551 0001D67F # print_cvld_data();
573: 552 0001D67F fe 04 ef0000029e callf $4,_print_cvld_data
574: 553 0001D686 # writec('\n');
575: 554 0001D686 dd 0a pushl $10
576: 555 0001D688 fe 08 effffffaf9 callf $8,_writec
577: 556 0001D68F # writes(" operand = ");
578: 557 0001D68F .data 1
579: 558 00000a54 * L283:
580: 559 00000a54 * 202020206F706572616E64203 .ascii " operand = \0"
581: D2000
582: 560 00000a63 * .text
583: 561 0001D68F dd 8f00000a54 pushl $L283
584: 562 0001D695 fe 08 effffffaec callf $8,_writes
585: 563 0001D69C # write32h( sgl_value_1 );
586: 564 0001D69C dd effffffae6 pushl _sgl_value_1
587: 565 0001D6A2 fe 08 effffffadf callf $8,_write32h
588: 566 0001D6A9 # writec('\n');
589: 567 0001D6A9 dd 0a pushl $10
590: 568 0001D6AB fe 08 effffffad6 callf $8,_writec
591: 569 0001D6B2 # writes("register "); /* print the information */
592: 570 0001D6B2 .data 1
593: 571 00000a63 * L284:
594: 572 00000a63 * 72656769737465722000 .ascii "register \0"
595: 573 00000a6d * .text
596: 574 0001D6B2 dd 8f00000a63 pushl $L284
597: 575 0001D6B8 fe 08 effffffac9 callf $8,_writes
598: 576 0001D6BF # writed( index2 ); /* about the corrupted */
599: 577 0001D6BF dd effffffac3 pushl _index2
600: 578 0001D6C5 fe 08 effffffabc callf $8,_writed
601: 579 0001D6CC # writes(" = "); /* register */
602: 580 0001D6CC .data 1
603: 581 00000a6d * L285:
604: 582 00000a6d * 203D2000 .ascii " = \0"
605: 583 00000a71 * .text
606: 584 0001D6CC dd 8f00000a6d pushl $L285
607: 585 0001D6D2 fe 08 effffffaaf callf $8,_writes
608: 586 0001D6D9 # write32h( store_regs[index2] );
609: 587 0001D6D9 0d effffffaa9 50 movl _index2,r0
610: 588 0001D6E0 dd 40effffffaa1 pushl _store_regs[r0]
611: 589 0001D6E7 fe 08 effffffa9a callf $8,_write32h
612: 590 0001D6EE # writes(", should be = ");
613: 591 0001D6EE .data 1
614: 592 00000a71 * L286:
615: 593 00000a71 * 2C202073686F756C642062652 .ascii ", should be = \0"
616: 03D2000
617: 594 00000a81 * .text
618: 595 0001D6EE dd 8f00000a71 pushl $L286
619: 596 0001D6F4 fe 08 effffffa8d callf $8,_writes
620: 597 0001D6FB # write32h( load_regs[index2] );
621: 598 0001D6FB 0d effffffa87 50 movl _index2,r0
622: 599 0001D702 dd 40effffffa7f pushl _load_regs[r0]
623: 600 0001D709 fe 08 effffffa78 callf $8,_write32h
624: 601 0001D710 # writec('\n');
625: 602 0001D710 dd 0a pushl $10
626: 603 0001D712 fe 08 effffffa6f callf $8,_writec
627: 604 0001D719 # }
628: 605 0001D719 # if( halt_flg )
629: 606 0001D719 L278:
630: 607 0001D719 5d effffffa69 tstl _halt_flg
631: 608 0001D71F 31 09 jeql L287
632: 609 0001D721 # cvld_er_halt( BAD_REG_HLT ); /* halt on the error */
633: 610 0001D721 dd 02 pushl $2
634: 611 0001D723 fe 08 ef00000262 callf $8,_cvld_er_halt
635: 612 0001D72A # if( loop_on_err ) {
636: 613 0001D72A L287:
637: 614 0001D72A 5d effffffa58 tstl _loop_on_err
638: 615 0001D730 31 0a jeql L288
639: 616 0001D732 # force_loop = TRUE; /* set the force loop flag */
640: 617 0001D732 0d 01 effffffa4f movl $1,_force_loop
641: 618 0001D739 # asm("brw _cvld_3_lp1");; /* and loop on the error */
642: 619 0001D739 13 fe74 brw _cvld_3_lp1
643: 620 0001D73C # } /* end of loop on error */
644: 621 0001D73C # } /* end of register corruption error */
645: 622 0001D73C L288:
646: 623 0001D73C # } /* end of subtest 3 */
647: 624 0001D73C L277:
648: 625 0001D73C 40 ret#2
649: 626 0001D73D .set L269,0x0
650: 627 0001D73D L271:
651: 628 0001D73D 13 fe0d jbr L272
652: 629 0001D740 .data
653: 630 00000920 * .text
654: 631 0001D740 .align 1
655: 632 0001D740 .globl _cvld_4
656: 633 0001D740 _cvld_4:
657: 634 0001D740 0000 .word L289
658: 635 0001D742 #
659: 636 0001D742 #
660: 637 0001D742 #
661: 638 0001D742 # /************************************************************************
662: 639 0001D742 # *
663: 640 0001D742 # * SUBTEST 4 - Check for PSL corruption
664: 641 0001D742 # *
665: 642 0001D742 # ************************************************************************/
666: 643 0001D742 # cvld_4()
667: 644 0001D742 # {
668: 645 0001D742 13 01dc jbr L291
669: 646 0001D745 L292:
670: 647 0001D745 # force_loop = FALSE; /* clear force_loop flg */
671: 648 0001D745 4d effffffa3d clrl _force_loop
672: 649 0001D74B # subtest = 4;
673: 650 0001D74B 0d 04 effffffa36 movl $4,_subtest
674: 651 0001D752 # fill_reg_buf( load_regs ); /* get patterns for regs */
675: 652 0001D752 dd 8f00000000 pushl $_load_regs
676: 653 0001D758 fe 08 effffffa29 callf $8,_fill_reg_buf
677: 654 0001D75F # for( index = 0; index < 3; index++ ) {
678: 655 0001D75F 4d effffffa23 clrl _index
679: 656 0001D765 L295:
680: 657 0001D765 1d effffffa1d 03 cmpl _index,$3
681: 658 0001D76C 91 03 13 01af jgeq L294
682: 659 0001D771 # dbl_ld_acc.m = 0xffffffff; /* get an initial value */
683: 660 0001D771 ec 01 effffffa10 mnegl $1,_dbl_ld_acc
684: 661 0001D778 # dbl_ld_acc.l = 0xfff0fff0; /* for the accumulator */
685: 662 0001D778 0d 8ffff0fff0 effffffa09 movl $-983056,_dbl_ld_acc+4
686: 663 0001D783 # sgl_value_1 = cvld_1_data[index].ld; /* get the operand */
687: 664 0001D783 5c 0c effffff9fe 50 mull3 $12,_index,r0
688: 665 0001D78B 0d e000000000 effffff9f2 movl _cvld_1_data(r0),_sgl_value_1
689: 666 0001D796 # dbl_expected = cvld_1_data[index].exp; /* get expected */
690: 667 0001D796 5c 0c effffff9eb 50 mull3 $12,_index,r0
691: 668 0001D79E 0c 8f00000004 50 addl2 $_cvld_1_data+4,r0
692: 669 0001D7A5 0d a004 effffff9df movl 4(r0),_dbl_expected+4
693: 670 0001D7AD 0d 60 effffff9d4 movl (r0),_dbl_expected
694: 671 0001D7B4 # sgl_dummy1 = status_array[status_index]; /* status = +, -, 0 */
695: 672 0001D7B4 0d effffff9ce 50 movl _status_index,r0
696: 673 0001D7BB 0d 40effffff9c6 movl _status_array[r0],_sgl_dummy1
697: effffff9c1
698: 674 0001D7C7 # /*
699: 675 0001D7C7 # * If LOOP ON ERROR is set, this is the loop for this subtest.
700: 676 0001D7C7 # * The force loop flag is set after the first error.
701: 677 0001D7C7 # */
702: 678 0001D7C7 # asm("_cvld_4_lp1:");
703: 679 0001D7C7 _cvld_4_lp1:
704: 680 0001D7C7 # asm("ldd _dbl_ld_acc"); /* load the base value */
705: 681 0001D7C7 07 effffff9bb ldd _dbl_ld_acc
706: 682 0001D7CD # asm("tstl _sgl_dummy1"); /* set the PSL status */
707: 683 0001D7CD 5d effffff9b5 tstl _sgl_dummy1
708: 684 0001D7D3 # asm("movpsl _init_psl"); /* save the initial PSL */
709: 685 0001D7D3 cd effffff9af movpsl _init_psl
710: 686 0001D7D9 # asm("nop");
711: 687 0001D7D9 10 nop
712: 688 0001D7DA # asm("cvld _sgl_value_1"); /* convert the value */
713: 689 0001D7DA 77 effffff9a8 cvld _sgl_value_1
714: 690 0001D7E0 # asm("nop");
715: 691 0001D7E0 10 nop
716: 692 0001D7E1 # asm("movpsl _psl_val"); /* save the final PSL */
717: 693 0001D7E1 cd effffff9a1 movpsl _psl_val
718: 694 0001D7E7 # asm("std _dbl_st_acc"); /* save the accumulator */
719: 695 0001D7E7 27 effffff99b std _dbl_st_acc
720: 696 0001D7ED # if( force_loop )
721: 697 0001D7ED 5d effffff995 tstl _force_loop
722: 698 0001D7F3 31 02 jeql L296
723: 699 0001D7F5 # asm("brb _cvld_4_lp1");; /* loop on the error */
724: 700 0001D7F5 11 d0 brb _cvld_4_lp1
725: 701 0001D7F7 L296:
726: 702 0001D7F7 # /*
727: 703 0001D7F7 # * Now compare the final PSL to the initial PSL -they should be the same
728: 704 0001D7F7 # */
729: 705 0001D7F7 # if( psl_val != init_psl ) {
730: 706 0001D7F7 1d effffff98b effffff986 cmpl _psl_val,_init_psl
731: 707 0001D802 21 03 13 0110 jeql L297
732: 708 0001D807 # errcnt++; /* bump the error count */
733: 709 0001D807 6d effffff97b incl _errcnt
734: 710 0001D80D # if( prt_error ) {
735: 711 0001D80D 5d effffff975 tstl _prt_error
736: 712 0001D813 21 03 13 00dc jeql L298
737: 713 0001D818 # writes(" \n"); /* start a new print line */
738: 714 0001D818 .data 1
739: 715 00000a81 * L299:
740: 716 00000a81 * 200A00 .ascii " \12\0"
741: 717 00000a84 * .text
742: 718 0001D818 dd 8f00000a81 pushl $L299
743: 719 0001D81E fe 08 effffff963 callf $8,_writes
744: 720 0001D825 # writes("cycle: ");
745: 721 0001D825 .data 1
746: 722 00000a84 * L300:
747: 723 00000a84 * 6379636C653A2000 .ascii "cycle: \0"
748: 724 00000a8c * .text
749: 725 0001D825 dd 8f00000a84 pushl $L300
750: 726 0001D82B fe 08 effffff956 callf $8,_writes
751: 727 0001D832 # writed( cycle );
752: 728 0001D832 dd effffff950 pushl _cycle
753: 729 0001D838 fe 08 effffff949 callf $8,_writed
754: 730 0001D83F # writes(" CVLD test ");
755: 731 0001D83F .data 1
756: 732 00000a8c * L301:
757: 733 00000a8c * 202043564C442074657374200 .ascii " CVLD test \0"
758: 0
759: 734 00000a99 * .text
760: 735 0001D83F dd 8f00000a8c pushl $L301
761: 736 0001D845 fe 08 effffff93c callf $8,_writes
762: 737 0001D84C # writed( test_no );
763: 738 0001D84C dd effffff936 pushl _test_no
764: 739 0001D852 fe 08 effffff92f callf $8,_writed
765: 740 0001D859 # writes(", subtest 4 - INCORRECT FINAL PSL\n");
766: 741 0001D859 .data 1
767: 742 00000a99 * L302:
768: 743 00000a99 * 2C20737562746573742034202 .ascii ", subtest 4 - INCORRECT FINAL PSL\12\0"
769: D20494E434F52524543542046
770: 494E414C2050534C0A00
771: 744 00000abc * .text
772: 745 0001D859 dd 8f00000a99 pushl $L302
773: 746 0001D85F fe 08 effffff922 callf $8,_writes
774: 747 0001D866 # print_cvld_data(); /* print the operands */
775: 748 0001D866 fe 04 ef000000b7 callf $4,_print_cvld_data
776: 749 0001D86D # writec('\n');
777: 750 0001D86D dd 0a pushl $10
778: 751 0001D86F fe 08 effffff912 callf $8,_writec
779: 752 0001D876 # writes(" operand = ");
780: 753 0001D876 .data 1
781: 754 00000abc * L303:
782: 755 00000abc * 202020206F706572616E64203 .ascii " operand = \0"
783: D2000
784: 756 00000acb * .text
785: 757 0001D876 dd 8f00000abc pushl $L303
786: 758 0001D87C fe 08 effffff905 callf $8,_writes
787: 759 0001D883 # write32h( sgl_value_1 );
788: 760 0001D883 dd effffff8ff pushl _sgl_value_1
789: 761 0001D889 fe 08 effffff8f8 callf $8,_write32h
790: 762 0001D890 # writec('\n');
791: 763 0001D890 dd 0a pushl $10
792: 764 0001D892 fe 08 effffff8ef callf $8,_writec
793: 765 0001D899 # writes("initial PSL = ");
794: 766 0001D899 .data 1
795: 767 00000acb * L304:
796: 768 00000acb * 696E697469616C2050534C203 .ascii "initial PSL = \0"
797: D2000
798: 769 00000ada * .text
799: 770 0001D899 dd 8f00000acb pushl $L304
800: 771 0001D89F fe 08 effffff8e2 callf $8,_writes
801: 772 0001D8A6 # write32h( init_psl );
802: 773 0001D8A6 dd effffff8dc pushl _init_psl
803: 774 0001D8AC fe 08 effffff8d5 callf $8,_write32h
804: 775 0001D8B3 # writes(", final PSL = ");
805: 776 0001D8B3 .data 1
806: 777 00000ada * L305:
807: 778 00000ada * 2C202066696E616C2050534C2 .ascii ", final PSL = \0"
808: 03D2000
809: 779 00000aea * .text
810: 780 0001D8B3 dd 8f00000ada pushl $L305
811: 781 0001D8B9 fe 08 effffff8c8 callf $8,_writes
812: 782 0001D8C0 # write32h( psl_val );
813: 783 0001D8C0 dd effffff8c2 pushl _psl_val
814: 784 0001D8C6 fe 08 effffff8bb callf $8,_write32h
815: 785 0001D8CD # writes(", expected PSL = ");
816: 786 0001D8CD .data 1
817: 787 00000aea * L306:
818: 788 00000aea * 2C20206578706563746564205 .ascii ", expected PSL = \0"
819: 0534C203D2000
820: 789 00000afd * .text
821: 790 0001D8CD dd 8f00000aea pushl $L306
822: 791 0001D8D3 fe 08 effffff8ae callf $8,_writes
823: 792 0001D8DA # write32h( psl_val );
824: 793 0001D8DA dd effffff8a8 pushl _psl_val
825: 794 0001D8E0 fe 08 effffff8a1 callf $8,_write32h
826: 795 0001D8E7 # writes("\n");
827: 796 0001D8E7 .data 1
828: 797 00000afd * L307:
829: 798 00000afd * 0A00 .ascii "\12\0"
830: 799 00000aff * .text
831: 800 0001D8E7 dd 8f00000afd pushl $L307
832: 801 0001D8ED fe 08 effffff894 callf $8,_writes
833: 802 0001D8F4 # }
834: 803 0001D8F4 # if( halt_flg )
835: 804 0001D8F4 L298:
836: 805 0001D8F4 5d effffff88e tstl _halt_flg
837: 806 0001D8FA 31 09 jeql L308
838: 807 0001D8FC # cvld_er_halt( BAD_PSL_HLT ); /* halt on the error */
839: 808 0001D8FC dd 03 pushl $3
840: 809 0001D8FE fe 08 ef00000087 callf $8,_cvld_er_halt
841: 810 0001D905 # if( loop_on_err ) {
842: 811 0001D905 L308:
843: 812 0001D905 5d effffff87d tstl _loop_on_err
844: 813 0001D90B 31 0a jeql L309
845: 814 0001D90D # force_loop = TRUE; /* set the force loop flag */
846: 815 0001D90D 0d 01 effffff874 movl $1,_force_loop
847: 816 0001D914 # asm("brw _cvld_4_lp1");; /* and loop on the error */
848: 817 0001D914 13 feb0 brw _cvld_4_lp1
849: 818 0001D917 # } /* end of loop on error */
850: 819 0001D917 # } /* end of PSL corruption error */
851: 820 0001D917 L309:
852: 821 0001D917 # } /* end of WHILE loop */
853: 822 0001D917 L297:
854: 823 0001D917 L293:
855: 824 0001D917 6d effffff86b incl _index
856: 825 0001D91D 13 fe45 jbr L295
857: 826 0001D920 L294:
858: 827 0001D920 # } /* end of subtest 4 */
859: 828 0001D920 40 ret#2
860: 829 0001D921 .set L289,0x0
861: 830 0001D921 L291:
862: 831 0001D921 13 fe21 jbr L292
863: 832 0001D924 .data
864: 833 00000920 * .text
865: 834 0001D924 .align 1
866: 835 0001D924 .globl _print_cvld_data
867: 836 0001D924 _print_cvld_data:
868: 837 0001D924 0000 .word L310
869: 838 0001D926 #
870: 839 0001D926 #
871: 840 0001D926 #
872: 841 0001D926 # /**************************************************************************
873: 842 0001D926 # *
874: 843 0001D926 # * PRINT THE DATA AND STORE RESULTS
875: 844 0001D926 # *
876: 845 0001D926 # * initial Acc = xxxxxxxx xxxxxxxx, final Acc = xxxxxxxx xxxxxxxx
877: 846 0001D926 # **************************************************************************/
878: 847 0001D926 # print_cvld_data()
879: 848 0001D926 # {
880: 849 0001D926 11 61 jbr L312
881: 850 0001D928 L313:
882: 851 0001D928 # writes("initial Acc = ");
883: 852 0001D928 .data 1
884: 853 00000aff * L314:
885: 854 00000aff * 696E697469616C20416363203 .ascii "initial Acc = \0"
886: D2000
887: 855 00000b0e * .text
888: 856 0001D928 dd 8f00000aff pushl $L314
889: 857 0001D92E fe 08 effffff853 callf $8,_writes
890: 858 0001D935 # write32h( dbl_ld_acc.m );
891: 859 0001D935 dd effffff84d pushl _dbl_ld_acc
892: 860 0001D93B fe 08 effffff846 callf $8,_write32h
893: 861 0001D942 # writec(' ');
894: 862 0001D942 dd 20 pushl $32
895: 863 0001D944 fe 08 effffff83d callf $8,_writec
896: 864 0001D94B # write32h( dbl_ld_acc.l );
897: 865 0001D94B dd effffff83b pushl _dbl_ld_acc+4
898: 866 0001D951 fe 08 effffff830 callf $8,_write32h
899: 867 0001D958 # writes(", final Acc = ");
900: 868 0001D958 .data 1
901: 869 00000b0e * L315:
902: 870 00000b0e * 2C202066696E616C204163632 .ascii ", final Acc = \0"
903: 03D2000
904: 871 00000b1e * .text
905: 872 0001D958 dd 8f00000b0e pushl $L315
906: 873 0001D95E fe 08 effffff823 callf $8,_writes
907: 874 0001D965 # write32h( dbl_st_acc.m );
908: 875 0001D965 dd effffff81d pushl _dbl_st_acc
909: 876 0001D96B fe 08 effffff816 callf $8,_write32h
910: 877 0001D972 # writec(' ');
911: 878 0001D972 dd 20 pushl $32
912: 879 0001D974 fe 08 effffff80d callf $8,_writec
913: 880 0001D97B # write32h( dbl_st_acc.l );
914: 881 0001D97B dd effffff80b pushl _dbl_st_acc+4
915: 882 0001D981 fe 08 effffff800 callf $8,_write32h
916: 883 0001D988 # }
917: 884 0001D988 40 ret#2
918: 885 0001D989 .set L310,0x0
919: 886 0001D989 L312:
920: 887 0001D989 11 9d jbr L313
921: 888 0001D98B .data
922: 889 00000920 * .text
923: 890 0001D98B 00 .align 1
924: 891 0001D98C .globl _cvld_er_halt
925: 892 0001D98C _cvld_er_halt:
926: 893 0001D98C 0000 .word L316
927: 894 0001D98E #
928: 895 0001D98E #
929: 896 0001D98E #
930: 897 0001D98E # /**************************************************************************
931: 898 0001D98E # *
932: 899 0001D98E # * HALT ON ERROR ROUTINE
933: 900 0001D98E # *
934: 901 0001D98E # **************************************************************************/
935: 902 0001D98E # cvld_er_halt( halt_code )
936: 903 0001D98E # int halt_code;
937: 904 0001D98E # {
938: 905 0001D98E 13 0111 jbr L318
939: 906 0001D991 L319:
940: 907 0001D991 # sgl_value_1 = dbl_ld_acc.m;
941: 908 0001D991 0d effffff7f1 effffff7ec movl _dbl_ld_acc,_sgl_value_1
942: 909 0001D99C # sgl_value_2 = dbl_ld_acc.l;
943: 910 0001D99C 0d effffff7ea effffff7e1 movl _dbl_ld_acc+4,_sgl_value_2
944: 911 0001D9A7 # sgl_value_3 = sgl_value_1;
945: 912 0001D9A7 0d effffff7db effffff7d6 movl _sgl_value_1,_sgl_value_3
946: 913 0001D9B2 # sgl_value_4 = dbl_st_acc.m;
947: 914 0001D9B2 0d effffff7d0 effffff7cb movl _dbl_st_acc,_sgl_value_4
948: 915 0001D9BD # sgl_value_5 = dbl_st_acc.l;
949: 916 0001D9BD 0d effffff7c9 effffff7c0 movl _dbl_st_acc+4,_sgl_value_5
950: 917 0001D9C8 # sgl_dummy1 = halt_code; /* get the error type */
951: 918 0001D9C8 0d ad04 effffff7b8 movl 4(fp),_sgl_dummy1
952: 919 0001D9D0 # asm("movl _test_no,r0"); /* r0 = test number */
953: 920 0001D9D0 0d effffff7b2 50 movl _test_no,r0
954: 921 0001D9D7 # asm("movl _subtest,r1"); /* r1 = subtest number */
955: 922 0001D9D7 0d effffff7ab 51 movl _subtest,r1
956: 923 0001D9DE # asm("movl _sgl_dummy1,r2"); /* r2 = error code */
957: 924 0001D9DE 0d effffff7a4 52 movl _sgl_dummy1,r2
958: 925 0001D9E5 # asm("movl _cycle,r3"); /* r3 = cycle count */
959: 926 0001D9E5 0d effffff79d 53 movl _cycle,r3
960: 927 0001D9EC # asm("movl _sgl_value_1,r4"); /* r4 = MS operand 1 */
961: 928 0001D9EC 0d effffff796 54 movl _sgl_value_1,r4
962: 929 0001D9F3 # asm("movl _sgl_value_2,r5"); /* r5 = LS operand 1 */
963: 930 0001D9F3 0d effffff78f 55 movl _sgl_value_2,r5
964: 931 0001D9FA # asm("movl _sgl_value_3,r6"); /* r6 = operand 2 */
965: 932 0001D9FA 0d effffff788 56 movl _sgl_value_3,r6
966: 933 0001DA01 # asm("movl _sgl_value_4,r7"); /* r7 = MS stored */
967: 934 0001DA01 0d effffff781 57 movl _sgl_value_4,r7
968: 935 0001DA08 # asm("movl _sgl_value_5,r8"); /* r8 = LS stored */
969: 936 0001DA08 0d effffff77a 58 movl _sgl_value_5,r8
970: 937 0001DA0F # if( halt_code == BAD_ACC_HLT ) {
971: 938 0001DA0F 1d ad04 01 cmpl 4(fp),$1
972: 939 0001DA13 21 2d jneq L320
973: 940 0001DA15 # sgl_value_1 = dbl_expected.m;
974: 941 0001DA15 0d effffff76d effffff768 movl _dbl_expected,_sgl_value_1
975: 942 0001DA20 # sgl_value_2 = dbl_expected.l;
976: 943 0001DA20 0d effffff766 effffff75d movl _dbl_expected+4,_sgl_value_2
977: 944 0001DA2B # asm("movl _sgl_value_1,r9"); /* r9 = MS expected */
978: 945 0001DA2B 0d effffff757 59 movl _sgl_value_1,r9
979: 946 0001DA32 # asm("movl _sgl_value_2,r10"); /* r10 = LS expected */
980: 947 0001DA32 0d effffff750 5a movl _sgl_value_2,r10
981: 948 0001DA39 # asm("movl _index2,r11"); /* r11 = data index */
982: 949 0001DA39 0d effffff749 5b movl _index2,r11
983: 950 0001DA40 # } else
984: 951 0001DA40 11 5e jbr L321
985: 952 0001DA42 L320:
986: 953 0001DA42 # if( halt_code == BAD_REG_HLT ) {
987: 954 0001DA42 1d ad04 02 cmpl 4(fp),$2
988: 955 0001DA46 21 3d jneq L322
989: 956 0001DA48 # sgl_dummy1 = load_regs[index2];
990: 957 0001DA48 0d effffff73a 50 movl _index2,r0
991: 958 0001DA4F 0d 40effffff732 movl _load_regs[r0],_sgl_dummy1
992: effffff72d
993: 959 0001DA5B # sgl_dummy2 = store_regs[index2];
994: 960 0001DA5B 0d effffff727 50 movl _index2,r0
995: 961 0001DA62 0d 40effffff71f movl _store_regs[r0],_sgl_dummy2
996: effffff71a
997: 962 0001DA6E # asm("movl _index2,r9"); /* r9 = bad register # */
998: 963 0001DA6E 0d effffff714 59 movl _index2,r9
999: 964 0001DA75 # asm("movl _sgl_dummy2,r10"); /* r10 = actual value */
1000: 965 0001DA75 0d effffff70d 5a movl _sgl_dummy2,r10
1001: 966 0001DA7C # asm("movl _sgl_dummy1,r11"); /* r11 = expected value */
1002: 967 0001DA7C 0d effffff706 5b movl _sgl_dummy1,r11
1003: 968 0001DA83 # } else
1004: 969 0001DA83 11 1b jbr L323
1005: 970 0001DA85 L322:
1006: 971 0001DA85 # if( halt_code == BAD_PSL_HLT ) {
1007: 972 0001DA85 1d ad04 03 cmpl 4(fp),$3
1008: 973 0001DA89 21 15 jneq L324
1009: 974 0001DA8B # asm("movl _init_psl,r9"); /* r9 = initial PSL */
1010: 975 0001DA8B 0d effffff6f7 59 movl _init_psl,r9
1011: 976 0001DA92 # asm("movl _psl_val,r10"); /* r10 = final PSL */
1012: 977 0001DA92 0d effffff6f0 5a movl _psl_val,r10
1013: 978 0001DA99 # asm("movl _exp_psl,r11"); /* r11 = expected PSL */
1014: 979 0001DA99 0d effffff6e9 5b movl _exp_psl,r11
1015: 980 0001DAA0 # };
1016: 981 0001DAA0 L324:
1017: 982 0001DAA0 L323:
1018: 983 0001DAA0 L321:
1019: 984 0001DAA0 # asm("halt"); /* HALT ... */
1020: 985 0001DAA0 00 halt
1021: 986 0001DAA1 # }
1022: 987 0001DAA1 40 ret#2
1023: 988 0001DAA2 .set L316,0x0
1024: 989 0001DAA2 L318:
1025: 990 0001DAA2 13 feec jbr L319
1026: 991 0001DAA5 .data
1027: 991 0003AC2D .data
This archive runs on limited infrastructure. Preserving old code on modern bandwidth. Automated agents are requested to crawl responsibly.