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Power 6/32 Unix version 1.21
#include "fpp_defs.h"
/*****************************************************************************
*
* CVLF - SINGLE PRECISION FLOATING POINT CONVERT LONG TO FLOAT TEST
*
*****************************************************************************/
cvlf()
{
asm(".globl _cvlf_t");
asm("_cvlf_t:"); /* entry address */
if( ( cycle == 1 ) && ( prt_hdrs ) ) /* print headers on 1st pass */
writes(" CVLF");
cvlf_1(); /* load through a register */
cvlf_2(); /* load through the cache */
cvlf_3(); /* register stability */
cvlf_4(); /* PSL stability test */
cvlf_5(); /* pipelined entry test */
cvlf_6(); /* pipelined exit test */
asm("jmp *return"); /* return to the test monitor */
}
/************************************************************************
*
* SUBTEST 1 - convert through a register
*
************************************************************************/
cvlf_1()
{
force_loop = FALSE;
subtest = 1;
for( index = 0; index < max_cvlf_1_index; index++ ) {
sgl_ld_acc = 0x12345678; /* get base value */
sgl_value_1 = cvlf_1_data[index].ld; /* get value to negate */
sgl_expected = cvlf_1_data[index].exp; /* get expected result */
/*
* If LOOP ON ERROR is set, this is the loop for this subtest.
* The force loop flag is set after the first error.
*/
asm("_cvlf_1_lp1:");
asm("ldf _sgl_ld_acc");
asm("movl _sgl_value_1,r4"); /* get the value to convert */
asm("cvlf r4"); /* convert the value */
asm("stf r5"); /* store the result in R5 */
if( force_loop )
asm("brb _cvlf_1_lp1");; /* loop on the error */
/*
* end error loop - test the results
*/
asm("movl r5,_sgl_st_acc"); /* move R5 data to cache */
if( sgl_st_acc != sgl_expected ) { /* COMPARE the values */
errcnt++; /* bump the error count */
if( prt_error ) {
writes(" \n"); /* start a new print line */
writes("cycle: ");
writed( cycle );
writes(" CVLF test ");
writed( test_no );
writes(", subtest 1 (Reg. Data) - BAD FINAL ACC\n");
print_cvlf_data();
writes(", data index = ");
writed( index );
writec('\n');
writes(" operand = ");
write32h( sgl_value_1 );
writes(", expected Acc = ");
write32h( sgl_expected );
writec('\n');
}
if( halt_flg )
cvlf_er_halt( BAD_ACC_HLT ); /* halt on the error */
if( loop_on_err ) {
force_loop = TRUE; /* set the force loop flag */
asm("brw _cvlf_1_lp1");; /* and loop on the error */
} /* end of loop on error */
} /* end of compare error */
} /* end of WHILE loop */
} /* end of subtest 1 */
/************************************************************************
*
* SUBTEST 2 - convert through memory
*
************************************************************************/
cvlf_2()
{
force_loop = FALSE;
subtest = 2;
for( index = 0; index < max_cvlf_1_index; index++ ) {
sgl_ld_acc = 0x7fffffff; /* get value to negate */
sgl_value_1 = cvlf_1_data[index].ld; /* get value to negate */
sgl_expected = cvlf_1_data[index].exp; /* get expected result */
/*
* If LOOP ON ERROR is set, this is the loop for this subtest.
* The force loop flag is set after the first error.
*/
asm("_cvlf_2_lp1:");
asm("ldf _sgl_ld_acc"); /* load the base value */
asm("cvlf _sgl_value_1"); /* convert the value */
asm("stf _sgl_st_acc"); /* store the result */
if( force_loop )
asm("brb _cvlf_2_lp1");; /* loop on the error */
/*
* end error loop - test the results
*/
if( sgl_st_acc != sgl_expected ) { /* COMPARE the values */
errcnt++; /* bump the error count */
if( prt_error ) {
writes(" \n"); /* start a new print line */
writes("cycle: ");
writed( cycle );
writes(" CVLF test ");
writed( test_no );
writes(", subtest 2 (Cache Data) - BAD FINAL ACC\n");
print_cvlf_data();
writes(", data index = ");
writed( index );
writec('\n');
writes(" operand = ");
write32h( sgl_value_1 );
writes(", expected Acc = ");
write32h( sgl_expected );
writec('\n');
}
if( halt_flg )
cvlf_er_halt( BAD_ACC_HLT ); /* halt on the error */
if( loop_on_err ) {
force_loop = TRUE; /* set the force loop flag */
asm("brw _cvlf_2_lp1");; /* and loop on the error */
} /* end of loop on error */
} /* end of compare error */
} /* end of WHILE loop */
} /* end of subtest 2 */
/************************************************************************
*
* SUBTEST 3 - Check for register corruption
*
************************************************************************/
cvlf_3()
{
force_loop = FALSE; /* clear force_loop flg */
subtest = 3;
fill_reg_buf( load_regs ); /* get patterns for regs */
index = 0;
sgl_ld_acc = 0x7fffffff; /* get value to negate */
sgl_value_1 = cvlf_1_data[0].ld; /* get value to negate */
sgl_expected = cvlf_1_data[0].exp; /* get expected result */
/*
* If LOOP ON ERROR is set, this is the loop for this subtest.
* The force loop flag is set after the first error.
*/
asm("_cvlf_3_lp1:");
asm("ldf _sgl_ld_acc"); /* load base value */
asm("loadr $0x1fff,_load_regs"); /* load regs 0 - 12 */
asm("nop");
asm("cvlf _sgl_value_1"); /* convert the value */
asm("nop");
asm("storer $0x1fff,_store_regs"); /* store regs 0 - 12 */
asm("stf _sgl_st_acc"); /* save the accumulator */
if( force_loop )
asm("brb _cvlf_3_lp1");; /* loop on the error */
/*
* Now compare the stored register values to those that were loaded
*/
index2 = 0;
while( (load_regs[index2] == store_regs[index2]) && (index2 < 13) )
index2++; /* check reg values */
if( index2 < 13 ) { /* error if index2 < 13 */
errcnt++; /* bump the error count */
if( prt_error ) {
writes(" \n"); /* start a new print line */
writes("cycle: ");
writed( cycle );
writes(" CVLF test ");
writed( test_no );
writes(", subtest 3 (Reg. Corr.) - A REGISTER WAS MODIFIED\n");
print_cvlf_data();
writec('\n');
writes(" operand = ");
write32h( sgl_value_1 );
writec('\n');
writes("register "); /* print the information */
writed( index2 ); /* about the corrupted */
writes(" = "); /* register */
write32h( store_regs[index2] );
writes(", should be = ");
write32h( load_regs[index2] );
writes("\n");
}
if( halt_flg )
cvlf_er_halt( BAD_REG_HLT ); /* halt on the error */
if( loop_on_err ) {
force_loop = TRUE; /* set the force loop flag */
asm("brw _cvlf_3_lp1");; /* and loop on the error */
} /* end of loop on error */
} /* end of register corruption error */
} /* end of subtest 3 */
/************************************************************************
*
* SUBTEST 4 - Check for PSL corruption
*
************************************************************************/
cvlf_4()
{
force_loop = FALSE; /* clear force_loop flg */
subtest = 4;
for( index = 0; index < 3; index++ ) {
sgl_ld_acc = 0x7fffffff; /* get value to negate */
sgl_value_1 = cvlf_1_data[index].ld; /* get value to negate */
sgl_expected = cvlf_1_data[index].exp; /* get expected */
sgl_dummy1 = status_array[status_index]; /* status = +, -, 0 */
/*
* If LOOP ON ERROR is set, this is the loop for this subtest.
* The force loop flag is set after the first error.
*/
asm("_cvlf_4_lp1:");
asm("ldf _sgl_ld_acc"); /* load the base value */
asm("tstl _sgl_dummy1"); /* set the PSL status */
asm("movpsl _init_psl"); /* save the initial PSL */
asm("nop");
asm("cvlf _sgl_value_1"); /* convert the value */
asm("nop");
asm("movpsl _psl_val"); /* save the final PSL */
asm("stf _sgl_st_acc"); /* save the accumulator */
if( force_loop )
asm("brb _cvlf_4_lp1");; /* loop on the error */
/*
* Now compare the final PSL to the initial PSL -they should be the same
*/
exp_psl = init_psl;
if( psl_val != exp_psl ) {
errcnt++; /* bump the error count */
if( prt_error ) {
writes(" \n"); /* start a new print line */
writes("cycle: ");
writed( cycle );
writes(" CVLF test ");
writed( test_no );
writes(", subtest 4 - INCORRECT FINAL PSL\n");
print_cvlf_data();
writec('\n');
writes(" operand = ");
write32h( sgl_value_1 );
writec('\n');
writes("initial PSL = ");
write32h( init_psl );
writes(", final PSL = ");
write32h( psl_val );
writes(", expected PSL = ");
write32h( exp_psl );
writes("\n");
}
if( halt_flg )
cvlf_er_halt( BAD_PSL_HLT ); /* halt on the error */
if( loop_on_err ) {
force_loop = TRUE; /* set the force loop flag */
asm("brw _cvlf_4_lp1");; /* and loop on the error */
} /* end of loop on error */
} /* end of PSL corruption error */
} /* end of WHILE loop */
} /* end of subtest 4 */
/************************************************************************
*
* SUBTEST 5 - pipelined entry test
*
************************************************************************/
cvlf_5()
{
force_loop = FALSE;
subtest = 5;
for( index = 0; index < max_cvlf_1_index; index++ ) {
sgl_ld_acc = 0x7fffffff; /* get the base value */
sgl_value_1 = cvlf_1_data[index].ld; /* get value to negate */
sgl_expected = cvlf_1_data[index].exp; /* get expected result */
/*
* If LOOP ON ERROR is set, this is the loop for this subtest.
* The force loop flag is set after the first error.
*/
asm("_cvlf_5_lp1:");
asm("movl $0,r0"); /* clear r0 */
asm("ldf r0"); /* load the Acc. with 0.0 */
asm("addf _sgl_ld_acc"); /* add the value */
asm("stf _sgl_st_acc"); /* store the result */
asm("cvlf _sgl_value_1"); /* convert the value */
asm("stf _sgl_st_acc"); /* store the result */
if( force_loop )
asm("brb _cvlf_5_lp1");; /* loop on the error */
/*
* end error loop - test the results
*/
if( sgl_st_acc != sgl_expected ) { /* COMPARE the values */
errcnt++; /* bump the error count */
if( prt_error ) {
writes(" \n"); /* start a new print line */
writes("cycle: ");
writed( cycle );
writes(" CVLF test ");
writed( test_no );
writes(", subtest 5 (Piped Entry) - BAD FINAL ACC\n");
print_cvlf_data();
writes(", data index = ");
writed( index );
writec('\n');
writes(" operand = ");
write32h( sgl_value_1 );
writes(", expected Acc = ");
write32h( sgl_expected );
writec('\n');
}
if( halt_flg )
cvlf_er_halt( BAD_ACC_HLT ); /* halt on the error */
if( loop_on_err ) {
force_loop = TRUE; /* set the force loop flag */
asm("brw _cvlf_5_lp1");; /* and loop on the error */
} /* end of loop on error */
} /* end of compare error */
} /* end of WHILE loop */
} /* end of subtest 5 */
/************************************************************************
*
* SUBTEST 6 - pipelined exit test
*
************************************************************************/
cvlf_6()
{
force_loop = FALSE;
subtest = 6;
for( index = 0; index < max_cvlf_1_index; index++ ) {
sgl_ld_acc = cvlf_1_data[index].ld; /* get initial acc val */
sgl_expected = cvlf_1_data[index].exp; /* get expected result */
/*
* If LOOP ON ERROR is set, this is the loop for this subtest.
* The force loop flag is set after the first error.
*/
asm("_cvlf_6_lp1:");
asm("movl $0,r0"); /* clear r0 */
asm("ldf _sgl_ld_acc"); /* load the value */
asm("cvlf _sgl_ld_acc"); /* convert the value */
asm("addf r0"); /* add a zero to the acc */
asm("stf _sgl_st_acc"); /* store the result */
if( force_loop )
asm("brb _cvlf_6_lp1");; /* loop on the error */
/*
* end error loop - test the results
*/
if( sgl_st_acc != sgl_expected ) { /* COMPARE the values */
errcnt++; /* bump the error count */
if( prt_error ) {
writes(" \n"); /* start a new print line */
writes("cycle: ");
writed( cycle );
writes(" CVLF test ");
writed( test_no );
writes(", subtest 6 (Piped Exit) - BAD FINAL ACC\n");
print_cvlf_data();
writes(", data index = ");
writed( index );
writec('\n');
writes(" operand = ");
write32h( sgl_value_1 );
writes(", expected Acc = ");
write32h( sgl_expected );
writec('\n');
}
if( halt_flg )
cvlf_er_halt( BAD_ACC_HLT ); /* halt on the error */
if( loop_on_err ) {
force_loop = TRUE; /* set the force loop flag */
asm("brw _cvlf_6_lp1");; /* and loop on the error */
} /* end of loop on error */
} /* end of compare error */
} /* end of WHILE loop */
} /* end of subtest 6 */
/**************************************************************************
*
* PRINT THE DATA AND STORE RESULTS
*
* initial Acc = xxxxxxxx, stored = xxxxxxxx, data index = xx
* operand = xxxxxxxx, expected = xxxxxxxx
**************************************************************************/
print_cvlf_data()
{
writes("initial Acc = ");
write32h( sgl_ld_acc );
writes(", final Acc = ");
write32h( sgl_st_acc );
}
/**************************************************************************
*
* HALT ON ERROR ROUTINE
*
**************************************************************************/
cvlf_er_halt( halt_code )
int halt_code;
{
sgl_dummy1 = halt_code; /* get the error type */
asm("movl _test_no,r0"); /* r0 = test number */
asm("movl _subtest,r1"); /* r1 = subtest number */
asm("movl _sgl_dummy1,r2"); /* r2 = error code */
asm("movl _cycle,r3"); /* r3 = cycle count */
asm("movl _sgl_ld_acc,r4"); /* r4 = initial data */
/* asm("movl _sgl_value_1,r5"); /* r5 = data loaded */
asm("movl _sgl_st_acc,r6"); /* r6 = data stored */
if( halt_code == BAD_ACC_HLT ) {
asm("movl _sgl_expected,r7"); /* r7 = data expected */
asm("movl _index,r8"); /* r8 = data expected */
} else
if( halt_code == BAD_REG_HLT ) {
sgl_dummy1 = load_regs[index2];
sgl_dummy2 = store_regs[index2];
asm("movl _index2,r7"); /* r7 = bad register # */
asm("movl _sgl_dummy2,r8"); /* r8 = final reg value */
asm("movl _sgl_dummy1,r9"); /* r9 = init reg value */
} else
if( halt_code == BAD_PSL_HLT ) {
asm("movl _init_psl,r7"); /* r7 = initial PSL */
asm("movl _psl_val,r8"); /* r8 = final PSL */
asm("movl _exp_psl,r9"); /* r9 = expected PSL */
};
asm("halt"); /* HALT ... */
}
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