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1.1 ! root 1: ! 2: ! 3: #include "fpp_defs.h" ! 4: ! 5: ! 6: /***************************************************************************** ! 7: * ! 8: * DIVD - DOUBLE PRECISION FLOATING POINT DIVIDE TEST ! 9: * ! 10: *****************************************************************************/ ! 11: divd() ! 12: { ! 13: asm(".globl _divd_t"); ! 14: asm("_divd_t:"); /* entry address */ ! 15: if( (cycle == 1) && (prt_hdrs) ) /* print headers on 1st cycle */ ! 16: writes(" DIVD"); ! 17: divd_1(); /* div through a register */ ! 18: divd_2(); /* div through the cache */ ! 19: divd_3(); /* wait 1 NOP before storeing */ ! 20: for( nop_cnt = 3; nop_cnt > 0; nop_cnt-- ) ! 21: divd_3(nop_cnt); /* wait 6 ... 2 NOPs */ ! 22: divd_4(); /* wait 3 NOPs */ ! 23: divd_5(); /* wait 1 NOP before storing */ ! 24: divd_6(); /* register stability test */ ! 25: divd_7(); /* PSL stability test */ ! 26: asm("jmp *return"); /* return to the test monitor */ ! 27: } ! 28: ! 29: ! 30: ! 31: /************************************************************************ ! 32: * ! 33: * SUBTEST 1 - divide through a register ! 34: * ! 35: ************************************************************************/ ! 36: divd_1() ! 37: { ! 38: force_loop = FALSE; ! 39: subtest = 1; ! 40: for( index = 0; index < max_divd_1_index; index++ ) { ! 41: dbl_ld_acc = divd_1_data[index].op_1; /* get operand 1 */ ! 42: dbl_value_1 = divd_1_data[index].op_2; /* get operand 2 */ ! 43: dbl_expected = divd_1_data[index].exp; /* get expected result */ ! 44: /* ! 45: * If LOOP ON ERROR is set, this is the loop for this subtest. ! 46: * The force loop flag is set after the first error. ! 47: */ ! 48: asm("_divd_1_lp1:"); ! 49: asm("movl _dbl_ld_acc,r2"); /* move operand 1 to r2/r3 */ ! 50: asm("movl _dbl_ld_acc+4,r3"); ! 51: asm("movl _dbl_value_1,r4"); /* move operand 2 to r4/r5 */ ! 52: asm("movl _dbl_value_1+4,r5"); ! 53: asm("ldd r2"); /* load the 1st operand */ ! 54: asm("divd r4"); /* divide the 2nd operand */ ! 55: asm("std _dbl_st_acc"); /* store the result */ ! 56: if( force_loop ) ! 57: asm("brb _divd_1_lp1");; /* loop on the error */ ! 58: /* ! 59: * end error loop - test the results ! 60: */ ! 61: if( (dbl_st_acc.m != dbl_expected.m) || /* verify the results */ ! 62: (dbl_st_acc.l != dbl_expected.l) ) { ! 63: errcnt++; /* bump the error count */ ! 64: if( prt_error ) { ! 65: writes(" \n"); /* start a new print line */ ! 66: writes("cycle: "); ! 67: writed( cycle ); ! 68: writes(" DIVD test "); ! 69: writed( test_no ); ! 70: writes(", subtest 1 (Reg. Data) - BAD FINAL ACC\n"); ! 71: print_divd_data(); ! 72: } ! 73: if( halt_flg ) ! 74: divd_er_halt( BAD_ACC_HLT ); /* halt on the error */ ! 75: if( loop_on_err ) { ! 76: force_loop = TRUE; /* set the force loop flag */ ! 77: asm("brw _divd_1_lp1");; /* and loop on the error */ ! 78: } /* end of loop on error */ ! 79: } /* end of compare error */ ! 80: } /* end of WHILE loop */ ! 81: } /* end of subtest 1 */ ! 82: ! 83: ! 84: ! 85: /************************************************************************ ! 86: * ! 87: * SUBTEST 2 - divide through memory ! 88: * ! 89: ************************************************************************/ ! 90: divd_2() ! 91: { ! 92: force_loop = FALSE; ! 93: subtest = 2; ! 94: for( index = 0; index < max_divd_1_index; index++ ) { ! 95: dbl_ld_acc = divd_1_data[index].op_1; /* get operand 1 */ ! 96: dbl_value_1 = divd_1_data[index].op_2; /* get operand 2 */ ! 97: dbl_expected = divd_1_data[index].exp; /* get expected result */ ! 98: /* ! 99: * If LOOP ON ERROR is set, this is the loop for this subtest. ! 100: * The force loop flag is set after the first error. ! 101: */ ! 102: asm("_divd_2_lp1:"); ! 103: asm("ldd _dbl_ld_acc"); /* load the 1st operand */ ! 104: asm("divd _dbl_value_1"); /* divide the 2nd operand */ ! 105: asm("std _dbl_st_acc"); /* store the result */ ! 106: if( force_loop ) ! 107: asm("brb _divd_2_lp1");; /* loop on the error */ ! 108: /* ! 109: * end error loop - test the results ! 110: */ ! 111: if( (dbl_st_acc.m != dbl_expected.m) || /* verify the results */ ! 112: (dbl_st_acc.l != dbl_expected.l) ) { ! 113: errcnt++; /* bump the error count */ ! 114: if( prt_error ) { ! 115: writes(" \n"); /* start a new print line */ ! 116: writes("cycle: "); ! 117: writed( cycle ); ! 118: writes(" DIVD test "); ! 119: writed( test_no ); ! 120: writes(", subtest 2 (Cache Data) - BAD FINAL ACC\n"); ! 121: print_divd_data(); ! 122: } ! 123: if( halt_flg ) ! 124: divd_er_halt( BAD_ACC_HLT ); /* halt on the error */ ! 125: if( loop_on_err ) { ! 126: force_loop = TRUE; /* set the force loop flag */ ! 127: asm("brw _divd_2_lp1");; /* and loop on the error */ ! 128: } /* end of loop on error */ ! 129: } /* end of compare error */ ! 130: } /* end of WHILE loop */ ! 131: } /* end of subtest 2 */ ! 132: ! 133: ! 134: ! 135: /**************************************************************************** ! 136: * ! 137: * SUBTEST 3 - Wait 2n NOPs before storing the results ! 138: * ! 139: ****************************************************************************/ ! 140: divd_3( count ) ! 141: int count; /* wait "count" * 2 NOPs */ ! 142: { ! 143: force_loop = FALSE; ! 144: subtest = 3; ! 145: sgl_dummy2 = count; /* get the NOP count */ ! 146: for( index = 0; index < max_divd_1_index; index++ ) { ! 147: dbl_ld_acc = divd_1_data[index].op_1; /* get operand 1 */ ! 148: dbl_value_1 = divd_1_data[index].op_2; /* get operand 2 */ ! 149: dbl_expected = divd_1_data[index].exp; /* get expected result */ ! 150: /* ! 151: * If LOOP ON ERROR is set, this is the loop for this subtest. ! 152: * The force loop flag is set after the first error. ! 153: */ ! 154: asm("_divd_3_lp1:"); ! 155: asm("movl _sgl_dummy2,r0"); /* set the NOP count */ ! 156: asm("ldd _dbl_ld_acc"); /* load the 1st operand */ ! 157: asm("nop"); /* delay */ ! 158: asm("divd _dbl_value_1"); /* divide the 2nd operand */ ! 159: asm("1:"); ! 160: asm("decl r0"); /* decrement the NOP count */ ! 161: asm("bneq 1b"); /* till the count = 0 */ ! 162: asm("std _dbl_st_acc"); /* store the result */ ! 163: if( force_loop ) ! 164: asm("brb _divd_3_lp1");; /* loop on the error */ ! 165: /* ! 166: * end error loop - test the results ! 167: */ ! 168: if( (dbl_st_acc.m != dbl_expected.m) || /* verify the results */ ! 169: (dbl_st_acc.l != dbl_expected.l) ) { ! 170: errcnt++; /* bump the error count */ ! 171: if( prt_error ) { ! 172: writes(" \n"); /* start a new print line */ ! 173: writes("cycle: "); ! 174: writed( cycle ); ! 175: writes(" DIVD test "); ! 176: writed( test_no ); ! 177: writes(", subtest 3 (wait "); ! 178: sgl_dummy1 = 2*count; ! 179: writed( sgl_dummy1 ); /* write the NOP count */ ! 180: writes(" NOPs) - BAD FINAL ACC\n"); ! 181: print_divd_data(); ! 182: } ! 183: if( halt_flg ) ! 184: divd_er_halt( BAD_ACC_HLT ); /* halt on the error */ ! 185: if( loop_on_err ) { ! 186: force_loop = TRUE; /* set the force loop flag */ ! 187: asm("brw _divd_3_lp1");; /* and loop on the error */ ! 188: } /* end of loop on error */ ! 189: } /* end of compare error */ ! 190: } /* end of WHILE loop */ ! 191: } /* end of subtest 3 */ ! 192: ! 193: ! 194: ! 195: /************************************************************************ ! 196: * ! 197: * SUBTEST 4 - Wait 2 NOPs before storing the results ! 198: * ! 199: ************************************************************************/ ! 200: divd_4() ! 201: { ! 202: force_loop = FALSE; ! 203: subtest = 4; ! 204: for( index = 0; index < max_divd_1_index; index++ ) { ! 205: dbl_ld_acc = divd_1_data[index].op_1; /* get operand 1 */ ! 206: dbl_value_1 = divd_1_data[index].op_2; /* get operand 2 */ ! 207: dbl_expected = divd_1_data[index].exp; /* get expected result */ ! 208: /* ! 209: * If LOOP ON ERROR is set, this is the loop for this subtest. ! 210: * The force loop flag is set after the first error. ! 211: */ ! 212: asm("_divd_4_lp1:"); ! 213: asm("ldd _dbl_ld_acc"); /* load the 1st operand */ ! 214: asm("nop"); /* delay */ ! 215: asm("divd _dbl_value_1"); /* divide the 2nd operand */ ! 216: asm("nop"); /* delay before ... */ ! 217: asm("nop"); /* ... storing the result */ ! 218: asm("std _dbl_st_acc"); /* store the result */ ! 219: if( force_loop ) ! 220: asm("brb _divd_4_lp1");; /* loop on the error */ ! 221: /* ! 222: * end error loop - test the results ! 223: */ ! 224: if( (dbl_st_acc.m != dbl_expected.m) || /* verify the results */ ! 225: (dbl_st_acc.l != dbl_expected.l) ) { ! 226: errcnt++; /* bump the error count */ ! 227: if( prt_error ) { ! 228: writes(" \n"); /* start a new print line */ ! 229: writes("cycle: "); ! 230: writed( cycle ); ! 231: writes(" DIVD test "); ! 232: writed( test_no ); ! 233: writes(", subtest 4 (2 NOPs) - BAD FINAL ACC\n"); ! 234: print_divd_data(); ! 235: } ! 236: if( halt_flg ) ! 237: divd_er_halt( BAD_ACC_HLT ); /* halt on the error */ ! 238: if( loop_on_err ) { ! 239: force_loop = TRUE; /* set the force loop flag */ ! 240: asm("brw _divd_4_lp1");; /* and loop on the error */ ! 241: } /* end of loop on error */ ! 242: } /* end of compare error */ ! 243: } /* end of WHILE loop */ ! 244: } /* end of subtest 4 */ ! 245: ! 246: ! 247: ! 248: /************************************************************************ ! 249: * ! 250: * SUBTEST 5 - Wait 1 NOP before storing the results ! 251: * ! 252: ************************************************************************/ ! 253: divd_5() ! 254: { ! 255: force_loop = FALSE; ! 256: subtest = 5; ! 257: for( index = 0; index < max_divd_1_index; index++ ) { ! 258: dbl_ld_acc = divd_1_data[index].op_1; /* get operand 1 */ ! 259: dbl_value_1 = divd_1_data[index].op_2; /* get operand 2 */ ! 260: dbl_expected = divd_1_data[index].exp; /* get expected result */ ! 261: /* ! 262: * If LOOP ON ERROR is set, this is the loop for this subtest. ! 263: * The force loop flag is set after the first error. ! 264: */ ! 265: asm("_divd_5_lp1:"); ! 266: asm("ldd _dbl_ld_acc"); /* load the 1st operand */ ! 267: asm("nop"); /* delay */ ! 268: asm("divd _dbl_value_1"); /* divide the 2nd operand */ ! 269: asm("nop"); /* delay before storing */ ! 270: asm("std _dbl_st_acc"); /* store the result */ ! 271: if( force_loop ) ! 272: asm("brb _divd_5_lp1");; /* loop on the error */ ! 273: /* ! 274: * end error loop - test the results ! 275: */ ! 276: if( (dbl_st_acc.m != dbl_expected.m) || /* verify the results */ ! 277: (dbl_st_acc.l != dbl_expected.l) ) { ! 278: errcnt++; /* bump the error count */ ! 279: if( prt_error ) { ! 280: writes(" \n"); /* start a new print line */ ! 281: writes("cycle: "); ! 282: writed( cycle ); ! 283: writes(" DIVD test "); ! 284: writed( test_no ); ! 285: writes(", subtest 5 (1 NOP) - BAD FINAL ACC\n"); ! 286: print_divd_data(); ! 287: } ! 288: if( halt_flg ) ! 289: divd_er_halt( BAD_ACC_HLT ); /* halt on the error */ ! 290: if( loop_on_err ) { ! 291: force_loop = TRUE; /* set the force loop flag */ ! 292: asm("brw _divd_5_lp1");; /* and loop on the error */ ! 293: } /* end of loop on error */ ! 294: } /* end of compare error */ ! 295: } /* end of WHILE loop */ ! 296: } /* end of subtest 5 */ ! 297: ! 298: ! 299: ! 300: /************************************************************************ ! 301: * ! 302: * SUBTEST 6 - Check for register corruption ! 303: * ! 304: ************************************************************************/ ! 305: divd_6() ! 306: { ! 307: force_loop = FALSE; /* clear force_loop flg */ ! 308: subtest = 6; ! 309: fill_reg_buf( load_regs ); /* get patterns for regs */ ! 310: index = 0; ! 311: dbl_ld_acc = divd_1_data[0].op_1; /* get operand 1 */ ! 312: dbl_value_1 = divd_1_data[0].op_2; /* get operand 2 */ ! 313: dbl_expected = divd_1_data[0].exp; /* get expected result */ ! 314: /* ! 315: * If LOOP ON ERROR is set, this is the loop for this subtest. ! 316: * The force loop flag is set after the first error. ! 317: */ ! 318: asm("_divd_6_lp1:"); ! 319: asm("ldd _dbl_ld_acc"); /* LOAD the accumulator */ ! 320: asm("nop"); ! 321: asm("loadr $0x1fff,_load_regs"); /* load regs 0 - 12 */ ! 322: asm("nop"); ! 323: asm("divd _dbl_value_1"); /* do the divide */ ! 324: asm("nop"); ! 325: asm("storer $0x1fff,_store_regs"); /* store regs 0 - 12 */ ! 326: asm("std _dbl_st_acc"); /* save the accumulator */ ! 327: if( force_loop ) ! 328: asm("brb _divd_6_lp1");; /* loop on the error */ ! 329: /* ! 330: * Now compare the stored register values to those that were loaded ! 331: */ ! 332: index2 = 0; ! 333: while( (load_regs[index2] == store_regs[index2]) && (index2 < 13) ) ! 334: index2++; /* check reg values */ ! 335: if( index2 < 13 ) { /* error if index2 < 13 */ ! 336: errcnt++; /* bump the error count */ ! 337: if( prt_error ) { ! 338: writes(" \n"); /* start a new print line */ ! 339: writes("cycle: "); ! 340: writed( cycle ); ! 341: writes(" DIVD test "); ! 342: writed( test_no ); ! 343: writes(", subtest 6 - A REGISTER WAS CHANGED\n"); ! 344: print_divd_data(); /* print the operands */ ! 345: writes("register "); /* print the information */ ! 346: writed( index2 ); /* about the corrupted */ ! 347: writes(" = "); /* register */ ! 348: write32h( store_regs[index2] ); ! 349: writes(", should be = "); ! 350: write32h( load_regs[index2] ); ! 351: writes("\n"); ! 352: } ! 353: if( halt_flg ) ! 354: divd_er_halt( BAD_REG_HLT ); /* halt on the error */ ! 355: if( loop_on_err ) { ! 356: force_loop = TRUE; /* set the force loop flag */ ! 357: asm("brw _divd_6_lp1");; /* and loop on the error */ ! 358: } /* end of loop on error */ ! 359: } /* end of register corruption error */ ! 360: } /* end of subtest 6 */ ! 361: ! 362: ! 363: ! 364: /************************************************************************ ! 365: * ! 366: * SUBTEST 7 - Check for PSL corruption ! 367: * ! 368: ************************************************************************/ ! 369: divd_7() ! 370: { ! 371: force_loop = FALSE; /* clear force_loop flg */ ! 372: subtest = 7; ! 373: fill_reg_buf( load_regs ); /* get patterns for regs */ ! 374: for( index = 0; index < 3; index++ ) { ! 375: dbl_ld_acc = divd_1_data[index].op_1; /* get operand 1 */ ! 376: dbl_value_1 = divd_1_data[index].op_2; /* get operand 2 */ ! 377: dbl_expected = divd_1_data[index].exp; /* get expected */ ! 378: sgl_dummy1 = status_array[status_index]; /* status = +, -, 0 */ ! 379: /* ! 380: * If LOOP ON ERROR is set, this is the loop for this subtest. ! 381: * The force loop flag is set after the first error. ! 382: */ ! 383: asm("_divd_7_lp1:"); ! 384: asm("ldd _dbl_ld_acc"); /* LOAD the accumulator */ ! 385: asm("nop"); ! 386: asm("tstl _sgl_dummy1"); /* set the PSL status */ ! 387: asm("movpsl _init_psl"); /* save the initial PSL */ ! 388: asm("divd _dbl_value_1"); /* do the divide */ ! 389: asm("nop"); ! 390: asm("movpsl _psl_val"); /* save the final PSL */ ! 391: asm("std _dbl_st_acc"); /* save the accumulator */ ! 392: if( force_loop ) ! 393: asm("brb _divd_7_lp1");; /* loop on the error */ ! 394: /* ! 395: * Now compare the final PSL to the initial PSL -they should be the same ! 396: */ ! 397: exp_psl = init_psl; ! 398: if( psl_val != exp_psl ) { ! 399: errcnt++; /* bump the error count */ ! 400: if( prt_error ) { ! 401: writes(" \n"); /* start a new print line */ ! 402: writes("cycle: "); ! 403: writed( cycle ); ! 404: writes(" DIVD test "); ! 405: writed( test_no ); ! 406: writes(", subtest 7 - INCORRECT FINAL PSL\n"); ! 407: print_divd_data(); /* print the operands */ ! 408: writes("initial PSL = "); ! 409: write32h( init_psl ); ! 410: writes(", final PSL = "); ! 411: write32h( psl_val ); ! 412: writes(", expected PSL = "); ! 413: write32h( exp_psl ); ! 414: writes("\n"); ! 415: } ! 416: if( halt_flg ) ! 417: divd_er_halt( BAD_PSL_HLT ); /* halt on the error */ ! 418: if( loop_on_err ) { ! 419: force_loop = TRUE; /* set the force loop flag */ ! 420: asm("brw _divd_7_lp1");; /* and loop on the error */ ! 421: } /* end of loop on error */ ! 422: } /* end of PSL corruption error */ ! 423: } /* end of WHILE loop */ ! 424: } /* end of subtest 7 */ ! 425: ! 426: ! 427: ! 428: /************************************************************************** ! 429: * ! 430: * PRINT THE DATA AND STORE RESULTS ! 431: * ! 432: * initial Acc = xxxxxxxx xxxxxxxx, stored = xxxxxxxx xxxxxxxx, index = xx ! 433: * operand = xxxxxxxx xxxxxxxx, expected = xxxxxxxx xxxxxxxx ! 434: **************************************************************************/ ! 435: print_divd_data() ! 436: { ! 437: writes("initial Acc = "); ! 438: write32h( dbl_ld_acc.m ); ! 439: writec(' '); ! 440: write32h( dbl_ld_acc.l ); ! 441: writes(", stored = "); ! 442: write32h( dbl_st_acc.m ); ! 443: writec(' '); ! 444: write32h( dbl_st_acc.l ); ! 445: writes(", index = "); ! 446: writed( index ); ! 447: writec('\n'); ! 448: writes(" operand = "); ! 449: write32h( dbl_value_1.m ); ! 450: writec(' '); ! 451: write32h( dbl_value_1.l ); ! 452: writes(", expected = "); ! 453: write32h( dbl_expected.m ); ! 454: writec(' '); ! 455: write32h( dbl_expected.l ); ! 456: writec('\n'); ! 457: } ! 458: ! 459: ! 460: ! 461: /************************************************************************** ! 462: * ! 463: * HALT ON ERROR ROUTINE ! 464: * ! 465: **************************************************************************/ ! 466: divd_er_halt( halt_code ) ! 467: int halt_code; ! 468: { ! 469: sgl_value_1 = dbl_ld_acc.m; ! 470: sgl_value_2 = dbl_ld_acc.l; ! 471: sgl_value_3 = dbl_value_1.m; ! 472: sgl_value_4 = dbl_value_1.l; ! 473: sgl_value_5 = dbl_st_acc.m; ! 474: sgl_value_6 = dbl_st_acc.l; ! 475: sgl_dummy1 = halt_code; /* get the error type */ ! 476: asm("movl _test_no,r0"); /* r0 = test number */ ! 477: asm("movl _subtest,r1"); /* r1 = subtest number */ ! 478: asm("movl _sgl_dummy1,r2"); /* r2 = error code */ ! 479: asm("movl _cycle,r3"); /* r3 = cycle count */ ! 480: asm("movl _sgl_value_1,r4"); /* r4 = MS operand 1 */ ! 481: asm("movl _sgl_value_2,r5"); /* r5 = LS operand 1 */ ! 482: asm("movl _sgl_value_3,r6"); /* r6 = MS operand 2 */ ! 483: asm("movl _sgl_value_4,r7"); /* r7 = LS operand 2 */ ! 484: asm("movl _sgl_value_5,r8"); /* r8 = MS stored */ ! 485: asm("movl _sgl_value_6,r9"); /* r9 = LS stored */ ! 486: if( halt_code == BAD_ACC_HLT ) { ! 487: sgl_value_1 = dbl_expected.m; ! 488: sgl_value_2 = dbl_expected.l; ! 489: asm("movl _sgl_value_1,r10"); /* r10 = MS expected */ ! 490: asm("movl _sgl_value_2,r11"); /* r11 = LS expected */ ! 491: asm("movl _index2,r12"); /* r12 = data index */ ! 492: } else ! 493: if( halt_code == BAD_REG_HLT ) { ! 494: sgl_dummy1 = load_regs[index2]; ! 495: sgl_dummy2 = store_regs[index2]; ! 496: asm("movl _index2,r10"); /* r10 = bad register # */ ! 497: asm("movl _sgl_dummy2,r11"); /* r11 = actual value */ ! 498: asm("movl _sgl_dummy1,r12"); /* r12 = expected value */ ! 499: } else ! 500: if( halt_code == BAD_PSL_HLT ) { ! 501: asm("movl _init_psl,r10"); /* r10 = initial PSL */ ! 502: asm("movl _psl_val,r11"); /* r11 = final PSL */ ! 503: asm("movl _exp_psl,r12"); /* r12 = expected PSL */ ! 504: }; ! 505: asm("halt"); /* HALT ... */ ! 506: }
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