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1.1 root 1: 1 00000000 LL0:
2: 2 00000000 .data
3: 3 00000d28 * .text
4: 4 00000000 .align 1
5: 5 00000000 .globl _divd
6: 6 00000000 _divd:
7: 7 00018FD8 0000 .word L215
8: 8 00018FDA #
9: 9 00018FDA #
10: 10 00018FDA # #include "fpp_defs.h"
11: 11 00018FDA #
12: 12 00018FDA #
13: 13 00018FDA # /*****************************************************************************
14: 14 00018FDA # *
15: 15 00018FDA # * DIVD - DOUBLE PRECISION FLOATING POINT DIVIDE TEST
16: 16 00018FDA # *
17: 17 00018FDA # *****************************************************************************/
18: 18 00018FDA # divd()
19: 19 00018FDA # {
20: 20 00018FDA 11 7a jbr L217
21: 21 00018FDC L218:
22: 22 00018FDC # asm(".globl _divd_t");
23: 23 00018FDC .globl _divd_t
24: 24 00018FDC # asm("_divd_t:"); /* entry address */
25: 25 00018FDC _divd_t:
26: 26 00018FDC # if( (cycle == 1) && (prt_hdrs) ) /* print headers on 1st cycle */
27: 27 00018FDC 1d effffffff6 01 cmpl _cycle,$1
28: 28 00018FE3 21 15 jneq L219
29: 29 00018FE5 5d efffffffed tstl _prt_hdrs
30: 30 00018FEB 31 0d jeql L219
31: 31 00018FED # writes(" DIVD");
32: 32 00018FED .data 1
33: 33 00000d28 * L221:
34: 34 00000d28 * 204449564400 .ascii " DIVD\0"
35: 35 00000d2e * .text
36: 36 00018FED dd 8f00000d28 pushl $L221
37: 37 00018FF3 fe 08 efffffffde callf $8,_writes
38: 38 00018FFA # divd_1(); /* div through a register */
39: 39 00018FFA L219:
40: 40 00018FFA fe 04 ef00000057 callf $4,_divd_1
41: 41 00019001 # divd_2(); /* div through the cache */
42: 42 00019001 fe 04 ef000001b2 callf $4,_divd_2
43: 43 00019008 # divd_3(); /* wait 1 NOP before storeing */
44: 44 00019008 fe 04 ef000002f9 callf $4,_divd_3
45: 45 0001900F # for( nop_cnt = 3; nop_cnt > 0; nop_cnt-- )
46: 46 0001900F 0d 03 efffffffc2 movl $3,_nop_cnt
47: 47 00019016 L227:
48: 48 00019016 5d efffffffbc tstl _nop_cnt
49: 49 0001901C 51 15 jleq L226
50: 50 0001901E # divd_3(nop_cnt); /* wait 6 ... 2 NOPs */
51: 51 0001901E dd efffffffb4 pushl _nop_cnt
52: 52 00019024 fe 08 ef000002dd callf $8,_divd_3
53: 53 0001902B L225:
54: 54 0001902B 7d efffffffa7 decl _nop_cnt
55: 55 00019031 11 e3 jbr L227
56: 56 00019033 L226:
57: 57 00019033 # divd_4(); /* wait 3 NOPs */
58: 58 00019033 fe 04 ef00000456 callf $4,_divd_4
59: 59 0001903A # divd_5(); /* wait 1 NOP before storing */
60: 60 0001903A fe 04 ef000005a1 callf $4,_divd_5
61: 61 00019041 # divd_6(); /* register stability test */
62: 62 00019041 fe 04 ef000006ea callf $4,_divd_6
63: 63 00019048 # divd_7(); /* PSL stability test */
64: 64 00019048 fe 04 ef000008b3 callf $4,_divd_7
65: 65 0001904F # asm("jmp *return"); /* return to the test monitor */
66: 66 0001904F 71 ffffffff83 jmp *return
67: 67 00019055 # }
68: 68 00019055 40 ret#2
69: 69 00019056 .set L215,0x0
70: 70 00019056 L217:
71: 71 00019056 11 84 jbr L218
72: 72 00019058 .data
73: 73 00000d28 * .text
74: 74 00019058 .align 1
75: 75 00019058 .globl _divd_1
76: 76 00019058 _divd_1:
77: 77 00019058 0000 .word L232
78: 78 0001905A #
79: 79 0001905A #
80: 80 0001905A #
81: 81 0001905A # /************************************************************************
82: 82 0001905A # *
83: 83 0001905A # * SUBTEST 1 - divide through a register
84: 84 0001905A # *
85: 85 0001905A # ************************************************************************/
86: 86 0001905A # divd_1()
87: 87 0001905A # {
88: 88 0001905A 13 015a jbr L234
89: 89 0001905D L235:
90: 90 0001905D # force_loop = FALSE;
91: 91 0001905D 4d efffffff75 clrl _force_loop
92: 92 00019063 # subtest = 1;
93: 93 00019063 0d 01 efffffff6e movl $1,_subtest
94: 94 0001906A # for( index = 0; index < max_divd_1_index; index++ ) {
95: 95 0001906A 4d efffffff68 clrl _index
96: 96 00019070 L238:
97: 97 00019070 1d efffffff62 efffffff5d cmpl _index,_max_divd_1_index
98: 98 0001907B 91 03 13 0136 jgeq L237
99: 99 00019080 # dbl_ld_acc = divd_1_data[index].op_1; /* get operand 1 */
100: 100 00019080 5c 18 efffffff51 50 mull3 $24,_index,r0
101: 101 00019088 0c 8f00000000 50 addl2 $_divd_1_data,r0
102: 102 0001908F 0d a004 efffffff45 movl 4(r0),_dbl_ld_acc+4
103: 103 00019097 0d 60 efffffff3a movl (r0),_dbl_ld_acc
104: 104 0001909E # dbl_value_1 = divd_1_data[index].op_2; /* get operand 2 */
105: 105 0001909E 5c 18 efffffff33 50 mull3 $24,_index,r0
106: 106 000190A6 0c 8f00000008 50 addl2 $_divd_1_data+8,r0
107: 107 000190AD 0d a004 efffffff27 movl 4(r0),_dbl_value_1+4
108: 108 000190B5 0d 60 efffffff1c movl (r0),_dbl_value_1
109: 109 000190BC # dbl_expected = divd_1_data[index].exp; /* get expected result */
110: 110 000190BC 5c 18 efffffff15 50 mull3 $24,_index,r0
111: 111 000190C4 0c 8f00000010 50 addl2 $_divd_1_data+16,r0
112: 112 000190CB 0d a004 efffffff09 movl 4(r0),_dbl_expected+4
113: 113 000190D3 0d 60 effffffefe movl (r0),_dbl_expected
114: 114 000190DA # /*
115: 115 000190DA # * If LOOP ON ERROR is set, this is the loop for this subtest.
116: 116 000190DA # * The force loop flag is set after the first error.
117: 117 000190DA # */
118: 118 000190DA # asm("_divd_1_lp1:");
119: 119 000190DA _divd_1_lp1:
120: 120 000190DA # asm("movl _dbl_ld_acc,r2"); /* move operand 1 to r2/r3 */
121: 121 000190DA 0d effffffef8 52 movl _dbl_ld_acc,r2
122: 122 000190E1 # asm("movl _dbl_ld_acc+4,r3");
123: 123 000190E1 0d effffffef5 53 movl _dbl_ld_acc+4,r3
124: 124 000190E8 # asm("movl _dbl_value_1,r4"); /* move operand 2 to r4/r5 */
125: 125 000190E8 0d effffffeea 54 movl _dbl_value_1,r4
126: 126 000190EF # asm("movl _dbl_value_1+4,r5");
127: 127 000190EF 0d effffffee7 55 movl _dbl_value_1+4,r5
128: 128 000190F6 # asm("ldd r2"); /* load the 1st operand */
129: 129 000190F6 07 52 ldd r2
130: 130 000190F8 # asm("divd r4"); /* divide the 2nd operand */
131: 131 000190F8 f7 54 divd r4
132: 132 000190FA # asm("std _dbl_st_acc"); /* store the result */
133: 133 000190FA 27 effffffed8 std _dbl_st_acc
134: 134 00019100 # if( force_loop )
135: 135 00019100 5d effffffed2 tstl _force_loop
136: 136 00019106 31 02 jeql L239
137: 137 00019108 # asm("brb _divd_1_lp1");; /* loop on the error */
138: 138 00019108 11 d0 brb _divd_1_lp1
139: 139 0001910A L239:
140: 140 0001910A # /*
141: 141 0001910A # * end error loop - test the results
142: 142 0001910A # */
143: 143 0001910A # if( (dbl_st_acc.m != dbl_expected.m) || /* verify the results */
144: 144 0001910A # (dbl_st_acc.l != dbl_expected.l) ) {
145: 145 0001910A 1d effffffec8 effffffec3 cmpl _dbl_st_acc,_dbl_expected
146: 146 00019115 21 10 jneq L9999
147: 147 00019117 1d effffffebf effffffeba cmpl _dbl_st_acc+4,_dbl_expected+4
148: 148 00019122 21 03 13 0086 jeql L240
149: 149 00019127 L9999:
150: 150 00019127 # errcnt++; /* bump the error count */
151: 151 00019127 6d effffffeab incl _errcnt
152: 152 0001912D # if( prt_error ) {
153: 153 0001912D 5d effffffea5 tstl _prt_error
154: 154 00019133 31 55 jeql L241
155: 155 00019135 # writes(" \n"); /* start a new print line */
156: 156 00019135 .data 1
157: 157 00000d2e * L242:
158: 158 00000d2e * 200A00 .ascii " \12\0"
159: 159 00000d31 * .text
160: 160 00019135 dd 8f00000d2e pushl $L242
161: 161 0001913B fe 08 effffffe96 callf $8,_writes
162: 162 00019142 # writes("cycle: ");
163: 163 00019142 .data 1
164: 164 00000d31 * L243:
165: 165 00000d31 * 6379636C653A2000 .ascii "cycle: \0"
166: 166 00000d39 * .text
167: 167 00019142 dd 8f00000d31 pushl $L243
168: 168 00019148 fe 08 effffffe89 callf $8,_writes
169: 169 0001914F # writed( cycle );
170: 170 0001914F dd effffffe83 pushl _cycle
171: 171 00019155 fe 08 effffffe7c callf $8,_writed
172: 172 0001915C # writes(" DIVD test ");
173: 173 0001915C .data 1
174: 174 00000d39 * L245:
175: 175 00000d39 * 2020444956442074657374200 .ascii " DIVD test \0"
176: 0
177: 176 00000d46 * .text
178: 177 0001915C dd 8f00000d39 pushl $L245
179: 178 00019162 fe 08 effffffe6f callf $8,_writes
180: 179 00019169 # writed( test_no );
181: 180 00019169 dd effffffe69 pushl _test_no
182: 181 0001916F fe 08 effffffe62 callf $8,_writed
183: 182 00019176 # writes(", subtest 1 (Reg. Data) - BAD FINAL ACC\n");
184: 183 00019176 .data 1
185: 184 00000d46 * L246:
186: 185 00000d46 * 2C20737562746573742031202 .ascii ", subtest 1 (Reg. Data) - BAD FINAL ACC\12\0"
187: 85265672E204461746129202D
188: 204241442046494E414C20414
189: 3430A00
190: 186 00000d6f * .text
191: 187 00019176 dd 8f00000d46 pushl $L246
192: 188 0001917C fe 08 effffffe55 callf $8,_writes
193: 189 00019183 # print_divd_data();
194: 190 00019183 fe 04 ef00000952 callf $4,_print_divd_data
195: 191 0001918A # }
196: 192 0001918A # if( halt_flg )
197: 193 0001918A L241:
198: 194 0001918A 5d effffffe48 tstl _halt_flg
199: 195 00019190 31 09 jeql L248
200: 196 00019192 # divd_er_halt( BAD_ACC_HLT ); /* halt on the error */
201: 197 00019192 dd 01 pushl $1
202: 198 00019194 fe 08 ef00000a37 callf $8,_divd_er_halt
203: 199 0001919B # if( loop_on_err ) {
204: 200 0001919B L248:
205: 201 0001919B 5d effffffe37 tstl _loop_on_err
206: 202 000191A1 31 0a jeql L250
207: 203 000191A3 # force_loop = TRUE; /* set the force loop flag */
208: 204 000191A3 0d 01 effffffe2e movl $1,_force_loop
209: 205 000191AA # asm("brw _divd_1_lp1");; /* and loop on the error */
210: 206 000191AA 13 ff2d brw _divd_1_lp1
211: 207 000191AD # } /* end of loop on error */
212: 208 000191AD # } /* end of compare error */
213: 209 000191AD L250:
214: 210 000191AD # } /* end of WHILE loop */
215: 211 000191AD L240:
216: 212 000191AD L236:
217: 213 000191AD 6d effffffe25 incl _index
218: 214 000191B3 13 feba jbr L238
219: 215 000191B6 L237:
220: 216 000191B6 # } /* end of subtest 1 */
221: 217 000191B6 40 ret#2
222: 218 000191B7 .set L232,0x0
223: 219 000191B7 L234:
224: 220 000191B7 13 fea3 jbr L235
225: 221 000191BA .data
226: 222 00000d28 * .text
227: 223 000191BA .align 1
228: 224 000191BA .globl _divd_2
229: 225 000191BA _divd_2:
230: 226 000191BA 0000 .word L251
231: 227 000191BC #
232: 228 000191BC #
233: 229 000191BC #
234: 230 000191BC # /************************************************************************
235: 231 000191BC # *
236: 232 000191BC # * SUBTEST 2 - divide through memory
237: 233 000191BC # *
238: 234 000191BC # ************************************************************************/
239: 235 000191BC # divd_2()
240: 236 000191BC # {
241: 237 000191BC 13 0146 jbr L253
242: 238 000191BF L254:
243: 239 000191BF # force_loop = FALSE;
244: 240 000191BF 4d effffffe13 clrl _force_loop
245: 241 000191C5 # subtest = 2;
246: 242 000191C5 0d 02 effffffe0c movl $2,_subtest
247: 243 000191CC # for( index = 0; index < max_divd_1_index; index++ ) {
248: 244 000191CC 4d effffffe06 clrl _index
249: 245 000191D2 L257:
250: 246 000191D2 1d effffffe00 effffffdfb cmpl _index,_max_divd_1_index
251: 247 000191DD 91 03 13 0122 jgeq L256
252: 248 000191E2 # dbl_ld_acc = divd_1_data[index].op_1; /* get operand 1 */
253: 249 000191E2 5c 18 effffffdef 50 mull3 $24,_index,r0
254: 250 000191EA 0c 8f00000000 50 addl2 $_divd_1_data,r0
255: 251 000191F1 0d a004 effffffde3 movl 4(r0),_dbl_ld_acc+4
256: 252 000191F9 0d 60 effffffdd8 movl (r0),_dbl_ld_acc
257: 253 00019200 # dbl_value_1 = divd_1_data[index].op_2; /* get operand 2 */
258: 254 00019200 5c 18 effffffdd1 50 mull3 $24,_index,r0
259: 255 00019208 0c 8f00000008 50 addl2 $_divd_1_data+8,r0
260: 256 0001920F 0d a004 effffffdc5 movl 4(r0),_dbl_value_1+4
261: 257 00019217 0d 60 effffffdba movl (r0),_dbl_value_1
262: 258 0001921E # dbl_expected = divd_1_data[index].exp; /* get expected result */
263: 259 0001921E 5c 18 effffffdb3 50 mull3 $24,_index,r0
264: 260 00019226 0c 8f00000010 50 addl2 $_divd_1_data+16,r0
265: 261 0001922D 0d a004 effffffda7 movl 4(r0),_dbl_expected+4
266: 262 00019235 0d 60 effffffd9c movl (r0),_dbl_expected
267: 263 0001923C # /*
268: 264 0001923C # * If LOOP ON ERROR is set, this is the loop for this subtest.
269: 265 0001923C # * The force loop flag is set after the first error.
270: 266 0001923C # */
271: 267 0001923C # asm("_divd_2_lp1:");
272: 268 0001923C _divd_2_lp1:
273: 269 0001923C # asm("ldd _dbl_ld_acc"); /* load the 1st operand */
274: 270 0001923C 07 effffffd96 ldd _dbl_ld_acc
275: 271 00019242 # asm("divd _dbl_value_1"); /* divide the 2nd operand */
276: 272 00019242 f7 effffffd90 divd _dbl_value_1
277: 273 00019248 # asm("std _dbl_st_acc"); /* store the result */
278: 274 00019248 27 effffffd8a std _dbl_st_acc
279: 275 0001924E # if( force_loop )
280: 276 0001924E 5d effffffd84 tstl _force_loop
281: 277 00019254 31 02 jeql L258
282: 278 00019256 # asm("brb _divd_2_lp1");; /* loop on the error */
283: 279 00019256 11 e4 brb _divd_2_lp1
284: 280 00019258 L258:
285: 281 00019258 # /*
286: 282 00019258 # * end error loop - test the results
287: 283 00019258 # */
288: 284 00019258 # if( (dbl_st_acc.m != dbl_expected.m) || /* verify the results */
289: 285 00019258 # (dbl_st_acc.l != dbl_expected.l) ) {
290: 286 00019258 1d effffffd7a effffffd75 cmpl _dbl_st_acc,_dbl_expected
291: 287 00019263 21 10 jneq L9998
292: 288 00019265 1d effffffd71 effffffd6c cmpl _dbl_st_acc+4,_dbl_expected+4
293: 289 00019270 21 03 13 0086 jeql L259
294: 290 00019275 L9998:
295: 291 00019275 # errcnt++; /* bump the error count */
296: 292 00019275 6d effffffd5d incl _errcnt
297: 293 0001927B # if( prt_error ) {
298: 294 0001927B 5d effffffd57 tstl _prt_error
299: 295 00019281 31 55 jeql L260
300: 296 00019283 # writes(" \n"); /* start a new print line */
301: 297 00019283 .data 1
302: 298 00000d6f * L261:
303: 299 00000d6f * 200A00 .ascii " \12\0"
304: 300 00000d72 * .text
305: 301 00019283 dd 8f00000d6f pushl $L261
306: 302 00019289 fe 08 effffffd48 callf $8,_writes
307: 303 00019290 # writes("cycle: ");
308: 304 00019290 .data 1
309: 305 00000d72 * L262:
310: 306 00000d72 * 6379636C653A2000 .ascii "cycle: \0"
311: 307 00000d7a * .text
312: 308 00019290 dd 8f00000d72 pushl $L262
313: 309 00019296 fe 08 effffffd3b callf $8,_writes
314: 310 0001929D # writed( cycle );
315: 311 0001929D dd effffffd35 pushl _cycle
316: 312 000192A3 fe 08 effffffd2e callf $8,_writed
317: 313 000192AA # writes(" DIVD test ");
318: 314 000192AA .data 1
319: 315 00000d7a * L263:
320: 316 00000d7a * 2020444956442074657374200 .ascii " DIVD test \0"
321: 0
322: 317 00000d87 * .text
323: 318 000192AA dd 8f00000d7a pushl $L263
324: 319 000192B0 fe 08 effffffd21 callf $8,_writes
325: 320 000192B7 # writed( test_no );
326: 321 000192B7 dd effffffd1b pushl _test_no
327: 322 000192BD fe 08 effffffd14 callf $8,_writed
328: 323 000192C4 # writes(", subtest 2 (Cache Data) - BAD FINAL ACC\n");
329: 324 000192C4 .data 1
330: 325 00000d87 * L264:
331: 326 00000d87 * 2C20737562746573742032202 .ascii ", subtest 2 (Cache Data) - BAD FINAL ACC\12\0"
332: 8436163686520446174612920
333: 2D204241442046494E414C204
334: 143430A00
335: 327 00000db1 * .text
336: 328 000192C4 dd 8f00000d87 pushl $L264
337: 329 000192CA fe 08 effffffd07 callf $8,_writes
338: 330 000192D1 # print_divd_data();
339: 331 000192D1 fe 04 ef00000804 callf $4,_print_divd_data
340: 332 000192D8 # }
341: 333 000192D8 # if( halt_flg )
342: 334 000192D8 L260:
343: 335 000192D8 5d effffffcfa tstl _halt_flg
344: 336 000192DE 31 09 jeql L265
345: 337 000192E0 # divd_er_halt( BAD_ACC_HLT ); /* halt on the error */
346: 338 000192E0 dd 01 pushl $1
347: 339 000192E2 fe 08 ef000008e9 callf $8,_divd_er_halt
348: 340 000192E9 # if( loop_on_err ) {
349: 341 000192E9 L265:
350: 342 000192E9 5d effffffce9 tstl _loop_on_err
351: 343 000192EF 31 0a jeql L266
352: 344 000192F1 # force_loop = TRUE; /* set the force loop flag */
353: 345 000192F1 0d 01 effffffce0 movl $1,_force_loop
354: 346 000192F8 # asm("brw _divd_2_lp1");; /* and loop on the error */
355: 347 000192F8 13 ff41 brw _divd_2_lp1
356: 348 000192FB # } /* end of loop on error */
357: 349 000192FB # } /* end of compare error */
358: 350 000192FB L266:
359: 351 000192FB # } /* end of WHILE loop */
360: 352 000192FB L259:
361: 353 000192FB L255:
362: 354 000192FB 6d effffffcd7 incl _index
363: 355 00019301 13 fece jbr L257
364: 356 00019304 L256:
365: 357 00019304 # } /* end of subtest 2 */
366: 358 00019304 40 ret#2
367: 359 00019305 .set L251,0x0
368: 360 00019305 L253:
369: 361 00019305 13 feb7 jbr L254
370: 362 00019308 .data
371: 363 00000d28 * .text
372: 364 00019308 .align 1
373: 365 00019308 .globl _divd_3
374: 366 00019308 _divd_3:
375: 367 00019308 0000 .word L267
376: 368 0001930A #
377: 369 0001930A #
378: 370 0001930A #
379: 371 0001930A # /****************************************************************************
380: 372 0001930A # *
381: 373 0001930A # * SUBTEST 3 - Wait 2n NOPs before storing the results
382: 374 0001930A # *
383: 375 0001930A # ****************************************************************************/
384: 376 0001930A # divd_3( count )
385: 377 0001930A # int count; /* wait "count" * 2 NOPs */
386: 378 0001930A # {
387: 379 0001930A 13 0180 jbr L269
388: 380 0001930D L270:
389: 381 0001930D # force_loop = FALSE;
390: 382 0001930D 4d effffffcc5 clrl _force_loop
391: 383 00019313 # subtest = 3;
392: 384 00019313 0d 03 effffffcbe movl $3,_subtest
393: 385 0001931A # sgl_dummy2 = count; /* get the NOP count */
394: 386 0001931A 0d ad04 effffffcb6 movl 4(fp),_sgl_dummy2
395: 387 00019322 # for( index = 0; index < max_divd_1_index; index++ ) {
396: 388 00019322 4d effffffcb0 clrl _index
397: 389 00019328 L273:
398: 390 00019328 1d effffffcaa effffffca5 cmpl _index,_max_divd_1_index
399: 391 00019333 91 03 13 0154 jgeq L272
400: 392 00019338 # dbl_ld_acc = divd_1_data[index].op_1; /* get operand 1 */
401: 393 00019338 5c 18 effffffc99 50 mull3 $24,_index,r0
402: 394 00019340 0c 8f00000000 50 addl2 $_divd_1_data,r0
403: 395 00019347 0d a004 effffffc8d movl 4(r0),_dbl_ld_acc+4
404: 396 0001934F 0d 60 effffffc82 movl (r0),_dbl_ld_acc
405: 397 00019356 # dbl_value_1 = divd_1_data[index].op_2; /* get operand 2 */
406: 398 00019356 5c 18 effffffc7b 50 mull3 $24,_index,r0
407: 399 0001935E 0c 8f00000008 50 addl2 $_divd_1_data+8,r0
408: 400 00019365 0d a004 effffffc6f movl 4(r0),_dbl_value_1+4
409: 401 0001936D 0d 60 effffffc64 movl (r0),_dbl_value_1
410: 402 00019374 # dbl_expected = divd_1_data[index].exp; /* get expected result */
411: 403 00019374 5c 18 effffffc5d 50 mull3 $24,_index,r0
412: 404 0001937C 0c 8f00000010 50 addl2 $_divd_1_data+16,r0
413: 405 00019383 0d a004 effffffc51 movl 4(r0),_dbl_expected+4
414: 406 0001938B 0d 60 effffffc46 movl (r0),_dbl_expected
415: 407 00019392 # /*
416: 408 00019392 # * If LOOP ON ERROR is set, this is the loop for this subtest.
417: 409 00019392 # * The force loop flag is set after the first error.
418: 410 00019392 # */
419: 411 00019392 # asm("_divd_3_lp1:");
420: 412 00019392 _divd_3_lp1:
421: 413 00019392 # asm("movl _sgl_dummy2,r0"); /* set the NOP count */
422: 414 00019392 0d effffffc40 50 movl _sgl_dummy2,r0
423: 415 00019399 # asm("ldd _dbl_ld_acc"); /* load the 1st operand */
424: 416 00019399 07 effffffc39 ldd _dbl_ld_acc
425: 417 0001939F # asm("nop"); /* delay */
426: 418 0001939F 10 nop
427: 419 000193A0 # asm("divd _dbl_value_1"); /* divide the 2nd operand */
428: 420 000193A0 f7 effffffc32 divd _dbl_value_1
429: 421 000193A6 # asm("1:");
430: 422 000193A6 1:
431: 423 000193A6 # asm("decl r0"); /* decrement the NOP count */
432: 424 000193A6 7d 50 decl r0
433: 425 000193A8 # asm("bneq 1b"); /* till the count = 0 */
434: 426 000193A8 21 fc bneq 1b
435: 427 000193AA # asm("std _dbl_st_acc"); /* store the result */
436: 428 000193AA 27 effffffc28 std _dbl_st_acc
437: 429 000193B0 # if( force_loop )
438: 430 000193B0 5d effffffc22 tstl _force_loop
439: 431 000193B6 31 02 jeql L274
440: 432 000193B8 # asm("brb _divd_3_lp1");; /* loop on the error */
441: 433 000193B8 11 d8 brb _divd_3_lp1
442: 434 000193BA L274:
443: 435 000193BA # /*
444: 436 000193BA # * end error loop - test the results
445: 437 000193BA # */
446: 438 000193BA # if( (dbl_st_acc.m != dbl_expected.m) || /* verify the results */
447: 439 000193BA # (dbl_st_acc.l != dbl_expected.l) ) {
448: 440 000193BA 1d effffffc18 effffffc13 cmpl _dbl_st_acc,_dbl_expected
449: 441 000193C5 21 10 jneq L9997
450: 442 000193C7 1d effffffc0f effffffc0a cmpl _dbl_st_acc+4,_dbl_expected+4
451: 443 000193D2 21 03 13 00ac jeql L275
452: 444 000193D7 L9997:
453: 445 000193D7 # errcnt++; /* bump the error count */
454: 446 000193D7 6d effffffbfb incl _errcnt
455: 447 000193DD # if( prt_error ) {
456: 448 000193DD 5d effffffbf5 tstl _prt_error
457: 449 000193E3 31 7b jeql L276
458: 450 000193E5 # writes(" \n"); /* start a new print line */
459: 451 000193E5 .data 1
460: 452 00000db1 * L277:
461: 453 00000db1 * 200A00 .ascii " \12\0"
462: 454 00000db4 * .text
463: 455 000193E5 dd 8f00000db1 pushl $L277
464: 456 000193EB fe 08 effffffbe6 callf $8,_writes
465: 457 000193F2 # writes("cycle: ");
466: 458 000193F2 .data 1
467: 459 00000db4 * L278:
468: 460 00000db4 * 6379636C653A2000 .ascii "cycle: \0"
469: 461 00000dbc * .text
470: 462 000193F2 dd 8f00000db4 pushl $L278
471: 463 000193F8 fe 08 effffffbd9 callf $8,_writes
472: 464 000193FF # writed( cycle );
473: 465 000193FF dd effffffbd3 pushl _cycle
474: 466 00019405 fe 08 effffffbcc callf $8,_writed
475: 467 0001940C # writes(" DIVD test ");
476: 468 0001940C .data 1
477: 469 00000dbc * L279:
478: 470 00000dbc * 2020444956442074657374200 .ascii " DIVD test \0"
479: 0
480: 471 00000dc9 * .text
481: 472 0001940C dd 8f00000dbc pushl $L279
482: 473 00019412 fe 08 effffffbbf callf $8,_writes
483: 474 00019419 # writed( test_no );
484: 475 00019419 dd effffffbb9 pushl _test_no
485: 476 0001941F fe 08 effffffbb2 callf $8,_writed
486: 477 00019426 # writes(", subtest 3 (wait ");
487: 478 00019426 .data 1
488: 479 00000dc9 * L280:
489: 480 00000dc9 * 2C20737562746573742033202 .ascii ", subtest 3 (wait \0"
490: 8776169742000
491: 481 00000ddc * .text
492: 482 00019426 dd 8f00000dc9 pushl $L280
493: 483 0001942C fe 08 effffffba5 callf $8,_writes
494: 484 00019433 # sgl_dummy1 = 2*count;
495: 485 00019433 48 01 ad04 50 shll $1,4(fp),r0
496: 486 00019438 0d 50 effffffb99 movl r0,_sgl_dummy1
497: 487 0001943F # writed( sgl_dummy1 ); /* write the NOP count */
498: 488 0001943F dd effffffb93 pushl _sgl_dummy1
499: 489 00019445 fe 08 effffffb8c callf $8,_writed
500: 490 0001944C # writes(" NOPs) - BAD FINAL ACC\n");
501: 491 0001944C .data 1
502: 492 00000ddc * L281:
503: 493 00000ddc * 204E4F507329202D204241442 .ascii " NOPs) - BAD FINAL ACC\12\0"
504: 046494E414C204143430A00
505: 494 00000df4 * .text
506: 495 0001944C dd 8f00000ddc pushl $L281
507: 496 00019452 fe 08 effffffb7f callf $8,_writes
508: 497 00019459 # print_divd_data();
509: 498 00019459 fe 04 ef0000067c callf $4,_print_divd_data
510: 499 00019460 # }
511: 500 00019460 # if( halt_flg )
512: 501 00019460 L276:
513: 502 00019460 5d effffffb72 tstl _halt_flg
514: 503 00019466 31 09 jeql L282
515: 504 00019468 # divd_er_halt( BAD_ACC_HLT ); /* halt on the error */
516: 505 00019468 dd 01 pushl $1
517: 506 0001946A fe 08 ef00000761 callf $8,_divd_er_halt
518: 507 00019471 # if( loop_on_err ) {
519: 508 00019471 L282:
520: 509 00019471 5d effffffb61 tstl _loop_on_err
521: 510 00019477 31 0a jeql L283
522: 511 00019479 # force_loop = TRUE; /* set the force loop flag */
523: 512 00019479 0d 01 effffffb58 movl $1,_force_loop
524: 513 00019480 # asm("brw _divd_3_lp1");; /* and loop on the error */
525: 514 00019480 13 ff0f brw _divd_3_lp1
526: 515 00019483 # } /* end of loop on error */
527: 516 00019483 # } /* end of compare error */
528: 517 00019483 L283:
529: 518 00019483 # } /* end of WHILE loop */
530: 519 00019483 L275:
531: 520 00019483 L271:
532: 521 00019483 6d effffffb4f incl _index
533: 522 00019489 13 fe9c jbr L273
534: 523 0001948C L272:
535: 524 0001948C # } /* end of subtest 3 */
536: 525 0001948C 40 ret#2
537: 526 0001948D .set L267,0x0
538: 527 0001948D L269:
539: 528 0001948D 13 fe7d jbr L270
540: 529 00019490 .data
541: 530 00000d28 * .text
542: 531 00019490 .align 1
543: 532 00019490 .globl _divd_4
544: 533 00019490 _divd_4:
545: 534 00019490 0000 .word L284
546: 535 00019492 #
547: 536 00019492 #
548: 537 00019492 #
549: 538 00019492 # /************************************************************************
550: 539 00019492 # *
551: 540 00019492 # * SUBTEST 4 - Wait 2 NOPs before storing the results
552: 541 00019492 # *
553: 542 00019492 # ************************************************************************/
554: 543 00019492 # divd_4()
555: 544 00019492 # {
556: 545 00019492 13 0149 jbr L286
557: 546 00019495 L287:
558: 547 00019495 # force_loop = FALSE;
559: 548 00019495 4d effffffb3d clrl _force_loop
560: 549 0001949B # subtest = 4;
561: 550 0001949B 0d 04 effffffb36 movl $4,_subtest
562: 551 000194A2 # for( index = 0; index < max_divd_1_index; index++ ) {
563: 552 000194A2 4d effffffb30 clrl _index
564: 553 000194A8 L290:
565: 554 000194A8 1d effffffb2a effffffb25 cmpl _index,_max_divd_1_index
566: 555 000194B3 91 03 13 0125 jgeq L289
567: 556 000194B8 # dbl_ld_acc = divd_1_data[index].op_1; /* get operand 1 */
568: 557 000194B8 5c 18 effffffb19 50 mull3 $24,_index,r0
569: 558 000194C0 0c 8f00000000 50 addl2 $_divd_1_data,r0
570: 559 000194C7 0d a004 effffffb0d movl 4(r0),_dbl_ld_acc+4
571: 560 000194CF 0d 60 effffffb02 movl (r0),_dbl_ld_acc
572: 561 000194D6 # dbl_value_1 = divd_1_data[index].op_2; /* get operand 2 */
573: 562 000194D6 5c 18 effffffafb 50 mull3 $24,_index,r0
574: 563 000194DE 0c 8f00000008 50 addl2 $_divd_1_data+8,r0
575: 564 000194E5 0d a004 effffffaef movl 4(r0),_dbl_value_1+4
576: 565 000194ED 0d 60 effffffae4 movl (r0),_dbl_value_1
577: 566 000194F4 # dbl_expected = divd_1_data[index].exp; /* get expected result */
578: 567 000194F4 5c 18 effffffadd 50 mull3 $24,_index,r0
579: 568 000194FC 0c 8f00000010 50 addl2 $_divd_1_data+16,r0
580: 569 00019503 0d a004 effffffad1 movl 4(r0),_dbl_expected+4
581: 570 0001950B 0d 60 effffffac6 movl (r0),_dbl_expected
582: 571 00019512 # /*
583: 572 00019512 # * If LOOP ON ERROR is set, this is the loop for this subtest.
584: 573 00019512 # * The force loop flag is set after the first error.
585: 574 00019512 # */
586: 575 00019512 # asm("_divd_4_lp1:");
587: 576 00019512 _divd_4_lp1:
588: 577 00019512 # asm("ldd _dbl_ld_acc"); /* load the 1st operand */
589: 578 00019512 07 effffffac0 ldd _dbl_ld_acc
590: 579 00019518 # asm("nop"); /* delay */
591: 580 00019518 10 nop
592: 581 00019519 # asm("divd _dbl_value_1"); /* divide the 2nd operand */
593: 582 00019519 f7 effffffab9 divd _dbl_value_1
594: 583 0001951F # asm("nop"); /* delay before ... */
595: 584 0001951F 10 nop
596: 585 00019520 # asm("nop"); /* ... storing the result */
597: 586 00019520 10 nop
598: 587 00019521 # asm("std _dbl_st_acc"); /* store the result */
599: 588 00019521 27 effffffab1 std _dbl_st_acc
600: 589 00019527 # if( force_loop )
601: 590 00019527 5d effffffaab tstl _force_loop
602: 591 0001952D 31 02 jeql L291
603: 592 0001952F # asm("brb _divd_4_lp1");; /* loop on the error */
604: 593 0001952F 11 e1 brb _divd_4_lp1
605: 594 00019531 L291:
606: 595 00019531 # /*
607: 596 00019531 # * end error loop - test the results
608: 597 00019531 # */
609: 598 00019531 # if( (dbl_st_acc.m != dbl_expected.m) || /* verify the results */
610: 599 00019531 # (dbl_st_acc.l != dbl_expected.l) ) {
611: 600 00019531 1d effffffaa1 effffffa9c cmpl _dbl_st_acc,_dbl_expected
612: 601 0001953C 21 10 jneq L9996
613: 602 0001953E 1d effffffa98 effffffa93 cmpl _dbl_st_acc+4,_dbl_expected+4
614: 603 00019549 21 03 13 0086 jeql L292
615: 604 0001954E L9996:
616: 605 0001954E # errcnt++; /* bump the error count */
617: 606 0001954E 6d effffffa84 incl _errcnt
618: 607 00019554 # if( prt_error ) {
619: 608 00019554 5d effffffa7e tstl _prt_error
620: 609 0001955A 31 55 jeql L293
621: 610 0001955C # writes(" \n"); /* start a new print line */
622: 611 0001955C .data 1
623: 612 00000df4 * L294:
624: 613 00000df4 * 200A00 .ascii " \12\0"
625: 614 00000df7 * .text
626: 615 0001955C dd 8f00000df4 pushl $L294
627: 616 00019562 fe 08 effffffa6f callf $8,_writes
628: 617 00019569 # writes("cycle: ");
629: 618 00019569 .data 1
630: 619 00000df7 * L295:
631: 620 00000df7 * 6379636C653A2000 .ascii "cycle: \0"
632: 621 00000dff * .text
633: 622 00019569 dd 8f00000df7 pushl $L295
634: 623 0001956F fe 08 effffffa62 callf $8,_writes
635: 624 00019576 # writed( cycle );
636: 625 00019576 dd effffffa5c pushl _cycle
637: 626 0001957C fe 08 effffffa55 callf $8,_writed
638: 627 00019583 # writes(" DIVD test ");
639: 628 00019583 .data 1
640: 629 00000dff * L296:
641: 630 00000dff * 2020444956442074657374200 .ascii " DIVD test \0"
642: 0
643: 631 00000e0c * .text
644: 632 00019583 dd 8f00000dff pushl $L296
645: 633 00019589 fe 08 effffffa48 callf $8,_writes
646: 634 00019590 # writed( test_no );
647: 635 00019590 dd effffffa42 pushl _test_no
648: 636 00019596 fe 08 effffffa3b callf $8,_writed
649: 637 0001959D # writes(", subtest 4 (2 NOPs) - BAD FINAL ACC\n");
650: 638 0001959D .data 1
651: 639 00000e0c * L297:
652: 640 00000e0c * 2C20737562746573742034202 .ascii ", subtest 4 (2 NOPs) - BAD FINAL ACC\12\0"
653: 832204E4F507329202D204241
654: 442046494E414C204143430A0
655: 0
656: 641 00000e32 * .text
657: 642 0001959D dd 8f00000e0c pushl $L297
658: 643 000195A3 fe 08 effffffa2e callf $8,_writes
659: 644 000195AA # print_divd_data();
660: 645 000195AA fe 04 ef0000052b callf $4,_print_divd_data
661: 646 000195B1 # }
662: 647 000195B1 # if( halt_flg )
663: 648 000195B1 L293:
664: 649 000195B1 5d effffffa21 tstl _halt_flg
665: 650 000195B7 31 09 jeql L298
666: 651 000195B9 # divd_er_halt( BAD_ACC_HLT ); /* halt on the error */
667: 652 000195B9 dd 01 pushl $1
668: 653 000195BB fe 08 ef00000610 callf $8,_divd_er_halt
669: 654 000195C2 # if( loop_on_err ) {
670: 655 000195C2 L298:
671: 656 000195C2 5d effffffa10 tstl _loop_on_err
672: 657 000195C8 31 0a jeql L299
673: 658 000195CA # force_loop = TRUE; /* set the force loop flag */
674: 659 000195CA 0d 01 effffffa07 movl $1,_force_loop
675: 660 000195D1 # asm("brw _divd_4_lp1");; /* and loop on the error */
676: 661 000195D1 13 ff3e brw _divd_4_lp1
677: 662 000195D4 # } /* end of loop on error */
678: 663 000195D4 # } /* end of compare error */
679: 664 000195D4 L299:
680: 665 000195D4 # } /* end of WHILE loop */
681: 666 000195D4 L292:
682: 667 000195D4 L288:
683: 668 000195D4 6d effffff9fe incl _index
684: 669 000195DA 13 fecb jbr L290
685: 670 000195DD L289:
686: 671 000195DD # } /* end of subtest 4 */
687: 672 000195DD 40 ret#2
688: 673 000195DE .set L284,0x0
689: 674 000195DE L286:
690: 675 000195DE 13 feb4 jbr L287
691: 676 000195E1 .data
692: 677 00000d28 * .text
693: 678 000195E1 00 .align 1
694: 679 000195E2 .globl _divd_5
695: 680 000195E2 _divd_5:
696: 681 000195E2 0000 .word L300
697: 682 000195E4 #
698: 683 000195E4 #
699: 684 000195E4 #
700: 685 000195E4 # /************************************************************************
701: 686 000195E4 # *
702: 687 000195E4 # * SUBTEST 5 - Wait 1 NOP before storing the results
703: 688 000195E4 # *
704: 689 000195E4 # ************************************************************************/
705: 690 000195E4 # divd_5()
706: 691 000195E4 # {
707: 692 000195E4 13 0148 jbr L302
708: 693 000195E7 L303:
709: 694 000195E7 # force_loop = FALSE;
710: 695 000195E7 4d effffff9eb clrl _force_loop
711: 696 000195ED # subtest = 5;
712: 697 000195ED 0d 05 effffff9e4 movl $5,_subtest
713: 698 000195F4 # for( index = 0; index < max_divd_1_index; index++ ) {
714: 699 000195F4 4d effffff9de clrl _index
715: 700 000195FA L306:
716: 701 000195FA 1d effffff9d8 effffff9d3 cmpl _index,_max_divd_1_index
717: 702 00019605 91 03 13 0124 jgeq L305
718: 703 0001960A # dbl_ld_acc = divd_1_data[index].op_1; /* get operand 1 */
719: 704 0001960A 5c 18 effffff9c7 50 mull3 $24,_index,r0
720: 705 00019612 0c 8f00000000 50 addl2 $_divd_1_data,r0
721: 706 00019619 0d a004 effffff9bb movl 4(r0),_dbl_ld_acc+4
722: 707 00019621 0d 60 effffff9b0 movl (r0),_dbl_ld_acc
723: 708 00019628 # dbl_value_1 = divd_1_data[index].op_2; /* get operand 2 */
724: 709 00019628 5c 18 effffff9a9 50 mull3 $24,_index,r0
725: 710 00019630 0c 8f00000008 50 addl2 $_divd_1_data+8,r0
726: 711 00019637 0d a004 effffff99d movl 4(r0),_dbl_value_1+4
727: 712 0001963F 0d 60 effffff992 movl (r0),_dbl_value_1
728: 713 00019646 # dbl_expected = divd_1_data[index].exp; /* get expected result */
729: 714 00019646 5c 18 effffff98b 50 mull3 $24,_index,r0
730: 715 0001964E 0c 8f00000010 50 addl2 $_divd_1_data+16,r0
731: 716 00019655 0d a004 effffff97f movl 4(r0),_dbl_expected+4
732: 717 0001965D 0d 60 effffff974 movl (r0),_dbl_expected
733: 718 00019664 # /*
734: 719 00019664 # * If LOOP ON ERROR is set, this is the loop for this subtest.
735: 720 00019664 # * The force loop flag is set after the first error.
736: 721 00019664 # */
737: 722 00019664 # asm("_divd_5_lp1:");
738: 723 00019664 _divd_5_lp1:
739: 724 00019664 # asm("ldd _dbl_ld_acc"); /* load the 1st operand */
740: 725 00019664 07 effffff96e ldd _dbl_ld_acc
741: 726 0001966A # asm("nop"); /* delay */
742: 727 0001966A 10 nop
743: 728 0001966B # asm("divd _dbl_value_1"); /* divide the 2nd operand */
744: 729 0001966B f7 effffff967 divd _dbl_value_1
745: 730 00019671 # asm("nop"); /* delay before storing */
746: 731 00019671 10 nop
747: 732 00019672 # asm("std _dbl_st_acc"); /* store the result */
748: 733 00019672 27 effffff960 std _dbl_st_acc
749: 734 00019678 # if( force_loop )
750: 735 00019678 5d effffff95a tstl _force_loop
751: 736 0001967E 31 02 jeql L307
752: 737 00019680 # asm("brb _divd_5_lp1");; /* loop on the error */
753: 738 00019680 11 e2 brb _divd_5_lp1
754: 739 00019682 L307:
755: 740 00019682 # /*
756: 741 00019682 # * end error loop - test the results
757: 742 00019682 # */
758: 743 00019682 # if( (dbl_st_acc.m != dbl_expected.m) || /* verify the results */
759: 744 00019682 # (dbl_st_acc.l != dbl_expected.l) ) {
760: 745 00019682 1d effffff950 effffff94b cmpl _dbl_st_acc,_dbl_expected
761: 746 0001968D 21 10 jneq L9995
762: 747 0001968F 1d effffff947 effffff942 cmpl _dbl_st_acc+4,_dbl_expected+4
763: 748 0001969A 21 03 13 0086 jeql L308
764: 749 0001969F L9995:
765: 750 0001969F # errcnt++; /* bump the error count */
766: 751 0001969F 6d effffff933 incl _errcnt
767: 752 000196A5 # if( prt_error ) {
768: 753 000196A5 5d effffff92d tstl _prt_error
769: 754 000196AB 31 55 jeql L309
770: 755 000196AD # writes(" \n"); /* start a new print line */
771: 756 000196AD .data 1
772: 757 00000e32 * L310:
773: 758 00000e32 * 200A00 .ascii " \12\0"
774: 759 00000e35 * .text
775: 760 000196AD dd 8f00000e32 pushl $L310
776: 761 000196B3 fe 08 effffff91e callf $8,_writes
777: 762 000196BA # writes("cycle: ");
778: 763 000196BA .data 1
779: 764 00000e35 * L311:
780: 765 00000e35 * 6379636C653A2000 .ascii "cycle: \0"
781: 766 00000e3d * .text
782: 767 000196BA dd 8f00000e35 pushl $L311
783: 768 000196C0 fe 08 effffff911 callf $8,_writes
784: 769 000196C7 # writed( cycle );
785: 770 000196C7 dd effffff90b pushl _cycle
786: 771 000196CD fe 08 effffff904 callf $8,_writed
787: 772 000196D4 # writes(" DIVD test ");
788: 773 000196D4 .data 1
789: 774 00000e3d * L312:
790: 775 00000e3d * 2020444956442074657374200 .ascii " DIVD test \0"
791: 0
792: 776 00000e4a * .text
793: 777 000196D4 dd 8f00000e3d pushl $L312
794: 778 000196DA fe 08 effffff8f7 callf $8,_writes
795: 779 000196E1 # writed( test_no );
796: 780 000196E1 dd effffff8f1 pushl _test_no
797: 781 000196E7 fe 08 effffff8ea callf $8,_writed
798: 782 000196EE # writes(", subtest 5 (1 NOP) - BAD FINAL ACC\n");
799: 783 000196EE .data 1
800: 784 00000e4a * L313:
801: 785 00000e4a * 2C20737562746573742035202 .ascii ", subtest 5 (1 NOP) - BAD FINAL ACC\12\0"
802: 831204E4F5029202D20424144
803: 2046494E414C204143430A00
804: 786 00000e6f * .text
805: 787 000196EE dd 8f00000e4a pushl $L313
806: 788 000196F4 fe 08 effffff8dd callf $8,_writes
807: 789 000196FB # print_divd_data();
808: 790 000196FB fe 04 ef000003da callf $4,_print_divd_data
809: 791 00019702 # }
810: 792 00019702 # if( halt_flg )
811: 793 00019702 L309:
812: 794 00019702 5d effffff8d0 tstl _halt_flg
813: 795 00019708 31 09 jeql L314
814: 796 0001970A # divd_er_halt( BAD_ACC_HLT ); /* halt on the error */
815: 797 0001970A dd 01 pushl $1
816: 798 0001970C fe 08 ef000004bf callf $8,_divd_er_halt
817: 799 00019713 # if( loop_on_err ) {
818: 800 00019713 L314:
819: 801 00019713 5d effffff8bf tstl _loop_on_err
820: 802 00019719 31 0a jeql L315
821: 803 0001971B # force_loop = TRUE; /* set the force loop flag */
822: 804 0001971B 0d 01 effffff8b6 movl $1,_force_loop
823: 805 00019722 # asm("brw _divd_5_lp1");; /* and loop on the error */
824: 806 00019722 13 ff3f brw _divd_5_lp1
825: 807 00019725 # } /* end of loop on error */
826: 808 00019725 # } /* end of compare error */
827: 809 00019725 L315:
828: 810 00019725 # } /* end of WHILE loop */
829: 811 00019725 L308:
830: 812 00019725 L304:
831: 813 00019725 6d effffff8ad incl _index
832: 814 0001972B 13 fecc jbr L306
833: 815 0001972E L305:
834: 816 0001972E # } /* end of subtest 5 */
835: 817 0001972E 40 ret#2
836: 818 0001972F .set L300,0x0
837: 819 0001972F L302:
838: 820 0001972F 13 feb5 jbr L303
839: 821 00019732 .data
840: 822 00000d28 * .text
841: 823 00019732 .align 1
842: 824 00019732 .globl _divd_6
843: 825 00019732 _divd_6:
844: 826 00019732 0000 .word L316
845: 827 00019734 #
846: 828 00019734 #
847: 829 00019734 #
848: 830 00019734 # /************************************************************************
849: 831 00019734 # *
850: 832 00019734 # * SUBTEST 6 - Check for register corruption
851: 833 00019734 # *
852: 834 00019734 # ************************************************************************/
853: 835 00019734 # divd_6()
854: 836 00019734 # {
855: 837 00019734 13 01c8 jbr L318
856: 838 00019737 L319:
857: 839 00019737 # force_loop = FALSE; /* clear force_loop flg */
858: 840 00019737 4d effffff89b clrl _force_loop
859: 841 0001973D # subtest = 6;
860: 842 0001973D 0d 06 effffff894 movl $6,_subtest
861: 843 00019744 # fill_reg_buf( load_regs ); /* get patterns for regs */
862: 844 00019744 dd 8f00000000 pushl $_load_regs
863: 845 0001974A fe 08 effffff887 callf $8,_fill_reg_buf
864: 846 00019751 # index = 0;
865: 847 00019751 4d effffff881 clrl _index
866: 848 00019757 # dbl_ld_acc = divd_1_data[0].op_1; /* get operand 1 */
867: 849 00019757 0d effffff87f effffff87a movl _divd_1_data+4,_dbl_ld_acc+4
868: 850 00019762 0d effffff870 effffff86b movl _divd_1_data,_dbl_ld_acc
869: 851 0001976D # dbl_value_1 = divd_1_data[0].op_2; /* get operand 2 */
870: 852 0001976D 0d effffff871 effffff864 movl _divd_1_data+12,_dbl_value_1+4
871: 853 00019778 0d effffff862 effffff855 movl _divd_1_data+8,_dbl_value_1
872: 854 00019783 # dbl_expected = divd_1_data[0].exp; /* get expected result */
873: 855 00019783 0d effffff863 effffff84e movl _divd_1_data+20,_dbl_expected+4
874: 856 0001978E 0d effffff854 effffff83f movl _divd_1_data+16,_dbl_expected
875: 857 00019799 # /*
876: 858 00019799 # * If LOOP ON ERROR is set, this is the loop for this subtest.
877: 859 00019799 # * The force loop flag is set after the first error.
878: 860 00019799 # */
879: 861 00019799 # asm("_divd_6_lp1:");
880: 862 00019799 _divd_6_lp1:
881: 863 00019799 # asm("ldd _dbl_ld_acc"); /* LOAD the accumulator */
882: 864 00019799 07 effffff839 ldd _dbl_ld_acc
883: 865 0001979F # asm("nop");
884: 866 0001979F 10 nop
885: 867 000197A0 # asm("loadr $0x1fff,_load_regs"); /* load regs 0 - 12 */
886: 868 000197A0 ab 891fff effffff82f loadr $0x1fff,_load_regs
887: 869 000197A9 # asm("nop");
888: 870 000197A9 10 nop
889: 871 000197AA # asm("divd _dbl_value_1"); /* do the divide */
890: 872 000197AA f7 effffff828 divd _dbl_value_1
891: 873 000197B0 # asm("nop");
892: 874 000197B0 10 nop
893: 875 000197B1 # asm("storer $0x1fff,_store_regs"); /* store regs 0 - 12 */
894: 876 000197B1 bb 891fff effffff81e storer $0x1fff,_store_regs
895: 877 000197BA # asm("std _dbl_st_acc"); /* save the accumulator */
896: 878 000197BA 27 effffff818 std _dbl_st_acc
897: 879 000197C0 # if( force_loop )
898: 880 000197C0 5d effffff812 tstl _force_loop
899: 881 000197C6 31 02 jeql L321
900: 882 000197C8 # asm("brb _divd_6_lp1");; /* loop on the error */
901: 883 000197C8 11 cf brb _divd_6_lp1
902: 884 000197CA L321:
903: 885 000197CA # /*
904: 886 000197CA # * Now compare the stored register values to those that were loaded
905: 887 000197CA # */
906: 888 000197CA # index2 = 0;
907: 889 000197CA 4d effffff808 clrl _index2
908: 890 000197D0 # while( (load_regs[index2] == store_regs[index2]) && (index2 < 13) )
909: 891 000197D0 L322:
910: 892 000197D0 0d effffff802 50 movl _index2,r0
911: 893 000197D7 0d effffff7fb 51 movl _index2,r1
912: 894 000197DE 1d 40effffff7f3 cmpl _load_regs[r0],_store_regs[r1]
913: 41effffff7ed
914: 895 000197EB 21 11 jneq L323
915: 896 000197ED 1d effffff7e5 0d cmpl _index2,$13
916: 897 000197F4 81 08 jgeq L323
917: 898 000197F6 # index2++; /* check reg values */
918: 899 000197F6 6d effffff7dc incl _index2
919: 900 000197FC 11 d2 jbr L322
920: 901 000197FE L323:
921: 902 000197FE # if( index2 < 13 ) { /* error if index2 < 13 */
922: 903 000197FE 1d effffff7d4 0d cmpl _index2,$13
923: 904 00019805 91 03 13 00f4 jgeq L324
924: 905 0001980A # errcnt++; /* bump the error count */
925: 906 0001980A 6d effffff7c8 incl _errcnt
926: 907 00019810 # if( prt_error ) {
927: 908 00019810 5d effffff7c2 tstl _prt_error
928: 909 00019816 21 03 13 00c0 jeql L325
929: 910 0001981B # writes(" \n"); /* start a new print line */
930: 911 0001981B .data 1
931: 912 00000e6f * L326:
932: 913 00000e6f * 200A00 .ascii " \12\0"
933: 914 00000e72 * .text
934: 915 0001981B dd 8f00000e6f pushl $L326
935: 916 00019821 fe 08 effffff7b0 callf $8,_writes
936: 917 00019828 # writes("cycle: ");
937: 918 00019828 .data 1
938: 919 00000e72 * L327:
939: 920 00000e72 * 6379636C653A2000 .ascii "cycle: \0"
940: 921 00000e7a * .text
941: 922 00019828 dd 8f00000e72 pushl $L327
942: 923 0001982E fe 08 effffff7a3 callf $8,_writes
943: 924 00019835 # writed( cycle );
944: 925 00019835 dd effffff79d pushl _cycle
945: 926 0001983B fe 08 effffff796 callf $8,_writed
946: 927 00019842 # writes(" DIVD test ");
947: 928 00019842 .data 1
948: 929 00000e7a * L328:
949: 930 00000e7a * 2020444956442074657374200 .ascii " DIVD test \0"
950: 0
951: 931 00000e87 * .text
952: 932 00019842 dd 8f00000e7a pushl $L328
953: 933 00019848 fe 08 effffff789 callf $8,_writes
954: 934 0001984F # writed( test_no );
955: 935 0001984F dd effffff783 pushl _test_no
956: 936 00019855 fe 08 effffff77c callf $8,_writed
957: 937 0001985C # writes(", subtest 6 - A REGISTER WAS CHANGED\n");
958: 938 0001985C .data 1
959: 939 00000e87 * L329:
960: 940 00000e87 * 2C20737562746573742036202 .ascii ", subtest 6 - A REGISTER WAS CHANGED\12\0"
961: D204120524547495354455220
962: 574153204348414E4745440A0
963: 0
964: 941 00000ead * .text
965: 942 0001985C dd 8f00000e87 pushl $L329
966: 943 00019862 fe 08 effffff76f callf $8,_writes
967: 944 00019869 # print_divd_data(); /* print the operands */
968: 945 00019869 fe 04 ef0000026c callf $4,_print_divd_data
969: 946 00019870 # writes("register "); /* print the information */
970: 947 00019870 .data 1
971: 948 00000ead * L330:
972: 949 00000ead * 72656769737465722000 .ascii "register \0"
973: 950 00000eb7 * .text
974: 951 00019870 dd 8f00000ead pushl $L330
975: 952 00019876 fe 08 effffff75b callf $8,_writes
976: 953 0001987D # writed( index2 ); /* about the corrupted */
977: 954 0001987D dd effffff755 pushl _index2
978: 955 00019883 fe 08 effffff74e callf $8,_writed
979: 956 0001988A # writes(" = "); /* register */
980: 957 0001988A .data 1
981: 958 00000eb7 * L331:
982: 959 00000eb7 * 203D2000 .ascii " = \0"
983: 960 00000ebb * .text
984: 961 0001988A dd 8f00000eb7 pushl $L331
985: 962 00019890 fe 08 effffff741 callf $8,_writes
986: 963 00019897 # write32h( store_regs[index2] );
987: 964 00019897 0d effffff73b 50 movl _index2,r0
988: 965 0001989E dd 40effffff733 pushl _store_regs[r0]
989: 966 000198A5 fe 08 effffff72c callf $8,_write32h
990: 967 000198AC # writes(", should be = ");
991: 968 000198AC .data 1
992: 969 00000ebb * L333:
993: 970 00000ebb * 2C202073686F756C642062652 .ascii ", should be = \0"
994: 03D2000
995: 971 00000ecb * .text
996: 972 000198AC dd 8f00000ebb pushl $L333
997: 973 000198B2 fe 08 effffff71f callf $8,_writes
998: 974 000198B9 # write32h( load_regs[index2] );
999: 975 000198B9 0d effffff719 50 movl _index2,r0
1000: 976 000198C0 dd 40effffff711 pushl _load_regs[r0]
1001: 977 000198C7 fe 08 effffff70a callf $8,_write32h
1002: 978 000198CE # writes("\n");
1003: 979 000198CE .data 1
1004: 980 00000ecb * L334:
1005: 981 00000ecb * 0A00 .ascii "\12\0"
1006: 982 00000ecd * .text
1007: 983 000198CE dd 8f00000ecb pushl $L334
1008: 984 000198D4 fe 08 effffff6fd callf $8,_writes
1009: 985 000198DB # }
1010: 986 000198DB # if( halt_flg )
1011: 987 000198DB L325:
1012: 988 000198DB 5d effffff6f7 tstl _halt_flg
1013: 989 000198E1 31 09 jeql L335
1014: 990 000198E3 # divd_er_halt( BAD_REG_HLT ); /* halt on the error */
1015: 991 000198E3 dd 02 pushl $2
1016: 992 000198E5 fe 08 ef000002e6 callf $8,_divd_er_halt
1017: 993 000198EC # if( loop_on_err ) {
1018: 994 000198EC L335:
1019: 995 000198EC 5d effffff6e6 tstl _loop_on_err
1020: 996 000198F2 31 0a jeql L336
1021: 997 000198F4 # force_loop = TRUE; /* set the force loop flag */
1022: 998 000198F4 0d 01 effffff6dd movl $1,_force_loop
1023: 999 000198FB # asm("brw _divd_6_lp1");; /* and loop on the error */
1024: 1000 000198FB 13 fe9b brw _divd_6_lp1
1025: 1001 000198FE # } /* end of loop on error */
1026: 1002 000198FE # } /* end of register corruption error */
1027: 1003 000198FE L336:
1028: 1004 000198FE # } /* end of subtest 6 */
1029: 1005 000198FE L324:
1030: 1006 000198FE 40 ret#2
1031: 1007 000198FF .set L316,0x0
1032: 1008 000198FF L318:
1033: 1009 000198FF 13 fe35 jbr L319
1034: 1010 00019902 .data
1035: 1011 00000d28 * .text
1036: 1012 00019902 .align 1
1037: 1013 00019902 .globl _divd_7
1038: 1014 00019902 _divd_7:
1039: 1015 00019902 0000 .word L337
1040: 1016 00019904 #
1041: 1017 00019904 #
1042: 1018 00019904 #
1043: 1019 00019904 # /************************************************************************
1044: 1020 00019904 # *
1045: 1021 00019904 # * SUBTEST 7 - Check for PSL corruption
1046: 1022 00019904 # *
1047: 1023 00019904 # ************************************************************************/
1048: 1024 00019904 # divd_7()
1049: 1025 00019904 # {
1050: 1026 00019904 13 01d2 jbr L339
1051: 1027 00019907 L340:
1052: 1028 00019907 # force_loop = FALSE; /* clear force_loop flg */
1053: 1029 00019907 4d effffff6cb clrl _force_loop
1054: 1030 0001990D # subtest = 7;
1055: 1031 0001990D 0d 07 effffff6c4 movl $7,_subtest
1056: 1032 00019914 # fill_reg_buf( load_regs ); /* get patterns for regs */
1057: 1033 00019914 dd 8f00000000 pushl $_load_regs
1058: 1034 0001991A fe 08 effffff6b7 callf $8,_fill_reg_buf
1059: 1035 00019921 # for( index = 0; index < 3; index++ ) {
1060: 1036 00019921 4d effffff6b1 clrl _index
1061: 1037 00019927 L343:
1062: 1038 00019927 1d effffff6ab 03 cmpl _index,$3
1063: 1039 0001992E 91 03 13 01a5 jgeq L342
1064: 1040 00019933 # dbl_ld_acc = divd_1_data[index].op_1; /* get operand 1 */
1065: 1041 00019933 5c 18 effffff69e 50 mull3 $24,_index,r0
1066: 1042 0001993B 0c 8f00000000 50 addl2 $_divd_1_data,r0
1067: 1043 00019942 0d a004 effffff692 movl 4(r0),_dbl_ld_acc+4
1068: 1044 0001994A 0d 60 effffff687 movl (r0),_dbl_ld_acc
1069: 1045 00019951 # dbl_value_1 = divd_1_data[index].op_2; /* get operand 2 */
1070: 1046 00019951 5c 18 effffff680 50 mull3 $24,_index,r0
1071: 1047 00019959 0c 8f00000008 50 addl2 $_divd_1_data+8,r0
1072: 1048 00019960 0d a004 effffff674 movl 4(r0),_dbl_value_1+4
1073: 1049 00019968 0d 60 effffff669 movl (r0),_dbl_value_1
1074: 1050 0001996F # dbl_expected = divd_1_data[index].exp; /* get expected */
1075: 1051 0001996F 5c 18 effffff662 50 mull3 $24,_index,r0
1076: 1052 00019977 0c 8f00000010 50 addl2 $_divd_1_data+16,r0
1077: 1053 0001997E 0d a004 effffff656 movl 4(r0),_dbl_expected+4
1078: 1054 00019986 0d 60 effffff64b movl (r0),_dbl_expected
1079: 1055 0001998D # sgl_dummy1 = status_array[status_index]; /* status = +, -, 0 */
1080: 1056 0001998D 0d effffff645 50 movl _status_index,r0
1081: 1057 00019994 0d 40effffff63d movl _status_array[r0],_sgl_dummy1
1082: effffff638
1083: 1058 000199A0 # /*
1084: 1059 000199A0 # * If LOOP ON ERROR is set, this is the loop for this subtest.
1085: 1060 000199A0 # * The force loop flag is set after the first error.
1086: 1061 000199A0 # */
1087: 1062 000199A0 # asm("_divd_7_lp1:");
1088: 1063 000199A0 _divd_7_lp1:
1089: 1064 000199A0 # asm("ldd _dbl_ld_acc"); /* LOAD the accumulator */
1090: 1065 000199A0 07 effffff632 ldd _dbl_ld_acc
1091: 1066 000199A6 # asm("nop");
1092: 1067 000199A6 10 nop
1093: 1068 000199A7 # asm("tstl _sgl_dummy1"); /* set the PSL status */
1094: 1069 000199A7 5d effffff62b tstl _sgl_dummy1
1095: 1070 000199AD # asm("movpsl _init_psl"); /* save the initial PSL */
1096: 1071 000199AD cd effffff625 movpsl _init_psl
1097: 1072 000199B3 # asm("divd _dbl_value_1"); /* do the divide */
1098: 1073 000199B3 f7 effffff61f divd _dbl_value_1
1099: 1074 000199B9 # asm("nop");
1100: 1075 000199B9 10 nop
1101: 1076 000199BA # asm("movpsl _psl_val"); /* save the final PSL */
1102: 1077 000199BA cd effffff618 movpsl _psl_val
1103: 1078 000199C0 # asm("std _dbl_st_acc"); /* save the accumulator */
1104: 1079 000199C0 27 effffff612 std _dbl_st_acc
1105: 1080 000199C6 # if( force_loop )
1106: 1081 000199C6 5d effffff60c tstl _force_loop
1107: 1082 000199CC 31 02 jeql L344
1108: 1083 000199CE # asm("brb _divd_7_lp1");; /* loop on the error */
1109: 1084 000199CE 11 d0 brb _divd_7_lp1
1110: 1085 000199D0 L344:
1111: 1086 000199D0 # /*
1112: 1087 000199D0 # * Now compare the final PSL to the initial PSL -they should be the same
1113: 1088 000199D0 # */
1114: 1089 000199D0 # exp_psl = init_psl;
1115: 1090 000199D0 0d effffff602 effffff5fd movl _init_psl,_exp_psl
1116: 1091 000199DB # if( psl_val != exp_psl ) {
1117: 1092 000199DB 1d effffff5f7 effffff5f2 cmpl _psl_val,_exp_psl
1118: 1093 000199E6 21 03 13 00e4 jeql L345
1119: 1094 000199EB # errcnt++; /* bump the error count */
1120: 1095 000199EB 6d effffff5e7 incl _errcnt
1121: 1096 000199F1 # if( prt_error ) {
1122: 1097 000199F1 5d effffff5e1 tstl _prt_error
1123: 1098 000199F7 21 03 13 00b0 jeql L346
1124: 1099 000199FC # writes(" \n"); /* start a new print line */
1125: 1100 000199FC .data 1
1126: 1101 00000ecd * L347:
1127: 1102 00000ecd * 200A00 .ascii " \12\0"
1128: 1103 00000ed0 * .text
1129: 1104 000199FC dd 8f00000ecd pushl $L347
1130: 1105 00019A02 fe 08 effffff5cf callf $8,_writes
1131: 1106 00019A09 # writes("cycle: ");
1132: 1107 00019A09 .data 1
1133: 1108 00000ed0 * L348:
1134: 1109 00000ed0 * 6379636C653A2000 .ascii "cycle: \0"
1135: 1110 00000ed8 * .text
1136: 1111 00019A09 dd 8f00000ed0 pushl $L348
1137: 1112 00019A0F fe 08 effffff5c2 callf $8,_writes
1138: 1113 00019A16 # writed( cycle );
1139: 1114 00019A16 dd effffff5bc pushl _cycle
1140: 1115 00019A1C fe 08 effffff5b5 callf $8,_writed
1141: 1116 00019A23 # writes(" DIVD test ");
1142: 1117 00019A23 .data 1
1143: 1118 00000ed8 * L349:
1144: 1119 00000ed8 * 2020444956442074657374200 .ascii " DIVD test \0"
1145: 0
1146: 1120 00000ee5 * .text
1147: 1121 00019A23 dd 8f00000ed8 pushl $L349
1148: 1122 00019A29 fe 08 effffff5a8 callf $8,_writes
1149: 1123 00019A30 # writed( test_no );
1150: 1124 00019A30 dd effffff5a2 pushl _test_no
1151: 1125 00019A36 fe 08 effffff59b callf $8,_writed
1152: 1126 00019A3D # writes(", subtest 7 - INCORRECT FINAL PSL\n");
1153: 1127 00019A3D .data 1
1154: 1128 00000ee5 * L350:
1155: 1129 00000ee5 * 2C20737562746573742037202 .ascii ", subtest 7 - INCORRECT FINAL PSL\12\0"
1156: D20494E434F52524543542046
1157: 494E414C2050534C0A00
1158: 1130 00000f08 * .text
1159: 1131 00019A3D dd 8f00000ee5 pushl $L350
1160: 1132 00019A43 fe 08 effffff58e callf $8,_writes
1161: 1133 00019A4A # print_divd_data(); /* print the operands */
1162: 1134 00019A4A fe 04 ef0000008b callf $4,_print_divd_data
1163: 1135 00019A51 # writes("initial PSL = ");
1164: 1136 00019A51 .data 1
1165: 1137 00000f08 * L351:
1166: 1138 00000f08 * 696E697469616C2050534C203 .ascii "initial PSL = \0"
1167: D2000
1168: 1139 00000f17 * .text
1169: 1140 00019A51 dd 8f00000f08 pushl $L351
1170: 1141 00019A57 fe 08 effffff57a callf $8,_writes
1171: 1142 00019A5E # write32h( init_psl );
1172: 1143 00019A5E dd effffff574 pushl _init_psl
1173: 1144 00019A64 fe 08 effffff56d callf $8,_write32h
1174: 1145 00019A6B # writes(", final PSL = ");
1175: 1146 00019A6B .data 1
1176: 1147 00000f17 * L352:
1177: 1148 00000f17 * 2C202066696E616C2050534C2 .ascii ", final PSL = \0"
1178: 03D2000
1179: 1149 00000f27 * .text
1180: 1150 00019A6B dd 8f00000f17 pushl $L352
1181: 1151 00019A71 fe 08 effffff560 callf $8,_writes
1182: 1152 00019A78 # write32h( psl_val );
1183: 1153 00019A78 dd effffff55a pushl _psl_val
1184: 1154 00019A7E fe 08 effffff553 callf $8,_write32h
1185: 1155 00019A85 # writes(", expected PSL = ");
1186: 1156 00019A85 .data 1
1187: 1157 00000f27 * L353:
1188: 1158 00000f27 * 2C20206578706563746564205 .ascii ", expected PSL = \0"
1189: 0534C203D2000
1190: 1159 00000f3a * .text
1191: 1160 00019A85 dd 8f00000f27 pushl $L353
1192: 1161 00019A8B fe 08 effffff546 callf $8,_writes
1193: 1162 00019A92 # write32h( exp_psl );
1194: 1163 00019A92 dd effffff540 pushl _exp_psl
1195: 1164 00019A98 fe 08 effffff539 callf $8,_write32h
1196: 1165 00019A9F # writes("\n");
1197: 1166 00019A9F .data 1
1198: 1167 00000f3a * L354:
1199: 1168 00000f3a * 0A00 .ascii "\12\0"
1200: 1169 00000f3c * .text
1201: 1170 00019A9F dd 8f00000f3a pushl $L354
1202: 1171 00019AA5 fe 08 effffff52c callf $8,_writes
1203: 1172 00019AAC # }
1204: 1173 00019AAC # if( halt_flg )
1205: 1174 00019AAC L346:
1206: 1175 00019AAC 5d effffff526 tstl _halt_flg
1207: 1176 00019AB2 31 09 jeql L355
1208: 1177 00019AB4 # divd_er_halt( BAD_PSL_HLT ); /* halt on the error */
1209: 1178 00019AB4 dd 03 pushl $3
1210: 1179 00019AB6 fe 08 ef00000115 callf $8,_divd_er_halt
1211: 1180 00019ABD # if( loop_on_err ) {
1212: 1181 00019ABD L355:
1213: 1182 00019ABD 5d effffff515 tstl _loop_on_err
1214: 1183 00019AC3 31 0a jeql L356
1215: 1184 00019AC5 # force_loop = TRUE; /* set the force loop flag */
1216: 1185 00019AC5 0d 01 effffff50c movl $1,_force_loop
1217: 1186 00019ACC # asm("brw _divd_7_lp1");; /* and loop on the error */
1218: 1187 00019ACC 13 fed1 brw _divd_7_lp1
1219: 1188 00019ACF # } /* end of loop on error */
1220: 1189 00019ACF # } /* end of PSL corruption error */
1221: 1190 00019ACF L356:
1222: 1191 00019ACF # } /* end of WHILE loop */
1223: 1192 00019ACF L345:
1224: 1193 00019ACF L341:
1225: 1194 00019ACF 6d effffff503 incl _index
1226: 1195 00019AD5 13 fe4f jbr L343
1227: 1196 00019AD8 L342:
1228: 1197 00019AD8 # } /* end of subtest 7 */
1229: 1198 00019AD8 40 ret#2
1230: 1199 00019AD9 .set L337,0x0
1231: 1200 00019AD9 L339:
1232: 1201 00019AD9 13 fe2b jbr L340
1233: 1202 00019ADC .data
1234: 1203 00000d28 * .text
1235: 1204 00019ADC .align 1
1236: 1205 00019ADC .globl _print_divd_data
1237: 1206 00019ADC _print_divd_data:
1238: 1207 00019ADC 0000 .word L357
1239: 1208 00019ADE #
1240: 1209 00019ADE #
1241: 1210 00019ADE #
1242: 1211 00019ADE # /**************************************************************************
1243: 1212 00019ADE # *
1244: 1213 00019ADE # * PRINT THE DATA AND STORE RESULTS
1245: 1214 00019ADE # *
1246: 1215 00019ADE # * initial Acc = xxxxxxxx xxxxxxxx, stored = xxxxxxxx xxxxxxxx, index = xx
1247: 1216 00019ADE # * operand = xxxxxxxx xxxxxxxx, expected = xxxxxxxx xxxxxxxx
1248: 1217 00019ADE # **************************************************************************/
1249: 1218 00019ADE # print_divd_data()
1250: 1219 00019ADE # {
1251: 1220 00019ADE 13 00ed jbr L359
1252: 1221 00019AE1 L360:
1253: 1222 00019AE1 # writes("initial Acc = ");
1254: 1223 00019AE1 .data 1
1255: 1224 00000f3c * L361:
1256: 1225 00000f3c * 696E697469616C20416363203 .ascii "initial Acc = \0"
1257: D2000
1258: 1226 00000f4b * .text
1259: 1227 00019AE1 dd 8f00000f3c pushl $L361
1260: 1228 00019AE7 fe 08 effffff4ea callf $8,_writes
1261: 1229 00019AEE # write32h( dbl_ld_acc.m );
1262: 1230 00019AEE dd effffff4e4 pushl _dbl_ld_acc
1263: 1231 00019AF4 fe 08 effffff4dd callf $8,_write32h
1264: 1232 00019AFB # writec(' ');
1265: 1233 00019AFB dd 20 pushl $32
1266: 1234 00019AFD fe 08 effffff4d4 callf $8,_writec
1267: 1235 00019B04 # write32h( dbl_ld_acc.l );
1268: 1236 00019B04 dd effffff4d2 pushl _dbl_ld_acc+4
1269: 1237 00019B0A fe 08 effffff4c7 callf $8,_write32h
1270: 1238 00019B11 # writes(", stored = ");
1271: 1239 00019B11 .data 1
1272: 1240 00000f4b * L363:
1273: 1241 00000f4b * 2C2020202073746F726564203 .ascii ", stored = \0"
1274: D2000
1275: 1242 00000f5a * .text
1276: 1243 00019B11 dd 8f00000f4b pushl $L363
1277: 1244 00019B17 fe 08 effffff4ba callf $8,_writes
1278: 1245 00019B1E # write32h( dbl_st_acc.m );
1279: 1246 00019B1E dd effffff4b4 pushl _dbl_st_acc
1280: 1247 00019B24 fe 08 effffff4ad callf $8,_write32h
1281: 1248 00019B2B # writec(' ');
1282: 1249 00019B2B dd 20 pushl $32
1283: 1250 00019B2D fe 08 effffff4a4 callf $8,_writec
1284: 1251 00019B34 # write32h( dbl_st_acc.l );
1285: 1252 00019B34 dd effffff4a2 pushl _dbl_st_acc+4
1286: 1253 00019B3A fe 08 effffff497 callf $8,_write32h
1287: 1254 00019B41 # writes(", index = ");
1288: 1255 00019B41 .data 1
1289: 1256 00000f5a * L364:
1290: 1257 00000f5a * 2C202020696E646578203D200 .ascii ", index = \0"
1291: 0
1292: 1258 00000f67 * .text
1293: 1259 00019B41 dd 8f00000f5a pushl $L364
1294: 1260 00019B47 fe 08 effffff48a callf $8,_writes
1295: 1261 00019B4E # writed( index );
1296: 1262 00019B4E dd effffff484 pushl _index
1297: 1263 00019B54 fe 08 effffff47d callf $8,_writed
1298: 1264 00019B5B # writec('\n');
1299: 1265 00019B5B dd 0a pushl $10
1300: 1266 00019B5D fe 08 effffff474 callf $8,_writec
1301: 1267 00019B64 # writes(" operand = ");
1302: 1268 00019B64 .data 1
1303: 1269 00000f67 * L365:
1304: 1270 00000f67 * 202020206F706572616E64203 .ascii " operand = \0"
1305: D2000
1306: 1271 00000f76 * .text
1307: 1272 00019B64 dd 8f00000f67 pushl $L365
1308: 1273 00019B6A fe 08 effffff467 callf $8,_writes
1309: 1274 00019B71 # write32h( dbl_value_1.m );
1310: 1275 00019B71 dd effffff461 pushl _dbl_value_1
1311: 1276 00019B77 fe 08 effffff45a callf $8,_write32h
1312: 1277 00019B7E # writec(' ');
1313: 1278 00019B7E dd 20 pushl $32
1314: 1279 00019B80 fe 08 effffff451 callf $8,_writec
1315: 1280 00019B87 # write32h( dbl_value_1.l );
1316: 1281 00019B87 dd effffff44f pushl _dbl_value_1+4
1317: 1282 00019B8D fe 08 effffff444 callf $8,_write32h
1318: 1283 00019B94 # writes(", expected = ");
1319: 1284 00019B94 .data 1
1320: 1285 00000f76 * L366:
1321: 1286 00000f76 * 2C20206578706563746564203 .ascii ", expected = \0"
1322: D2000
1323: 1287 00000f85 * .text
1324: 1288 00019B94 dd 8f00000f76 pushl $L366
1325: 1289 00019B9A fe 08 effffff437 callf $8,_writes
1326: 1290 00019BA1 # write32h( dbl_expected.m );
1327: 1291 00019BA1 dd effffff431 pushl _dbl_expected
1328: 1292 00019BA7 fe 08 effffff42a callf $8,_write32h
1329: 1293 00019BAE # writec(' ');
1330: 1294 00019BAE dd 20 pushl $32
1331: 1295 00019BB0 fe 08 effffff421 callf $8,_writec
1332: 1296 00019BB7 # write32h( dbl_expected.l );
1333: 1297 00019BB7 dd effffff41f pushl _dbl_expected+4
1334: 1298 00019BBD fe 08 effffff414 callf $8,_write32h
1335: 1299 00019BC4 # writec('\n');
1336: 1300 00019BC4 dd 0a pushl $10
1337: 1301 00019BC6 fe 08 effffff40b callf $8,_writec
1338: 1302 00019BCD # }
1339: 1303 00019BCD 40 ret#2
1340: 1304 00019BCE .set L357,0x0
1341: 1305 00019BCE L359:
1342: 1306 00019BCE 13 ff10 jbr L360
1343: 1307 00019BD1 .data
1344: 1308 00000d28 * .text
1345: 1309 00019BD1 00 .align 1
1346: 1310 00019BD2 .globl _divd_er_halt
1347: 1311 00019BD2 _divd_er_halt:
1348: 1312 00019BD2 0000 .word L367
1349: 1313 00019BD4 #
1350: 1314 00019BD4 #
1351: 1315 00019BD4 #
1352: 1316 00019BD4 # /**************************************************************************
1353: 1317 00019BD4 # *
1354: 1318 00019BD4 # * HALT ON ERROR ROUTINE
1355: 1319 00019BD4 # *
1356: 1320 00019BD4 # **************************************************************************/
1357: 1321 00019BD4 # divd_er_halt( halt_code )
1358: 1322 00019BD4 # int halt_code;
1359: 1323 00019BD4 # {
1360: 1324 00019BD4 13 0123 jbr L369
1361: 1325 00019BD7 L370:
1362: 1326 00019BD7 # sgl_value_1 = dbl_ld_acc.m;
1363: 1327 00019BD7 0d effffff3fb effffff3f6 movl _dbl_ld_acc,_sgl_value_1
1364: 1328 00019BE2 # sgl_value_2 = dbl_ld_acc.l;
1365: 1329 00019BE2 0d effffff3f4 effffff3eb movl _dbl_ld_acc+4,_sgl_value_2
1366: 1330 00019BED # sgl_value_3 = dbl_value_1.m;
1367: 1331 00019BED 0d effffff3e5 effffff3e0 movl _dbl_value_1,_sgl_value_3
1368: 1332 00019BF8 # sgl_value_4 = dbl_value_1.l;
1369: 1333 00019BF8 0d effffff3de effffff3d5 movl _dbl_value_1+4,_sgl_value_4
1370: 1334 00019C03 # sgl_value_5 = dbl_st_acc.m;
1371: 1335 00019C03 0d effffff3cf effffff3ca movl _dbl_st_acc,_sgl_value_5
1372: 1336 00019C0E # sgl_value_6 = dbl_st_acc.l;
1373: 1337 00019C0E 0d effffff3c8 effffff3bf movl _dbl_st_acc+4,_sgl_value_6
1374: 1338 00019C19 # sgl_dummy1 = halt_code; /* get the error type */
1375: 1339 00019C19 0d ad04 effffff3b7 movl 4(fp),_sgl_dummy1
1376: 1340 00019C21 # asm("movl _test_no,r0"); /* r0 = test number */
1377: 1341 00019C21 0d effffff3b1 50 movl _test_no,r0
1378: 1342 00019C28 # asm("movl _subtest,r1"); /* r1 = subtest number */
1379: 1343 00019C28 0d effffff3aa 51 movl _subtest,r1
1380: 1344 00019C2F # asm("movl _sgl_dummy1,r2"); /* r2 = error code */
1381: 1345 00019C2F 0d effffff3a3 52 movl _sgl_dummy1,r2
1382: 1346 00019C36 # asm("movl _cycle,r3"); /* r3 = cycle count */
1383: 1347 00019C36 0d effffff39c 53 movl _cycle,r3
1384: 1348 00019C3D # asm("movl _sgl_value_1,r4"); /* r4 = MS operand 1 */
1385: 1349 00019C3D 0d effffff395 54 movl _sgl_value_1,r4
1386: 1350 00019C44 # asm("movl _sgl_value_2,r5"); /* r5 = LS operand 1 */
1387: 1351 00019C44 0d effffff38e 55 movl _sgl_value_2,r5
1388: 1352 00019C4B # asm("movl _sgl_value_3,r6"); /* r6 = MS operand 2 */
1389: 1353 00019C4B 0d effffff387 56 movl _sgl_value_3,r6
1390: 1354 00019C52 # asm("movl _sgl_value_4,r7"); /* r7 = LS operand 2 */
1391: 1355 00019C52 0d effffff380 57 movl _sgl_value_4,r7
1392: 1356 00019C59 # asm("movl _sgl_value_5,r8"); /* r8 = MS stored */
1393: 1357 00019C59 0d effffff379 58 movl _sgl_value_5,r8
1394: 1358 00019C60 # asm("movl _sgl_value_6,r9"); /* r9 = LS stored */
1395: 1359 00019C60 0d effffff372 59 movl _sgl_value_6,r9
1396: 1360 00019C67 # if( halt_code == BAD_ACC_HLT ) {
1397: 1361 00019C67 1d ad04 01 cmpl 4(fp),$1
1398: 1362 00019C6B 21 2d jneq L371
1399: 1363 00019C6D # sgl_value_1 = dbl_expected.m;
1400: 1364 00019C6D 0d effffff365 effffff360 movl _dbl_expected,_sgl_value_1
1401: 1365 00019C78 # sgl_value_2 = dbl_expected.l;
1402: 1366 00019C78 0d effffff35e effffff355 movl _dbl_expected+4,_sgl_value_2
1403: 1367 00019C83 # asm("movl _sgl_value_1,r10"); /* r10 = MS expected */
1404: 1368 00019C83 0d effffff34f 5a movl _sgl_value_1,r10
1405: 1369 00019C8A # asm("movl _sgl_value_2,r11"); /* r11 = LS expected */
1406: 1370 00019C8A 0d effffff348 5b movl _sgl_value_2,r11
1407: 1371 00019C91 # asm("movl _index2,r12"); /* r12 = data index */
1408: 1372 00019C91 0d effffff341 5c movl _index2,r12
1409: 1373 00019C98 # } else
1410: 1374 00019C98 11 5e jbr L372
1411: 1375 00019C9A L371:
1412: 1376 00019C9A # if( halt_code == BAD_REG_HLT ) {
1413: 1377 00019C9A 1d ad04 02 cmpl 4(fp),$2
1414: 1378 00019C9E 21 3d jneq L373
1415: 1379 00019CA0 # sgl_dummy1 = load_regs[index2];
1416: 1380 00019CA0 0d effffff332 50 movl _index2,r0
1417: 1381 00019CA7 0d 40effffff32a movl _load_regs[r0],_sgl_dummy1
1418: effffff325
1419: 1382 00019CB3 # sgl_dummy2 = store_regs[index2];
1420: 1383 00019CB3 0d effffff31f 50 movl _index2,r0
1421: 1384 00019CBA 0d 40effffff317 movl _store_regs[r0],_sgl_dummy2
1422: effffff312
1423: 1385 00019CC6 # asm("movl _index2,r10"); /* r10 = bad register # */
1424: 1386 00019CC6 0d effffff30c 5a movl _index2,r10
1425: 1387 00019CCD # asm("movl _sgl_dummy2,r11"); /* r11 = actual value */
1426: 1388 00019CCD 0d effffff305 5b movl _sgl_dummy2,r11
1427: 1389 00019CD4 # asm("movl _sgl_dummy1,r12"); /* r12 = expected value */
1428: 1390 00019CD4 0d effffff2fe 5c movl _sgl_dummy1,r12
1429: 1391 00019CDB # } else
1430: 1392 00019CDB 11 1b jbr L374
1431: 1393 00019CDD L373:
1432: 1394 00019CDD # if( halt_code == BAD_PSL_HLT ) {
1433: 1395 00019CDD 1d ad04 03 cmpl 4(fp),$3
1434: 1396 00019CE1 21 15 jneq L375
1435: 1397 00019CE3 # asm("movl _init_psl,r10"); /* r10 = initial PSL */
1436: 1398 00019CE3 0d effffff2ef 5a movl _init_psl,r10
1437: 1399 00019CEA # asm("movl _psl_val,r11"); /* r11 = final PSL */
1438: 1400 00019CEA 0d effffff2e8 5b movl _psl_val,r11
1439: 1401 00019CF1 # asm("movl _exp_psl,r12"); /* r12 = expected PSL */
1440: 1402 00019CF1 0d effffff2e1 5c movl _exp_psl,r12
1441: 1403 00019CF8 # };
1442: 1404 00019CF8 L375:
1443: 1405 00019CF8 L374:
1444: 1406 00019CF8 L372:
1445: 1407 00019CF8 # asm("halt"); /* HALT ... */
1446: 1408 00019CF8 00 halt
1447: 1409 00019CF9 # }
1448: 1410 00019CF9 40 ret#2
1449: 1411 00019CFA .set L367,0x0
1450: 1412 00019CFA L369:
1451: 1413 00019CFA 13 feda jbr L370
1452: 1414 00019CFD .data
1453: 1414 00032CD5 .data
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