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Up to [Power 6/32 Unix Tahoe 4.2BSD] / cci / d / macro4|
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Power 6/32 Unix version 1.21
1 00000000 LL0:
2 00000000 .data
3 00000d28 * .text
4 00000000 .align 1
5 00000000 .globl _divd
6 00000000 _divd:
7 00018FD8 0000 .word L215
8 00018FDA #
9 00018FDA #
10 00018FDA # #include "fpp_defs.h"
11 00018FDA #
12 00018FDA #
13 00018FDA # /*****************************************************************************
14 00018FDA # *
15 00018FDA # * DIVD - DOUBLE PRECISION FLOATING POINT DIVIDE TEST
16 00018FDA # *
17 00018FDA # *****************************************************************************/
18 00018FDA # divd()
19 00018FDA # {
20 00018FDA 11 7a jbr L217
21 00018FDC L218:
22 00018FDC # asm(".globl _divd_t");
23 00018FDC .globl _divd_t
24 00018FDC # asm("_divd_t:"); /* entry address */
25 00018FDC _divd_t:
26 00018FDC # if( (cycle == 1) && (prt_hdrs) ) /* print headers on 1st cycle */
27 00018FDC 1d effffffff6 01 cmpl _cycle,$1
28 00018FE3 21 15 jneq L219
29 00018FE5 5d efffffffed tstl _prt_hdrs
30 00018FEB 31 0d jeql L219
31 00018FED # writes(" DIVD");
32 00018FED .data 1
33 00000d28 * L221:
34 00000d28 * 204449564400 .ascii " DIVD\0"
35 00000d2e * .text
36 00018FED dd 8f00000d28 pushl $L221
37 00018FF3 fe 08 efffffffde callf $8,_writes
38 00018FFA # divd_1(); /* div through a register */
39 00018FFA L219:
40 00018FFA fe 04 ef00000057 callf $4,_divd_1
41 00019001 # divd_2(); /* div through the cache */
42 00019001 fe 04 ef000001b2 callf $4,_divd_2
43 00019008 # divd_3(); /* wait 1 NOP before storeing */
44 00019008 fe 04 ef000002f9 callf $4,_divd_3
45 0001900F # for( nop_cnt = 3; nop_cnt > 0; nop_cnt-- )
46 0001900F 0d 03 efffffffc2 movl $3,_nop_cnt
47 00019016 L227:
48 00019016 5d efffffffbc tstl _nop_cnt
49 0001901C 51 15 jleq L226
50 0001901E # divd_3(nop_cnt); /* wait 6 ... 2 NOPs */
51 0001901E dd efffffffb4 pushl _nop_cnt
52 00019024 fe 08 ef000002dd callf $8,_divd_3
53 0001902B L225:
54 0001902B 7d efffffffa7 decl _nop_cnt
55 00019031 11 e3 jbr L227
56 00019033 L226:
57 00019033 # divd_4(); /* wait 3 NOPs */
58 00019033 fe 04 ef00000456 callf $4,_divd_4
59 0001903A # divd_5(); /* wait 1 NOP before storing */
60 0001903A fe 04 ef000005a1 callf $4,_divd_5
61 00019041 # divd_6(); /* register stability test */
62 00019041 fe 04 ef000006ea callf $4,_divd_6
63 00019048 # divd_7(); /* PSL stability test */
64 00019048 fe 04 ef000008b3 callf $4,_divd_7
65 0001904F # asm("jmp *return"); /* return to the test monitor */
66 0001904F 71 ffffffff83 jmp *return
67 00019055 # }
68 00019055 40 ret#2
69 00019056 .set L215,0x0
70 00019056 L217:
71 00019056 11 84 jbr L218
72 00019058 .data
73 00000d28 * .text
74 00019058 .align 1
75 00019058 .globl _divd_1
76 00019058 _divd_1:
77 00019058 0000 .word L232
78 0001905A #
79 0001905A #
80 0001905A #
81 0001905A # /************************************************************************
82 0001905A # *
83 0001905A # * SUBTEST 1 - divide through a register
84 0001905A # *
85 0001905A # ************************************************************************/
86 0001905A # divd_1()
87 0001905A # {
88 0001905A 13 015a jbr L234
89 0001905D L235:
90 0001905D # force_loop = FALSE;
91 0001905D 4d efffffff75 clrl _force_loop
92 00019063 # subtest = 1;
93 00019063 0d 01 efffffff6e movl $1,_subtest
94 0001906A # for( index = 0; index < max_divd_1_index; index++ ) {
95 0001906A 4d efffffff68 clrl _index
96 00019070 L238:
97 00019070 1d efffffff62 efffffff5d cmpl _index,_max_divd_1_index
98 0001907B 91 03 13 0136 jgeq L237
99 00019080 # dbl_ld_acc = divd_1_data[index].op_1; /* get operand 1 */
100 00019080 5c 18 efffffff51 50 mull3 $24,_index,r0
101 00019088 0c 8f00000000 50 addl2 $_divd_1_data,r0
102 0001908F 0d a004 efffffff45 movl 4(r0),_dbl_ld_acc+4
103 00019097 0d 60 efffffff3a movl (r0),_dbl_ld_acc
104 0001909E # dbl_value_1 = divd_1_data[index].op_2; /* get operand 2 */
105 0001909E 5c 18 efffffff33 50 mull3 $24,_index,r0
106 000190A6 0c 8f00000008 50 addl2 $_divd_1_data+8,r0
107 000190AD 0d a004 efffffff27 movl 4(r0),_dbl_value_1+4
108 000190B5 0d 60 efffffff1c movl (r0),_dbl_value_1
109 000190BC # dbl_expected = divd_1_data[index].exp; /* get expected result */
110 000190BC 5c 18 efffffff15 50 mull3 $24,_index,r0
111 000190C4 0c 8f00000010 50 addl2 $_divd_1_data+16,r0
112 000190CB 0d a004 efffffff09 movl 4(r0),_dbl_expected+4
113 000190D3 0d 60 effffffefe movl (r0),_dbl_expected
114 000190DA # /*
115 000190DA # * If LOOP ON ERROR is set, this is the loop for this subtest.
116 000190DA # * The force loop flag is set after the first error.
117 000190DA # */
118 000190DA # asm("_divd_1_lp1:");
119 000190DA _divd_1_lp1:
120 000190DA # asm("movl _dbl_ld_acc,r2"); /* move operand 1 to r2/r3 */
121 000190DA 0d effffffef8 52 movl _dbl_ld_acc,r2
122 000190E1 # asm("movl _dbl_ld_acc+4,r3");
123 000190E1 0d effffffef5 53 movl _dbl_ld_acc+4,r3
124 000190E8 # asm("movl _dbl_value_1,r4"); /* move operand 2 to r4/r5 */
125 000190E8 0d effffffeea 54 movl _dbl_value_1,r4
126 000190EF # asm("movl _dbl_value_1+4,r5");
127 000190EF 0d effffffee7 55 movl _dbl_value_1+4,r5
128 000190F6 # asm("ldd r2"); /* load the 1st operand */
129 000190F6 07 52 ldd r2
130 000190F8 # asm("divd r4"); /* divide the 2nd operand */
131 000190F8 f7 54 divd r4
132 000190FA # asm("std _dbl_st_acc"); /* store the result */
133 000190FA 27 effffffed8 std _dbl_st_acc
134 00019100 # if( force_loop )
135 00019100 5d effffffed2 tstl _force_loop
136 00019106 31 02 jeql L239
137 00019108 # asm("brb _divd_1_lp1");; /* loop on the error */
138 00019108 11 d0 brb _divd_1_lp1
139 0001910A L239:
140 0001910A # /*
141 0001910A # * end error loop - test the results
142 0001910A # */
143 0001910A # if( (dbl_st_acc.m != dbl_expected.m) || /* verify the results */
144 0001910A # (dbl_st_acc.l != dbl_expected.l) ) {
145 0001910A 1d effffffec8 effffffec3 cmpl _dbl_st_acc,_dbl_expected
146 00019115 21 10 jneq L9999
147 00019117 1d effffffebf effffffeba cmpl _dbl_st_acc+4,_dbl_expected+4
148 00019122 21 03 13 0086 jeql L240
149 00019127 L9999:
150 00019127 # errcnt++; /* bump the error count */
151 00019127 6d effffffeab incl _errcnt
152 0001912D # if( prt_error ) {
153 0001912D 5d effffffea5 tstl _prt_error
154 00019133 31 55 jeql L241
155 00019135 # writes(" \n"); /* start a new print line */
156 00019135 .data 1
157 00000d2e * L242:
158 00000d2e * 200A00 .ascii " \12\0"
159 00000d31 * .text
160 00019135 dd 8f00000d2e pushl $L242
161 0001913B fe 08 effffffe96 callf $8,_writes
162 00019142 # writes("cycle: ");
163 00019142 .data 1
164 00000d31 * L243:
165 00000d31 * 6379636C653A2000 .ascii "cycle: \0"
166 00000d39 * .text
167 00019142 dd 8f00000d31 pushl $L243
168 00019148 fe 08 effffffe89 callf $8,_writes
169 0001914F # writed( cycle );
170 0001914F dd effffffe83 pushl _cycle
171 00019155 fe 08 effffffe7c callf $8,_writed
172 0001915C # writes(" DIVD test ");
173 0001915C .data 1
174 00000d39 * L245:
175 00000d39 * 2020444956442074657374200 .ascii " DIVD test \0"
0
176 00000d46 * .text
177 0001915C dd 8f00000d39 pushl $L245
178 00019162 fe 08 effffffe6f callf $8,_writes
179 00019169 # writed( test_no );
180 00019169 dd effffffe69 pushl _test_no
181 0001916F fe 08 effffffe62 callf $8,_writed
182 00019176 # writes(", subtest 1 (Reg. Data) - BAD FINAL ACC\n");
183 00019176 .data 1
184 00000d46 * L246:
185 00000d46 * 2C20737562746573742031202 .ascii ", subtest 1 (Reg. Data) - BAD FINAL ACC\12\0"
85265672E204461746129202D
204241442046494E414C20414
3430A00
186 00000d6f * .text
187 00019176 dd 8f00000d46 pushl $L246
188 0001917C fe 08 effffffe55 callf $8,_writes
189 00019183 # print_divd_data();
190 00019183 fe 04 ef00000952 callf $4,_print_divd_data
191 0001918A # }
192 0001918A # if( halt_flg )
193 0001918A L241:
194 0001918A 5d effffffe48 tstl _halt_flg
195 00019190 31 09 jeql L248
196 00019192 # divd_er_halt( BAD_ACC_HLT ); /* halt on the error */
197 00019192 dd 01 pushl $1
198 00019194 fe 08 ef00000a37 callf $8,_divd_er_halt
199 0001919B # if( loop_on_err ) {
200 0001919B L248:
201 0001919B 5d effffffe37 tstl _loop_on_err
202 000191A1 31 0a jeql L250
203 000191A3 # force_loop = TRUE; /* set the force loop flag */
204 000191A3 0d 01 effffffe2e movl $1,_force_loop
205 000191AA # asm("brw _divd_1_lp1");; /* and loop on the error */
206 000191AA 13 ff2d brw _divd_1_lp1
207 000191AD # } /* end of loop on error */
208 000191AD # } /* end of compare error */
209 000191AD L250:
210 000191AD # } /* end of WHILE loop */
211 000191AD L240:
212 000191AD L236:
213 000191AD 6d effffffe25 incl _index
214 000191B3 13 feba jbr L238
215 000191B6 L237:
216 000191B6 # } /* end of subtest 1 */
217 000191B6 40 ret#2
218 000191B7 .set L232,0x0
219 000191B7 L234:
220 000191B7 13 fea3 jbr L235
221 000191BA .data
222 00000d28 * .text
223 000191BA .align 1
224 000191BA .globl _divd_2
225 000191BA _divd_2:
226 000191BA 0000 .word L251
227 000191BC #
228 000191BC #
229 000191BC #
230 000191BC # /************************************************************************
231 000191BC # *
232 000191BC # * SUBTEST 2 - divide through memory
233 000191BC # *
234 000191BC # ************************************************************************/
235 000191BC # divd_2()
236 000191BC # {
237 000191BC 13 0146 jbr L253
238 000191BF L254:
239 000191BF # force_loop = FALSE;
240 000191BF 4d effffffe13 clrl _force_loop
241 000191C5 # subtest = 2;
242 000191C5 0d 02 effffffe0c movl $2,_subtest
243 000191CC # for( index = 0; index < max_divd_1_index; index++ ) {
244 000191CC 4d effffffe06 clrl _index
245 000191D2 L257:
246 000191D2 1d effffffe00 effffffdfb cmpl _index,_max_divd_1_index
247 000191DD 91 03 13 0122 jgeq L256
248 000191E2 # dbl_ld_acc = divd_1_data[index].op_1; /* get operand 1 */
249 000191E2 5c 18 effffffdef 50 mull3 $24,_index,r0
250 000191EA 0c 8f00000000 50 addl2 $_divd_1_data,r0
251 000191F1 0d a004 effffffde3 movl 4(r0),_dbl_ld_acc+4
252 000191F9 0d 60 effffffdd8 movl (r0),_dbl_ld_acc
253 00019200 # dbl_value_1 = divd_1_data[index].op_2; /* get operand 2 */
254 00019200 5c 18 effffffdd1 50 mull3 $24,_index,r0
255 00019208 0c 8f00000008 50 addl2 $_divd_1_data+8,r0
256 0001920F 0d a004 effffffdc5 movl 4(r0),_dbl_value_1+4
257 00019217 0d 60 effffffdba movl (r0),_dbl_value_1
258 0001921E # dbl_expected = divd_1_data[index].exp; /* get expected result */
259 0001921E 5c 18 effffffdb3 50 mull3 $24,_index,r0
260 00019226 0c 8f00000010 50 addl2 $_divd_1_data+16,r0
261 0001922D 0d a004 effffffda7 movl 4(r0),_dbl_expected+4
262 00019235 0d 60 effffffd9c movl (r0),_dbl_expected
263 0001923C # /*
264 0001923C # * If LOOP ON ERROR is set, this is the loop for this subtest.
265 0001923C # * The force loop flag is set after the first error.
266 0001923C # */
267 0001923C # asm("_divd_2_lp1:");
268 0001923C _divd_2_lp1:
269 0001923C # asm("ldd _dbl_ld_acc"); /* load the 1st operand */
270 0001923C 07 effffffd96 ldd _dbl_ld_acc
271 00019242 # asm("divd _dbl_value_1"); /* divide the 2nd operand */
272 00019242 f7 effffffd90 divd _dbl_value_1
273 00019248 # asm("std _dbl_st_acc"); /* store the result */
274 00019248 27 effffffd8a std _dbl_st_acc
275 0001924E # if( force_loop )
276 0001924E 5d effffffd84 tstl _force_loop
277 00019254 31 02 jeql L258
278 00019256 # asm("brb _divd_2_lp1");; /* loop on the error */
279 00019256 11 e4 brb _divd_2_lp1
280 00019258 L258:
281 00019258 # /*
282 00019258 # * end error loop - test the results
283 00019258 # */
284 00019258 # if( (dbl_st_acc.m != dbl_expected.m) || /* verify the results */
285 00019258 # (dbl_st_acc.l != dbl_expected.l) ) {
286 00019258 1d effffffd7a effffffd75 cmpl _dbl_st_acc,_dbl_expected
287 00019263 21 10 jneq L9998
288 00019265 1d effffffd71 effffffd6c cmpl _dbl_st_acc+4,_dbl_expected+4
289 00019270 21 03 13 0086 jeql L259
290 00019275 L9998:
291 00019275 # errcnt++; /* bump the error count */
292 00019275 6d effffffd5d incl _errcnt
293 0001927B # if( prt_error ) {
294 0001927B 5d effffffd57 tstl _prt_error
295 00019281 31 55 jeql L260
296 00019283 # writes(" \n"); /* start a new print line */
297 00019283 .data 1
298 00000d6f * L261:
299 00000d6f * 200A00 .ascii " \12\0"
300 00000d72 * .text
301 00019283 dd 8f00000d6f pushl $L261
302 00019289 fe 08 effffffd48 callf $8,_writes
303 00019290 # writes("cycle: ");
304 00019290 .data 1
305 00000d72 * L262:
306 00000d72 * 6379636C653A2000 .ascii "cycle: \0"
307 00000d7a * .text
308 00019290 dd 8f00000d72 pushl $L262
309 00019296 fe 08 effffffd3b callf $8,_writes
310 0001929D # writed( cycle );
311 0001929D dd effffffd35 pushl _cycle
312 000192A3 fe 08 effffffd2e callf $8,_writed
313 000192AA # writes(" DIVD test ");
314 000192AA .data 1
315 00000d7a * L263:
316 00000d7a * 2020444956442074657374200 .ascii " DIVD test \0"
0
317 00000d87 * .text
318 000192AA dd 8f00000d7a pushl $L263
319 000192B0 fe 08 effffffd21 callf $8,_writes
320 000192B7 # writed( test_no );
321 000192B7 dd effffffd1b pushl _test_no
322 000192BD fe 08 effffffd14 callf $8,_writed
323 000192C4 # writes(", subtest 2 (Cache Data) - BAD FINAL ACC\n");
324 000192C4 .data 1
325 00000d87 * L264:
326 00000d87 * 2C20737562746573742032202 .ascii ", subtest 2 (Cache Data) - BAD FINAL ACC\12\0"
8436163686520446174612920
2D204241442046494E414C204
143430A00
327 00000db1 * .text
328 000192C4 dd 8f00000d87 pushl $L264
329 000192CA fe 08 effffffd07 callf $8,_writes
330 000192D1 # print_divd_data();
331 000192D1 fe 04 ef00000804 callf $4,_print_divd_data
332 000192D8 # }
333 000192D8 # if( halt_flg )
334 000192D8 L260:
335 000192D8 5d effffffcfa tstl _halt_flg
336 000192DE 31 09 jeql L265
337 000192E0 # divd_er_halt( BAD_ACC_HLT ); /* halt on the error */
338 000192E0 dd 01 pushl $1
339 000192E2 fe 08 ef000008e9 callf $8,_divd_er_halt
340 000192E9 # if( loop_on_err ) {
341 000192E9 L265:
342 000192E9 5d effffffce9 tstl _loop_on_err
343 000192EF 31 0a jeql L266
344 000192F1 # force_loop = TRUE; /* set the force loop flag */
345 000192F1 0d 01 effffffce0 movl $1,_force_loop
346 000192F8 # asm("brw _divd_2_lp1");; /* and loop on the error */
347 000192F8 13 ff41 brw _divd_2_lp1
348 000192FB # } /* end of loop on error */
349 000192FB # } /* end of compare error */
350 000192FB L266:
351 000192FB # } /* end of WHILE loop */
352 000192FB L259:
353 000192FB L255:
354 000192FB 6d effffffcd7 incl _index
355 00019301 13 fece jbr L257
356 00019304 L256:
357 00019304 # } /* end of subtest 2 */
358 00019304 40 ret#2
359 00019305 .set L251,0x0
360 00019305 L253:
361 00019305 13 feb7 jbr L254
362 00019308 .data
363 00000d28 * .text
364 00019308 .align 1
365 00019308 .globl _divd_3
366 00019308 _divd_3:
367 00019308 0000 .word L267
368 0001930A #
369 0001930A #
370 0001930A #
371 0001930A # /****************************************************************************
372 0001930A # *
373 0001930A # * SUBTEST 3 - Wait 2n NOPs before storing the results
374 0001930A # *
375 0001930A # ****************************************************************************/
376 0001930A # divd_3( count )
377 0001930A # int count; /* wait "count" * 2 NOPs */
378 0001930A # {
379 0001930A 13 0180 jbr L269
380 0001930D L270:
381 0001930D # force_loop = FALSE;
382 0001930D 4d effffffcc5 clrl _force_loop
383 00019313 # subtest = 3;
384 00019313 0d 03 effffffcbe movl $3,_subtest
385 0001931A # sgl_dummy2 = count; /* get the NOP count */
386 0001931A 0d ad04 effffffcb6 movl 4(fp),_sgl_dummy2
387 00019322 # for( index = 0; index < max_divd_1_index; index++ ) {
388 00019322 4d effffffcb0 clrl _index
389 00019328 L273:
390 00019328 1d effffffcaa effffffca5 cmpl _index,_max_divd_1_index
391 00019333 91 03 13 0154 jgeq L272
392 00019338 # dbl_ld_acc = divd_1_data[index].op_1; /* get operand 1 */
393 00019338 5c 18 effffffc99 50 mull3 $24,_index,r0
394 00019340 0c 8f00000000 50 addl2 $_divd_1_data,r0
395 00019347 0d a004 effffffc8d movl 4(r0),_dbl_ld_acc+4
396 0001934F 0d 60 effffffc82 movl (r0),_dbl_ld_acc
397 00019356 # dbl_value_1 = divd_1_data[index].op_2; /* get operand 2 */
398 00019356 5c 18 effffffc7b 50 mull3 $24,_index,r0
399 0001935E 0c 8f00000008 50 addl2 $_divd_1_data+8,r0
400 00019365 0d a004 effffffc6f movl 4(r0),_dbl_value_1+4
401 0001936D 0d 60 effffffc64 movl (r0),_dbl_value_1
402 00019374 # dbl_expected = divd_1_data[index].exp; /* get expected result */
403 00019374 5c 18 effffffc5d 50 mull3 $24,_index,r0
404 0001937C 0c 8f00000010 50 addl2 $_divd_1_data+16,r0
405 00019383 0d a004 effffffc51 movl 4(r0),_dbl_expected+4
406 0001938B 0d 60 effffffc46 movl (r0),_dbl_expected
407 00019392 # /*
408 00019392 # * If LOOP ON ERROR is set, this is the loop for this subtest.
409 00019392 # * The force loop flag is set after the first error.
410 00019392 # */
411 00019392 # asm("_divd_3_lp1:");
412 00019392 _divd_3_lp1:
413 00019392 # asm("movl _sgl_dummy2,r0"); /* set the NOP count */
414 00019392 0d effffffc40 50 movl _sgl_dummy2,r0
415 00019399 # asm("ldd _dbl_ld_acc"); /* load the 1st operand */
416 00019399 07 effffffc39 ldd _dbl_ld_acc
417 0001939F # asm("nop"); /* delay */
418 0001939F 10 nop
419 000193A0 # asm("divd _dbl_value_1"); /* divide the 2nd operand */
420 000193A0 f7 effffffc32 divd _dbl_value_1
421 000193A6 # asm("1:");
422 000193A6 1:
423 000193A6 # asm("decl r0"); /* decrement the NOP count */
424 000193A6 7d 50 decl r0
425 000193A8 # asm("bneq 1b"); /* till the count = 0 */
426 000193A8 21 fc bneq 1b
427 000193AA # asm("std _dbl_st_acc"); /* store the result */
428 000193AA 27 effffffc28 std _dbl_st_acc
429 000193B0 # if( force_loop )
430 000193B0 5d effffffc22 tstl _force_loop
431 000193B6 31 02 jeql L274
432 000193B8 # asm("brb _divd_3_lp1");; /* loop on the error */
433 000193B8 11 d8 brb _divd_3_lp1
434 000193BA L274:
435 000193BA # /*
436 000193BA # * end error loop - test the results
437 000193BA # */
438 000193BA # if( (dbl_st_acc.m != dbl_expected.m) || /* verify the results */
439 000193BA # (dbl_st_acc.l != dbl_expected.l) ) {
440 000193BA 1d effffffc18 effffffc13 cmpl _dbl_st_acc,_dbl_expected
441 000193C5 21 10 jneq L9997
442 000193C7 1d effffffc0f effffffc0a cmpl _dbl_st_acc+4,_dbl_expected+4
443 000193D2 21 03 13 00ac jeql L275
444 000193D7 L9997:
445 000193D7 # errcnt++; /* bump the error count */
446 000193D7 6d effffffbfb incl _errcnt
447 000193DD # if( prt_error ) {
448 000193DD 5d effffffbf5 tstl _prt_error
449 000193E3 31 7b jeql L276
450 000193E5 # writes(" \n"); /* start a new print line */
451 000193E5 .data 1
452 00000db1 * L277:
453 00000db1 * 200A00 .ascii " \12\0"
454 00000db4 * .text
455 000193E5 dd 8f00000db1 pushl $L277
456 000193EB fe 08 effffffbe6 callf $8,_writes
457 000193F2 # writes("cycle: ");
458 000193F2 .data 1
459 00000db4 * L278:
460 00000db4 * 6379636C653A2000 .ascii "cycle: \0"
461 00000dbc * .text
462 000193F2 dd 8f00000db4 pushl $L278
463 000193F8 fe 08 effffffbd9 callf $8,_writes
464 000193FF # writed( cycle );
465 000193FF dd effffffbd3 pushl _cycle
466 00019405 fe 08 effffffbcc callf $8,_writed
467 0001940C # writes(" DIVD test ");
468 0001940C .data 1
469 00000dbc * L279:
470 00000dbc * 2020444956442074657374200 .ascii " DIVD test \0"
0
471 00000dc9 * .text
472 0001940C dd 8f00000dbc pushl $L279
473 00019412 fe 08 effffffbbf callf $8,_writes
474 00019419 # writed( test_no );
475 00019419 dd effffffbb9 pushl _test_no
476 0001941F fe 08 effffffbb2 callf $8,_writed
477 00019426 # writes(", subtest 3 (wait ");
478 00019426 .data 1
479 00000dc9 * L280:
480 00000dc9 * 2C20737562746573742033202 .ascii ", subtest 3 (wait \0"
8776169742000
481 00000ddc * .text
482 00019426 dd 8f00000dc9 pushl $L280
483 0001942C fe 08 effffffba5 callf $8,_writes
484 00019433 # sgl_dummy1 = 2*count;
485 00019433 48 01 ad04 50 shll $1,4(fp),r0
486 00019438 0d 50 effffffb99 movl r0,_sgl_dummy1
487 0001943F # writed( sgl_dummy1 ); /* write the NOP count */
488 0001943F dd effffffb93 pushl _sgl_dummy1
489 00019445 fe 08 effffffb8c callf $8,_writed
490 0001944C # writes(" NOPs) - BAD FINAL ACC\n");
491 0001944C .data 1
492 00000ddc * L281:
493 00000ddc * 204E4F507329202D204241442 .ascii " NOPs) - BAD FINAL ACC\12\0"
046494E414C204143430A00
494 00000df4 * .text
495 0001944C dd 8f00000ddc pushl $L281
496 00019452 fe 08 effffffb7f callf $8,_writes
497 00019459 # print_divd_data();
498 00019459 fe 04 ef0000067c callf $4,_print_divd_data
499 00019460 # }
500 00019460 # if( halt_flg )
501 00019460 L276:
502 00019460 5d effffffb72 tstl _halt_flg
503 00019466 31 09 jeql L282
504 00019468 # divd_er_halt( BAD_ACC_HLT ); /* halt on the error */
505 00019468 dd 01 pushl $1
506 0001946A fe 08 ef00000761 callf $8,_divd_er_halt
507 00019471 # if( loop_on_err ) {
508 00019471 L282:
509 00019471 5d effffffb61 tstl _loop_on_err
510 00019477 31 0a jeql L283
511 00019479 # force_loop = TRUE; /* set the force loop flag */
512 00019479 0d 01 effffffb58 movl $1,_force_loop
513 00019480 # asm("brw _divd_3_lp1");; /* and loop on the error */
514 00019480 13 ff0f brw _divd_3_lp1
515 00019483 # } /* end of loop on error */
516 00019483 # } /* end of compare error */
517 00019483 L283:
518 00019483 # } /* end of WHILE loop */
519 00019483 L275:
520 00019483 L271:
521 00019483 6d effffffb4f incl _index
522 00019489 13 fe9c jbr L273
523 0001948C L272:
524 0001948C # } /* end of subtest 3 */
525 0001948C 40 ret#2
526 0001948D .set L267,0x0
527 0001948D L269:
528 0001948D 13 fe7d jbr L270
529 00019490 .data
530 00000d28 * .text
531 00019490 .align 1
532 00019490 .globl _divd_4
533 00019490 _divd_4:
534 00019490 0000 .word L284
535 00019492 #
536 00019492 #
537 00019492 #
538 00019492 # /************************************************************************
539 00019492 # *
540 00019492 # * SUBTEST 4 - Wait 2 NOPs before storing the results
541 00019492 # *
542 00019492 # ************************************************************************/
543 00019492 # divd_4()
544 00019492 # {
545 00019492 13 0149 jbr L286
546 00019495 L287:
547 00019495 # force_loop = FALSE;
548 00019495 4d effffffb3d clrl _force_loop
549 0001949B # subtest = 4;
550 0001949B 0d 04 effffffb36 movl $4,_subtest
551 000194A2 # for( index = 0; index < max_divd_1_index; index++ ) {
552 000194A2 4d effffffb30 clrl _index
553 000194A8 L290:
554 000194A8 1d effffffb2a effffffb25 cmpl _index,_max_divd_1_index
555 000194B3 91 03 13 0125 jgeq L289
556 000194B8 # dbl_ld_acc = divd_1_data[index].op_1; /* get operand 1 */
557 000194B8 5c 18 effffffb19 50 mull3 $24,_index,r0
558 000194C0 0c 8f00000000 50 addl2 $_divd_1_data,r0
559 000194C7 0d a004 effffffb0d movl 4(r0),_dbl_ld_acc+4
560 000194CF 0d 60 effffffb02 movl (r0),_dbl_ld_acc
561 000194D6 # dbl_value_1 = divd_1_data[index].op_2; /* get operand 2 */
562 000194D6 5c 18 effffffafb 50 mull3 $24,_index,r0
563 000194DE 0c 8f00000008 50 addl2 $_divd_1_data+8,r0
564 000194E5 0d a004 effffffaef movl 4(r0),_dbl_value_1+4
565 000194ED 0d 60 effffffae4 movl (r0),_dbl_value_1
566 000194F4 # dbl_expected = divd_1_data[index].exp; /* get expected result */
567 000194F4 5c 18 effffffadd 50 mull3 $24,_index,r0
568 000194FC 0c 8f00000010 50 addl2 $_divd_1_data+16,r0
569 00019503 0d a004 effffffad1 movl 4(r0),_dbl_expected+4
570 0001950B 0d 60 effffffac6 movl (r0),_dbl_expected
571 00019512 # /*
572 00019512 # * If LOOP ON ERROR is set, this is the loop for this subtest.
573 00019512 # * The force loop flag is set after the first error.
574 00019512 # */
575 00019512 # asm("_divd_4_lp1:");
576 00019512 _divd_4_lp1:
577 00019512 # asm("ldd _dbl_ld_acc"); /* load the 1st operand */
578 00019512 07 effffffac0 ldd _dbl_ld_acc
579 00019518 # asm("nop"); /* delay */
580 00019518 10 nop
581 00019519 # asm("divd _dbl_value_1"); /* divide the 2nd operand */
582 00019519 f7 effffffab9 divd _dbl_value_1
583 0001951F # asm("nop"); /* delay before ... */
584 0001951F 10 nop
585 00019520 # asm("nop"); /* ... storing the result */
586 00019520 10 nop
587 00019521 # asm("std _dbl_st_acc"); /* store the result */
588 00019521 27 effffffab1 std _dbl_st_acc
589 00019527 # if( force_loop )
590 00019527 5d effffffaab tstl _force_loop
591 0001952D 31 02 jeql L291
592 0001952F # asm("brb _divd_4_lp1");; /* loop on the error */
593 0001952F 11 e1 brb _divd_4_lp1
594 00019531 L291:
595 00019531 # /*
596 00019531 # * end error loop - test the results
597 00019531 # */
598 00019531 # if( (dbl_st_acc.m != dbl_expected.m) || /* verify the results */
599 00019531 # (dbl_st_acc.l != dbl_expected.l) ) {
600 00019531 1d effffffaa1 effffffa9c cmpl _dbl_st_acc,_dbl_expected
601 0001953C 21 10 jneq L9996
602 0001953E 1d effffffa98 effffffa93 cmpl _dbl_st_acc+4,_dbl_expected+4
603 00019549 21 03 13 0086 jeql L292
604 0001954E L9996:
605 0001954E # errcnt++; /* bump the error count */
606 0001954E 6d effffffa84 incl _errcnt
607 00019554 # if( prt_error ) {
608 00019554 5d effffffa7e tstl _prt_error
609 0001955A 31 55 jeql L293
610 0001955C # writes(" \n"); /* start a new print line */
611 0001955C .data 1
612 00000df4 * L294:
613 00000df4 * 200A00 .ascii " \12\0"
614 00000df7 * .text
615 0001955C dd 8f00000df4 pushl $L294
616 00019562 fe 08 effffffa6f callf $8,_writes
617 00019569 # writes("cycle: ");
618 00019569 .data 1
619 00000df7 * L295:
620 00000df7 * 6379636C653A2000 .ascii "cycle: \0"
621 00000dff * .text
622 00019569 dd 8f00000df7 pushl $L295
623 0001956F fe 08 effffffa62 callf $8,_writes
624 00019576 # writed( cycle );
625 00019576 dd effffffa5c pushl _cycle
626 0001957C fe 08 effffffa55 callf $8,_writed
627 00019583 # writes(" DIVD test ");
628 00019583 .data 1
629 00000dff * L296:
630 00000dff * 2020444956442074657374200 .ascii " DIVD test \0"
0
631 00000e0c * .text
632 00019583 dd 8f00000dff pushl $L296
633 00019589 fe 08 effffffa48 callf $8,_writes
634 00019590 # writed( test_no );
635 00019590 dd effffffa42 pushl _test_no
636 00019596 fe 08 effffffa3b callf $8,_writed
637 0001959D # writes(", subtest 4 (2 NOPs) - BAD FINAL ACC\n");
638 0001959D .data 1
639 00000e0c * L297:
640 00000e0c * 2C20737562746573742034202 .ascii ", subtest 4 (2 NOPs) - BAD FINAL ACC\12\0"
832204E4F507329202D204241
442046494E414C204143430A0
0
641 00000e32 * .text
642 0001959D dd 8f00000e0c pushl $L297
643 000195A3 fe 08 effffffa2e callf $8,_writes
644 000195AA # print_divd_data();
645 000195AA fe 04 ef0000052b callf $4,_print_divd_data
646 000195B1 # }
647 000195B1 # if( halt_flg )
648 000195B1 L293:
649 000195B1 5d effffffa21 tstl _halt_flg
650 000195B7 31 09 jeql L298
651 000195B9 # divd_er_halt( BAD_ACC_HLT ); /* halt on the error */
652 000195B9 dd 01 pushl $1
653 000195BB fe 08 ef00000610 callf $8,_divd_er_halt
654 000195C2 # if( loop_on_err ) {
655 000195C2 L298:
656 000195C2 5d effffffa10 tstl _loop_on_err
657 000195C8 31 0a jeql L299
658 000195CA # force_loop = TRUE; /* set the force loop flag */
659 000195CA 0d 01 effffffa07 movl $1,_force_loop
660 000195D1 # asm("brw _divd_4_lp1");; /* and loop on the error */
661 000195D1 13 ff3e brw _divd_4_lp1
662 000195D4 # } /* end of loop on error */
663 000195D4 # } /* end of compare error */
664 000195D4 L299:
665 000195D4 # } /* end of WHILE loop */
666 000195D4 L292:
667 000195D4 L288:
668 000195D4 6d effffff9fe incl _index
669 000195DA 13 fecb jbr L290
670 000195DD L289:
671 000195DD # } /* end of subtest 4 */
672 000195DD 40 ret#2
673 000195DE .set L284,0x0
674 000195DE L286:
675 000195DE 13 feb4 jbr L287
676 000195E1 .data
677 00000d28 * .text
678 000195E1 00 .align 1
679 000195E2 .globl _divd_5
680 000195E2 _divd_5:
681 000195E2 0000 .word L300
682 000195E4 #
683 000195E4 #
684 000195E4 #
685 000195E4 # /************************************************************************
686 000195E4 # *
687 000195E4 # * SUBTEST 5 - Wait 1 NOP before storing the results
688 000195E4 # *
689 000195E4 # ************************************************************************/
690 000195E4 # divd_5()
691 000195E4 # {
692 000195E4 13 0148 jbr L302
693 000195E7 L303:
694 000195E7 # force_loop = FALSE;
695 000195E7 4d effffff9eb clrl _force_loop
696 000195ED # subtest = 5;
697 000195ED 0d 05 effffff9e4 movl $5,_subtest
698 000195F4 # for( index = 0; index < max_divd_1_index; index++ ) {
699 000195F4 4d effffff9de clrl _index
700 000195FA L306:
701 000195FA 1d effffff9d8 effffff9d3 cmpl _index,_max_divd_1_index
702 00019605 91 03 13 0124 jgeq L305
703 0001960A # dbl_ld_acc = divd_1_data[index].op_1; /* get operand 1 */
704 0001960A 5c 18 effffff9c7 50 mull3 $24,_index,r0
705 00019612 0c 8f00000000 50 addl2 $_divd_1_data,r0
706 00019619 0d a004 effffff9bb movl 4(r0),_dbl_ld_acc+4
707 00019621 0d 60 effffff9b0 movl (r0),_dbl_ld_acc
708 00019628 # dbl_value_1 = divd_1_data[index].op_2; /* get operand 2 */
709 00019628 5c 18 effffff9a9 50 mull3 $24,_index,r0
710 00019630 0c 8f00000008 50 addl2 $_divd_1_data+8,r0
711 00019637 0d a004 effffff99d movl 4(r0),_dbl_value_1+4
712 0001963F 0d 60 effffff992 movl (r0),_dbl_value_1
713 00019646 # dbl_expected = divd_1_data[index].exp; /* get expected result */
714 00019646 5c 18 effffff98b 50 mull3 $24,_index,r0
715 0001964E 0c 8f00000010 50 addl2 $_divd_1_data+16,r0
716 00019655 0d a004 effffff97f movl 4(r0),_dbl_expected+4
717 0001965D 0d 60 effffff974 movl (r0),_dbl_expected
718 00019664 # /*
719 00019664 # * If LOOP ON ERROR is set, this is the loop for this subtest.
720 00019664 # * The force loop flag is set after the first error.
721 00019664 # */
722 00019664 # asm("_divd_5_lp1:");
723 00019664 _divd_5_lp1:
724 00019664 # asm("ldd _dbl_ld_acc"); /* load the 1st operand */
725 00019664 07 effffff96e ldd _dbl_ld_acc
726 0001966A # asm("nop"); /* delay */
727 0001966A 10 nop
728 0001966B # asm("divd _dbl_value_1"); /* divide the 2nd operand */
729 0001966B f7 effffff967 divd _dbl_value_1
730 00019671 # asm("nop"); /* delay before storing */
731 00019671 10 nop
732 00019672 # asm("std _dbl_st_acc"); /* store the result */
733 00019672 27 effffff960 std _dbl_st_acc
734 00019678 # if( force_loop )
735 00019678 5d effffff95a tstl _force_loop
736 0001967E 31 02 jeql L307
737 00019680 # asm("brb _divd_5_lp1");; /* loop on the error */
738 00019680 11 e2 brb _divd_5_lp1
739 00019682 L307:
740 00019682 # /*
741 00019682 # * end error loop - test the results
742 00019682 # */
743 00019682 # if( (dbl_st_acc.m != dbl_expected.m) || /* verify the results */
744 00019682 # (dbl_st_acc.l != dbl_expected.l) ) {
745 00019682 1d effffff950 effffff94b cmpl _dbl_st_acc,_dbl_expected
746 0001968D 21 10 jneq L9995
747 0001968F 1d effffff947 effffff942 cmpl _dbl_st_acc+4,_dbl_expected+4
748 0001969A 21 03 13 0086 jeql L308
749 0001969F L9995:
750 0001969F # errcnt++; /* bump the error count */
751 0001969F 6d effffff933 incl _errcnt
752 000196A5 # if( prt_error ) {
753 000196A5 5d effffff92d tstl _prt_error
754 000196AB 31 55 jeql L309
755 000196AD # writes(" \n"); /* start a new print line */
756 000196AD .data 1
757 00000e32 * L310:
758 00000e32 * 200A00 .ascii " \12\0"
759 00000e35 * .text
760 000196AD dd 8f00000e32 pushl $L310
761 000196B3 fe 08 effffff91e callf $8,_writes
762 000196BA # writes("cycle: ");
763 000196BA .data 1
764 00000e35 * L311:
765 00000e35 * 6379636C653A2000 .ascii "cycle: \0"
766 00000e3d * .text
767 000196BA dd 8f00000e35 pushl $L311
768 000196C0 fe 08 effffff911 callf $8,_writes
769 000196C7 # writed( cycle );
770 000196C7 dd effffff90b pushl _cycle
771 000196CD fe 08 effffff904 callf $8,_writed
772 000196D4 # writes(" DIVD test ");
773 000196D4 .data 1
774 00000e3d * L312:
775 00000e3d * 2020444956442074657374200 .ascii " DIVD test \0"
0
776 00000e4a * .text
777 000196D4 dd 8f00000e3d pushl $L312
778 000196DA fe 08 effffff8f7 callf $8,_writes
779 000196E1 # writed( test_no );
780 000196E1 dd effffff8f1 pushl _test_no
781 000196E7 fe 08 effffff8ea callf $8,_writed
782 000196EE # writes(", subtest 5 (1 NOP) - BAD FINAL ACC\n");
783 000196EE .data 1
784 00000e4a * L313:
785 00000e4a * 2C20737562746573742035202 .ascii ", subtest 5 (1 NOP) - BAD FINAL ACC\12\0"
831204E4F5029202D20424144
2046494E414C204143430A00
786 00000e6f * .text
787 000196EE dd 8f00000e4a pushl $L313
788 000196F4 fe 08 effffff8dd callf $8,_writes
789 000196FB # print_divd_data();
790 000196FB fe 04 ef000003da callf $4,_print_divd_data
791 00019702 # }
792 00019702 # if( halt_flg )
793 00019702 L309:
794 00019702 5d effffff8d0 tstl _halt_flg
795 00019708 31 09 jeql L314
796 0001970A # divd_er_halt( BAD_ACC_HLT ); /* halt on the error */
797 0001970A dd 01 pushl $1
798 0001970C fe 08 ef000004bf callf $8,_divd_er_halt
799 00019713 # if( loop_on_err ) {
800 00019713 L314:
801 00019713 5d effffff8bf tstl _loop_on_err
802 00019719 31 0a jeql L315
803 0001971B # force_loop = TRUE; /* set the force loop flag */
804 0001971B 0d 01 effffff8b6 movl $1,_force_loop
805 00019722 # asm("brw _divd_5_lp1");; /* and loop on the error */
806 00019722 13 ff3f brw _divd_5_lp1
807 00019725 # } /* end of loop on error */
808 00019725 # } /* end of compare error */
809 00019725 L315:
810 00019725 # } /* end of WHILE loop */
811 00019725 L308:
812 00019725 L304:
813 00019725 6d effffff8ad incl _index
814 0001972B 13 fecc jbr L306
815 0001972E L305:
816 0001972E # } /* end of subtest 5 */
817 0001972E 40 ret#2
818 0001972F .set L300,0x0
819 0001972F L302:
820 0001972F 13 feb5 jbr L303
821 00019732 .data
822 00000d28 * .text
823 00019732 .align 1
824 00019732 .globl _divd_6
825 00019732 _divd_6:
826 00019732 0000 .word L316
827 00019734 #
828 00019734 #
829 00019734 #
830 00019734 # /************************************************************************
831 00019734 # *
832 00019734 # * SUBTEST 6 - Check for register corruption
833 00019734 # *
834 00019734 # ************************************************************************/
835 00019734 # divd_6()
836 00019734 # {
837 00019734 13 01c8 jbr L318
838 00019737 L319:
839 00019737 # force_loop = FALSE; /* clear force_loop flg */
840 00019737 4d effffff89b clrl _force_loop
841 0001973D # subtest = 6;
842 0001973D 0d 06 effffff894 movl $6,_subtest
843 00019744 # fill_reg_buf( load_regs ); /* get patterns for regs */
844 00019744 dd 8f00000000 pushl $_load_regs
845 0001974A fe 08 effffff887 callf $8,_fill_reg_buf
846 00019751 # index = 0;
847 00019751 4d effffff881 clrl _index
848 00019757 # dbl_ld_acc = divd_1_data[0].op_1; /* get operand 1 */
849 00019757 0d effffff87f effffff87a movl _divd_1_data+4,_dbl_ld_acc+4
850 00019762 0d effffff870 effffff86b movl _divd_1_data,_dbl_ld_acc
851 0001976D # dbl_value_1 = divd_1_data[0].op_2; /* get operand 2 */
852 0001976D 0d effffff871 effffff864 movl _divd_1_data+12,_dbl_value_1+4
853 00019778 0d effffff862 effffff855 movl _divd_1_data+8,_dbl_value_1
854 00019783 # dbl_expected = divd_1_data[0].exp; /* get expected result */
855 00019783 0d effffff863 effffff84e movl _divd_1_data+20,_dbl_expected+4
856 0001978E 0d effffff854 effffff83f movl _divd_1_data+16,_dbl_expected
857 00019799 # /*
858 00019799 # * If LOOP ON ERROR is set, this is the loop for this subtest.
859 00019799 # * The force loop flag is set after the first error.
860 00019799 # */
861 00019799 # asm("_divd_6_lp1:");
862 00019799 _divd_6_lp1:
863 00019799 # asm("ldd _dbl_ld_acc"); /* LOAD the accumulator */
864 00019799 07 effffff839 ldd _dbl_ld_acc
865 0001979F # asm("nop");
866 0001979F 10 nop
867 000197A0 # asm("loadr $0x1fff,_load_regs"); /* load regs 0 - 12 */
868 000197A0 ab 891fff effffff82f loadr $0x1fff,_load_regs
869 000197A9 # asm("nop");
870 000197A9 10 nop
871 000197AA # asm("divd _dbl_value_1"); /* do the divide */
872 000197AA f7 effffff828 divd _dbl_value_1
873 000197B0 # asm("nop");
874 000197B0 10 nop
875 000197B1 # asm("storer $0x1fff,_store_regs"); /* store regs 0 - 12 */
876 000197B1 bb 891fff effffff81e storer $0x1fff,_store_regs
877 000197BA # asm("std _dbl_st_acc"); /* save the accumulator */
878 000197BA 27 effffff818 std _dbl_st_acc
879 000197C0 # if( force_loop )
880 000197C0 5d effffff812 tstl _force_loop
881 000197C6 31 02 jeql L321
882 000197C8 # asm("brb _divd_6_lp1");; /* loop on the error */
883 000197C8 11 cf brb _divd_6_lp1
884 000197CA L321:
885 000197CA # /*
886 000197CA # * Now compare the stored register values to those that were loaded
887 000197CA # */
888 000197CA # index2 = 0;
889 000197CA 4d effffff808 clrl _index2
890 000197D0 # while( (load_regs[index2] == store_regs[index2]) && (index2 < 13) )
891 000197D0 L322:
892 000197D0 0d effffff802 50 movl _index2,r0
893 000197D7 0d effffff7fb 51 movl _index2,r1
894 000197DE 1d 40effffff7f3 cmpl _load_regs[r0],_store_regs[r1]
41effffff7ed
895 000197EB 21 11 jneq L323
896 000197ED 1d effffff7e5 0d cmpl _index2,$13
897 000197F4 81 08 jgeq L323
898 000197F6 # index2++; /* check reg values */
899 000197F6 6d effffff7dc incl _index2
900 000197FC 11 d2 jbr L322
901 000197FE L323:
902 000197FE # if( index2 < 13 ) { /* error if index2 < 13 */
903 000197FE 1d effffff7d4 0d cmpl _index2,$13
904 00019805 91 03 13 00f4 jgeq L324
905 0001980A # errcnt++; /* bump the error count */
906 0001980A 6d effffff7c8 incl _errcnt
907 00019810 # if( prt_error ) {
908 00019810 5d effffff7c2 tstl _prt_error
909 00019816 21 03 13 00c0 jeql L325
910 0001981B # writes(" \n"); /* start a new print line */
911 0001981B .data 1
912 00000e6f * L326:
913 00000e6f * 200A00 .ascii " \12\0"
914 00000e72 * .text
915 0001981B dd 8f00000e6f pushl $L326
916 00019821 fe 08 effffff7b0 callf $8,_writes
917 00019828 # writes("cycle: ");
918 00019828 .data 1
919 00000e72 * L327:
920 00000e72 * 6379636C653A2000 .ascii "cycle: \0"
921 00000e7a * .text
922 00019828 dd 8f00000e72 pushl $L327
923 0001982E fe 08 effffff7a3 callf $8,_writes
924 00019835 # writed( cycle );
925 00019835 dd effffff79d pushl _cycle
926 0001983B fe 08 effffff796 callf $8,_writed
927 00019842 # writes(" DIVD test ");
928 00019842 .data 1
929 00000e7a * L328:
930 00000e7a * 2020444956442074657374200 .ascii " DIVD test \0"
0
931 00000e87 * .text
932 00019842 dd 8f00000e7a pushl $L328
933 00019848 fe 08 effffff789 callf $8,_writes
934 0001984F # writed( test_no );
935 0001984F dd effffff783 pushl _test_no
936 00019855 fe 08 effffff77c callf $8,_writed
937 0001985C # writes(", subtest 6 - A REGISTER WAS CHANGED\n");
938 0001985C .data 1
939 00000e87 * L329:
940 00000e87 * 2C20737562746573742036202 .ascii ", subtest 6 - A REGISTER WAS CHANGED\12\0"
D204120524547495354455220
574153204348414E4745440A0
0
941 00000ead * .text
942 0001985C dd 8f00000e87 pushl $L329
943 00019862 fe 08 effffff76f callf $8,_writes
944 00019869 # print_divd_data(); /* print the operands */
945 00019869 fe 04 ef0000026c callf $4,_print_divd_data
946 00019870 # writes("register "); /* print the information */
947 00019870 .data 1
948 00000ead * L330:
949 00000ead * 72656769737465722000 .ascii "register \0"
950 00000eb7 * .text
951 00019870 dd 8f00000ead pushl $L330
952 00019876 fe 08 effffff75b callf $8,_writes
953 0001987D # writed( index2 ); /* about the corrupted */
954 0001987D dd effffff755 pushl _index2
955 00019883 fe 08 effffff74e callf $8,_writed
956 0001988A # writes(" = "); /* register */
957 0001988A .data 1
958 00000eb7 * L331:
959 00000eb7 * 203D2000 .ascii " = \0"
960 00000ebb * .text
961 0001988A dd 8f00000eb7 pushl $L331
962 00019890 fe 08 effffff741 callf $8,_writes
963 00019897 # write32h( store_regs[index2] );
964 00019897 0d effffff73b 50 movl _index2,r0
965 0001989E dd 40effffff733 pushl _store_regs[r0]
966 000198A5 fe 08 effffff72c callf $8,_write32h
967 000198AC # writes(", should be = ");
968 000198AC .data 1
969 00000ebb * L333:
970 00000ebb * 2C202073686F756C642062652 .ascii ", should be = \0"
03D2000
971 00000ecb * .text
972 000198AC dd 8f00000ebb pushl $L333
973 000198B2 fe 08 effffff71f callf $8,_writes
974 000198B9 # write32h( load_regs[index2] );
975 000198B9 0d effffff719 50 movl _index2,r0
976 000198C0 dd 40effffff711 pushl _load_regs[r0]
977 000198C7 fe 08 effffff70a callf $8,_write32h
978 000198CE # writes("\n");
979 000198CE .data 1
980 00000ecb * L334:
981 00000ecb * 0A00 .ascii "\12\0"
982 00000ecd * .text
983 000198CE dd 8f00000ecb pushl $L334
984 000198D4 fe 08 effffff6fd callf $8,_writes
985 000198DB # }
986 000198DB # if( halt_flg )
987 000198DB L325:
988 000198DB 5d effffff6f7 tstl _halt_flg
989 000198E1 31 09 jeql L335
990 000198E3 # divd_er_halt( BAD_REG_HLT ); /* halt on the error */
991 000198E3 dd 02 pushl $2
992 000198E5 fe 08 ef000002e6 callf $8,_divd_er_halt
993 000198EC # if( loop_on_err ) {
994 000198EC L335:
995 000198EC 5d effffff6e6 tstl _loop_on_err
996 000198F2 31 0a jeql L336
997 000198F4 # force_loop = TRUE; /* set the force loop flag */
998 000198F4 0d 01 effffff6dd movl $1,_force_loop
999 000198FB # asm("brw _divd_6_lp1");; /* and loop on the error */
1000 000198FB 13 fe9b brw _divd_6_lp1
1001 000198FE # } /* end of loop on error */
1002 000198FE # } /* end of register corruption error */
1003 000198FE L336:
1004 000198FE # } /* end of subtest 6 */
1005 000198FE L324:
1006 000198FE 40 ret#2
1007 000198FF .set L316,0x0
1008 000198FF L318:
1009 000198FF 13 fe35 jbr L319
1010 00019902 .data
1011 00000d28 * .text
1012 00019902 .align 1
1013 00019902 .globl _divd_7
1014 00019902 _divd_7:
1015 00019902 0000 .word L337
1016 00019904 #
1017 00019904 #
1018 00019904 #
1019 00019904 # /************************************************************************
1020 00019904 # *
1021 00019904 # * SUBTEST 7 - Check for PSL corruption
1022 00019904 # *
1023 00019904 # ************************************************************************/
1024 00019904 # divd_7()
1025 00019904 # {
1026 00019904 13 01d2 jbr L339
1027 00019907 L340:
1028 00019907 # force_loop = FALSE; /* clear force_loop flg */
1029 00019907 4d effffff6cb clrl _force_loop
1030 0001990D # subtest = 7;
1031 0001990D 0d 07 effffff6c4 movl $7,_subtest
1032 00019914 # fill_reg_buf( load_regs ); /* get patterns for regs */
1033 00019914 dd 8f00000000 pushl $_load_regs
1034 0001991A fe 08 effffff6b7 callf $8,_fill_reg_buf
1035 00019921 # for( index = 0; index < 3; index++ ) {
1036 00019921 4d effffff6b1 clrl _index
1037 00019927 L343:
1038 00019927 1d effffff6ab 03 cmpl _index,$3
1039 0001992E 91 03 13 01a5 jgeq L342
1040 00019933 # dbl_ld_acc = divd_1_data[index].op_1; /* get operand 1 */
1041 00019933 5c 18 effffff69e 50 mull3 $24,_index,r0
1042 0001993B 0c 8f00000000 50 addl2 $_divd_1_data,r0
1043 00019942 0d a004 effffff692 movl 4(r0),_dbl_ld_acc+4
1044 0001994A 0d 60 effffff687 movl (r0),_dbl_ld_acc
1045 00019951 # dbl_value_1 = divd_1_data[index].op_2; /* get operand 2 */
1046 00019951 5c 18 effffff680 50 mull3 $24,_index,r0
1047 00019959 0c 8f00000008 50 addl2 $_divd_1_data+8,r0
1048 00019960 0d a004 effffff674 movl 4(r0),_dbl_value_1+4
1049 00019968 0d 60 effffff669 movl (r0),_dbl_value_1
1050 0001996F # dbl_expected = divd_1_data[index].exp; /* get expected */
1051 0001996F 5c 18 effffff662 50 mull3 $24,_index,r0
1052 00019977 0c 8f00000010 50 addl2 $_divd_1_data+16,r0
1053 0001997E 0d a004 effffff656 movl 4(r0),_dbl_expected+4
1054 00019986 0d 60 effffff64b movl (r0),_dbl_expected
1055 0001998D # sgl_dummy1 = status_array[status_index]; /* status = +, -, 0 */
1056 0001998D 0d effffff645 50 movl _status_index,r0
1057 00019994 0d 40effffff63d movl _status_array[r0],_sgl_dummy1
effffff638
1058 000199A0 # /*
1059 000199A0 # * If LOOP ON ERROR is set, this is the loop for this subtest.
1060 000199A0 # * The force loop flag is set after the first error.
1061 000199A0 # */
1062 000199A0 # asm("_divd_7_lp1:");
1063 000199A0 _divd_7_lp1:
1064 000199A0 # asm("ldd _dbl_ld_acc"); /* LOAD the accumulator */
1065 000199A0 07 effffff632 ldd _dbl_ld_acc
1066 000199A6 # asm("nop");
1067 000199A6 10 nop
1068 000199A7 # asm("tstl _sgl_dummy1"); /* set the PSL status */
1069 000199A7 5d effffff62b tstl _sgl_dummy1
1070 000199AD # asm("movpsl _init_psl"); /* save the initial PSL */
1071 000199AD cd effffff625 movpsl _init_psl
1072 000199B3 # asm("divd _dbl_value_1"); /* do the divide */
1073 000199B3 f7 effffff61f divd _dbl_value_1
1074 000199B9 # asm("nop");
1075 000199B9 10 nop
1076 000199BA # asm("movpsl _psl_val"); /* save the final PSL */
1077 000199BA cd effffff618 movpsl _psl_val
1078 000199C0 # asm("std _dbl_st_acc"); /* save the accumulator */
1079 000199C0 27 effffff612 std _dbl_st_acc
1080 000199C6 # if( force_loop )
1081 000199C6 5d effffff60c tstl _force_loop
1082 000199CC 31 02 jeql L344
1083 000199CE # asm("brb _divd_7_lp1");; /* loop on the error */
1084 000199CE 11 d0 brb _divd_7_lp1
1085 000199D0 L344:
1086 000199D0 # /*
1087 000199D0 # * Now compare the final PSL to the initial PSL -they should be the same
1088 000199D0 # */
1089 000199D0 # exp_psl = init_psl;
1090 000199D0 0d effffff602 effffff5fd movl _init_psl,_exp_psl
1091 000199DB # if( psl_val != exp_psl ) {
1092 000199DB 1d effffff5f7 effffff5f2 cmpl _psl_val,_exp_psl
1093 000199E6 21 03 13 00e4 jeql L345
1094 000199EB # errcnt++; /* bump the error count */
1095 000199EB 6d effffff5e7 incl _errcnt
1096 000199F1 # if( prt_error ) {
1097 000199F1 5d effffff5e1 tstl _prt_error
1098 000199F7 21 03 13 00b0 jeql L346
1099 000199FC # writes(" \n"); /* start a new print line */
1100 000199FC .data 1
1101 00000ecd * L347:
1102 00000ecd * 200A00 .ascii " \12\0"
1103 00000ed0 * .text
1104 000199FC dd 8f00000ecd pushl $L347
1105 00019A02 fe 08 effffff5cf callf $8,_writes
1106 00019A09 # writes("cycle: ");
1107 00019A09 .data 1
1108 00000ed0 * L348:
1109 00000ed0 * 6379636C653A2000 .ascii "cycle: \0"
1110 00000ed8 * .text
1111 00019A09 dd 8f00000ed0 pushl $L348
1112 00019A0F fe 08 effffff5c2 callf $8,_writes
1113 00019A16 # writed( cycle );
1114 00019A16 dd effffff5bc pushl _cycle
1115 00019A1C fe 08 effffff5b5 callf $8,_writed
1116 00019A23 # writes(" DIVD test ");
1117 00019A23 .data 1
1118 00000ed8 * L349:
1119 00000ed8 * 2020444956442074657374200 .ascii " DIVD test \0"
0
1120 00000ee5 * .text
1121 00019A23 dd 8f00000ed8 pushl $L349
1122 00019A29 fe 08 effffff5a8 callf $8,_writes
1123 00019A30 # writed( test_no );
1124 00019A30 dd effffff5a2 pushl _test_no
1125 00019A36 fe 08 effffff59b callf $8,_writed
1126 00019A3D # writes(", subtest 7 - INCORRECT FINAL PSL\n");
1127 00019A3D .data 1
1128 00000ee5 * L350:
1129 00000ee5 * 2C20737562746573742037202 .ascii ", subtest 7 - INCORRECT FINAL PSL\12\0"
D20494E434F52524543542046
494E414C2050534C0A00
1130 00000f08 * .text
1131 00019A3D dd 8f00000ee5 pushl $L350
1132 00019A43 fe 08 effffff58e callf $8,_writes
1133 00019A4A # print_divd_data(); /* print the operands */
1134 00019A4A fe 04 ef0000008b callf $4,_print_divd_data
1135 00019A51 # writes("initial PSL = ");
1136 00019A51 .data 1
1137 00000f08 * L351:
1138 00000f08 * 696E697469616C2050534C203 .ascii "initial PSL = \0"
D2000
1139 00000f17 * .text
1140 00019A51 dd 8f00000f08 pushl $L351
1141 00019A57 fe 08 effffff57a callf $8,_writes
1142 00019A5E # write32h( init_psl );
1143 00019A5E dd effffff574 pushl _init_psl
1144 00019A64 fe 08 effffff56d callf $8,_write32h
1145 00019A6B # writes(", final PSL = ");
1146 00019A6B .data 1
1147 00000f17 * L352:
1148 00000f17 * 2C202066696E616C2050534C2 .ascii ", final PSL = \0"
03D2000
1149 00000f27 * .text
1150 00019A6B dd 8f00000f17 pushl $L352
1151 00019A71 fe 08 effffff560 callf $8,_writes
1152 00019A78 # write32h( psl_val );
1153 00019A78 dd effffff55a pushl _psl_val
1154 00019A7E fe 08 effffff553 callf $8,_write32h
1155 00019A85 # writes(", expected PSL = ");
1156 00019A85 .data 1
1157 00000f27 * L353:
1158 00000f27 * 2C20206578706563746564205 .ascii ", expected PSL = \0"
0534C203D2000
1159 00000f3a * .text
1160 00019A85 dd 8f00000f27 pushl $L353
1161 00019A8B fe 08 effffff546 callf $8,_writes
1162 00019A92 # write32h( exp_psl );
1163 00019A92 dd effffff540 pushl _exp_psl
1164 00019A98 fe 08 effffff539 callf $8,_write32h
1165 00019A9F # writes("\n");
1166 00019A9F .data 1
1167 00000f3a * L354:
1168 00000f3a * 0A00 .ascii "\12\0"
1169 00000f3c * .text
1170 00019A9F dd 8f00000f3a pushl $L354
1171 00019AA5 fe 08 effffff52c callf $8,_writes
1172 00019AAC # }
1173 00019AAC # if( halt_flg )
1174 00019AAC L346:
1175 00019AAC 5d effffff526 tstl _halt_flg
1176 00019AB2 31 09 jeql L355
1177 00019AB4 # divd_er_halt( BAD_PSL_HLT ); /* halt on the error */
1178 00019AB4 dd 03 pushl $3
1179 00019AB6 fe 08 ef00000115 callf $8,_divd_er_halt
1180 00019ABD # if( loop_on_err ) {
1181 00019ABD L355:
1182 00019ABD 5d effffff515 tstl _loop_on_err
1183 00019AC3 31 0a jeql L356
1184 00019AC5 # force_loop = TRUE; /* set the force loop flag */
1185 00019AC5 0d 01 effffff50c movl $1,_force_loop
1186 00019ACC # asm("brw _divd_7_lp1");; /* and loop on the error */
1187 00019ACC 13 fed1 brw _divd_7_lp1
1188 00019ACF # } /* end of loop on error */
1189 00019ACF # } /* end of PSL corruption error */
1190 00019ACF L356:
1191 00019ACF # } /* end of WHILE loop */
1192 00019ACF L345:
1193 00019ACF L341:
1194 00019ACF 6d effffff503 incl _index
1195 00019AD5 13 fe4f jbr L343
1196 00019AD8 L342:
1197 00019AD8 # } /* end of subtest 7 */
1198 00019AD8 40 ret#2
1199 00019AD9 .set L337,0x0
1200 00019AD9 L339:
1201 00019AD9 13 fe2b jbr L340
1202 00019ADC .data
1203 00000d28 * .text
1204 00019ADC .align 1
1205 00019ADC .globl _print_divd_data
1206 00019ADC _print_divd_data:
1207 00019ADC 0000 .word L357
1208 00019ADE #
1209 00019ADE #
1210 00019ADE #
1211 00019ADE # /**************************************************************************
1212 00019ADE # *
1213 00019ADE # * PRINT THE DATA AND STORE RESULTS
1214 00019ADE # *
1215 00019ADE # * initial Acc = xxxxxxxx xxxxxxxx, stored = xxxxxxxx xxxxxxxx, index = xx
1216 00019ADE # * operand = xxxxxxxx xxxxxxxx, expected = xxxxxxxx xxxxxxxx
1217 00019ADE # **************************************************************************/
1218 00019ADE # print_divd_data()
1219 00019ADE # {
1220 00019ADE 13 00ed jbr L359
1221 00019AE1 L360:
1222 00019AE1 # writes("initial Acc = ");
1223 00019AE1 .data 1
1224 00000f3c * L361:
1225 00000f3c * 696E697469616C20416363203 .ascii "initial Acc = \0"
D2000
1226 00000f4b * .text
1227 00019AE1 dd 8f00000f3c pushl $L361
1228 00019AE7 fe 08 effffff4ea callf $8,_writes
1229 00019AEE # write32h( dbl_ld_acc.m );
1230 00019AEE dd effffff4e4 pushl _dbl_ld_acc
1231 00019AF4 fe 08 effffff4dd callf $8,_write32h
1232 00019AFB # writec(' ');
1233 00019AFB dd 20 pushl $32
1234 00019AFD fe 08 effffff4d4 callf $8,_writec
1235 00019B04 # write32h( dbl_ld_acc.l );
1236 00019B04 dd effffff4d2 pushl _dbl_ld_acc+4
1237 00019B0A fe 08 effffff4c7 callf $8,_write32h
1238 00019B11 # writes(", stored = ");
1239 00019B11 .data 1
1240 00000f4b * L363:
1241 00000f4b * 2C2020202073746F726564203 .ascii ", stored = \0"
D2000
1242 00000f5a * .text
1243 00019B11 dd 8f00000f4b pushl $L363
1244 00019B17 fe 08 effffff4ba callf $8,_writes
1245 00019B1E # write32h( dbl_st_acc.m );
1246 00019B1E dd effffff4b4 pushl _dbl_st_acc
1247 00019B24 fe 08 effffff4ad callf $8,_write32h
1248 00019B2B # writec(' ');
1249 00019B2B dd 20 pushl $32
1250 00019B2D fe 08 effffff4a4 callf $8,_writec
1251 00019B34 # write32h( dbl_st_acc.l );
1252 00019B34 dd effffff4a2 pushl _dbl_st_acc+4
1253 00019B3A fe 08 effffff497 callf $8,_write32h
1254 00019B41 # writes(", index = ");
1255 00019B41 .data 1
1256 00000f5a * L364:
1257 00000f5a * 2C202020696E646578203D200 .ascii ", index = \0"
0
1258 00000f67 * .text
1259 00019B41 dd 8f00000f5a pushl $L364
1260 00019B47 fe 08 effffff48a callf $8,_writes
1261 00019B4E # writed( index );
1262 00019B4E dd effffff484 pushl _index
1263 00019B54 fe 08 effffff47d callf $8,_writed
1264 00019B5B # writec('\n');
1265 00019B5B dd 0a pushl $10
1266 00019B5D fe 08 effffff474 callf $8,_writec
1267 00019B64 # writes(" operand = ");
1268 00019B64 .data 1
1269 00000f67 * L365:
1270 00000f67 * 202020206F706572616E64203 .ascii " operand = \0"
D2000
1271 00000f76 * .text
1272 00019B64 dd 8f00000f67 pushl $L365
1273 00019B6A fe 08 effffff467 callf $8,_writes
1274 00019B71 # write32h( dbl_value_1.m );
1275 00019B71 dd effffff461 pushl _dbl_value_1
1276 00019B77 fe 08 effffff45a callf $8,_write32h
1277 00019B7E # writec(' ');
1278 00019B7E dd 20 pushl $32
1279 00019B80 fe 08 effffff451 callf $8,_writec
1280 00019B87 # write32h( dbl_value_1.l );
1281 00019B87 dd effffff44f pushl _dbl_value_1+4
1282 00019B8D fe 08 effffff444 callf $8,_write32h
1283 00019B94 # writes(", expected = ");
1284 00019B94 .data 1
1285 00000f76 * L366:
1286 00000f76 * 2C20206578706563746564203 .ascii ", expected = \0"
D2000
1287 00000f85 * .text
1288 00019B94 dd 8f00000f76 pushl $L366
1289 00019B9A fe 08 effffff437 callf $8,_writes
1290 00019BA1 # write32h( dbl_expected.m );
1291 00019BA1 dd effffff431 pushl _dbl_expected
1292 00019BA7 fe 08 effffff42a callf $8,_write32h
1293 00019BAE # writec(' ');
1294 00019BAE dd 20 pushl $32
1295 00019BB0 fe 08 effffff421 callf $8,_writec
1296 00019BB7 # write32h( dbl_expected.l );
1297 00019BB7 dd effffff41f pushl _dbl_expected+4
1298 00019BBD fe 08 effffff414 callf $8,_write32h
1299 00019BC4 # writec('\n');
1300 00019BC4 dd 0a pushl $10
1301 00019BC6 fe 08 effffff40b callf $8,_writec
1302 00019BCD # }
1303 00019BCD 40 ret#2
1304 00019BCE .set L357,0x0
1305 00019BCE L359:
1306 00019BCE 13 ff10 jbr L360
1307 00019BD1 .data
1308 00000d28 * .text
1309 00019BD1 00 .align 1
1310 00019BD2 .globl _divd_er_halt
1311 00019BD2 _divd_er_halt:
1312 00019BD2 0000 .word L367
1313 00019BD4 #
1314 00019BD4 #
1315 00019BD4 #
1316 00019BD4 # /**************************************************************************
1317 00019BD4 # *
1318 00019BD4 # * HALT ON ERROR ROUTINE
1319 00019BD4 # *
1320 00019BD4 # **************************************************************************/
1321 00019BD4 # divd_er_halt( halt_code )
1322 00019BD4 # int halt_code;
1323 00019BD4 # {
1324 00019BD4 13 0123 jbr L369
1325 00019BD7 L370:
1326 00019BD7 # sgl_value_1 = dbl_ld_acc.m;
1327 00019BD7 0d effffff3fb effffff3f6 movl _dbl_ld_acc,_sgl_value_1
1328 00019BE2 # sgl_value_2 = dbl_ld_acc.l;
1329 00019BE2 0d effffff3f4 effffff3eb movl _dbl_ld_acc+4,_sgl_value_2
1330 00019BED # sgl_value_3 = dbl_value_1.m;
1331 00019BED 0d effffff3e5 effffff3e0 movl _dbl_value_1,_sgl_value_3
1332 00019BF8 # sgl_value_4 = dbl_value_1.l;
1333 00019BF8 0d effffff3de effffff3d5 movl _dbl_value_1+4,_sgl_value_4
1334 00019C03 # sgl_value_5 = dbl_st_acc.m;
1335 00019C03 0d effffff3cf effffff3ca movl _dbl_st_acc,_sgl_value_5
1336 00019C0E # sgl_value_6 = dbl_st_acc.l;
1337 00019C0E 0d effffff3c8 effffff3bf movl _dbl_st_acc+4,_sgl_value_6
1338 00019C19 # sgl_dummy1 = halt_code; /* get the error type */
1339 00019C19 0d ad04 effffff3b7 movl 4(fp),_sgl_dummy1
1340 00019C21 # asm("movl _test_no,r0"); /* r0 = test number */
1341 00019C21 0d effffff3b1 50 movl _test_no,r0
1342 00019C28 # asm("movl _subtest,r1"); /* r1 = subtest number */
1343 00019C28 0d effffff3aa 51 movl _subtest,r1
1344 00019C2F # asm("movl _sgl_dummy1,r2"); /* r2 = error code */
1345 00019C2F 0d effffff3a3 52 movl _sgl_dummy1,r2
1346 00019C36 # asm("movl _cycle,r3"); /* r3 = cycle count */
1347 00019C36 0d effffff39c 53 movl _cycle,r3
1348 00019C3D # asm("movl _sgl_value_1,r4"); /* r4 = MS operand 1 */
1349 00019C3D 0d effffff395 54 movl _sgl_value_1,r4
1350 00019C44 # asm("movl _sgl_value_2,r5"); /* r5 = LS operand 1 */
1351 00019C44 0d effffff38e 55 movl _sgl_value_2,r5
1352 00019C4B # asm("movl _sgl_value_3,r6"); /* r6 = MS operand 2 */
1353 00019C4B 0d effffff387 56 movl _sgl_value_3,r6
1354 00019C52 # asm("movl _sgl_value_4,r7"); /* r7 = LS operand 2 */
1355 00019C52 0d effffff380 57 movl _sgl_value_4,r7
1356 00019C59 # asm("movl _sgl_value_5,r8"); /* r8 = MS stored */
1357 00019C59 0d effffff379 58 movl _sgl_value_5,r8
1358 00019C60 # asm("movl _sgl_value_6,r9"); /* r9 = LS stored */
1359 00019C60 0d effffff372 59 movl _sgl_value_6,r9
1360 00019C67 # if( halt_code == BAD_ACC_HLT ) {
1361 00019C67 1d ad04 01 cmpl 4(fp),$1
1362 00019C6B 21 2d jneq L371
1363 00019C6D # sgl_value_1 = dbl_expected.m;
1364 00019C6D 0d effffff365 effffff360 movl _dbl_expected,_sgl_value_1
1365 00019C78 # sgl_value_2 = dbl_expected.l;
1366 00019C78 0d effffff35e effffff355 movl _dbl_expected+4,_sgl_value_2
1367 00019C83 # asm("movl _sgl_value_1,r10"); /* r10 = MS expected */
1368 00019C83 0d effffff34f 5a movl _sgl_value_1,r10
1369 00019C8A # asm("movl _sgl_value_2,r11"); /* r11 = LS expected */
1370 00019C8A 0d effffff348 5b movl _sgl_value_2,r11
1371 00019C91 # asm("movl _index2,r12"); /* r12 = data index */
1372 00019C91 0d effffff341 5c movl _index2,r12
1373 00019C98 # } else
1374 00019C98 11 5e jbr L372
1375 00019C9A L371:
1376 00019C9A # if( halt_code == BAD_REG_HLT ) {
1377 00019C9A 1d ad04 02 cmpl 4(fp),$2
1378 00019C9E 21 3d jneq L373
1379 00019CA0 # sgl_dummy1 = load_regs[index2];
1380 00019CA0 0d effffff332 50 movl _index2,r0
1381 00019CA7 0d 40effffff32a movl _load_regs[r0],_sgl_dummy1
effffff325
1382 00019CB3 # sgl_dummy2 = store_regs[index2];
1383 00019CB3 0d effffff31f 50 movl _index2,r0
1384 00019CBA 0d 40effffff317 movl _store_regs[r0],_sgl_dummy2
effffff312
1385 00019CC6 # asm("movl _index2,r10"); /* r10 = bad register # */
1386 00019CC6 0d effffff30c 5a movl _index2,r10
1387 00019CCD # asm("movl _sgl_dummy2,r11"); /* r11 = actual value */
1388 00019CCD 0d effffff305 5b movl _sgl_dummy2,r11
1389 00019CD4 # asm("movl _sgl_dummy1,r12"); /* r12 = expected value */
1390 00019CD4 0d effffff2fe 5c movl _sgl_dummy1,r12
1391 00019CDB # } else
1392 00019CDB 11 1b jbr L374
1393 00019CDD L373:
1394 00019CDD # if( halt_code == BAD_PSL_HLT ) {
1395 00019CDD 1d ad04 03 cmpl 4(fp),$3
1396 00019CE1 21 15 jneq L375
1397 00019CE3 # asm("movl _init_psl,r10"); /* r10 = initial PSL */
1398 00019CE3 0d effffff2ef 5a movl _init_psl,r10
1399 00019CEA # asm("movl _psl_val,r11"); /* r11 = final PSL */
1400 00019CEA 0d effffff2e8 5b movl _psl_val,r11
1401 00019CF1 # asm("movl _exp_psl,r12"); /* r12 = expected PSL */
1402 00019CF1 0d effffff2e1 5c movl _exp_psl,r12
1403 00019CF8 # };
1404 00019CF8 L375:
1405 00019CF8 L374:
1406 00019CF8 L372:
1407 00019CF8 # asm("halt"); /* HALT ... */
1408 00019CF8 00 halt
1409 00019CF9 # }
1410 00019CF9 40 ret#2
1411 00019CFA .set L367,0x0
1412 00019CFA L369:
1413 00019CFA 13 feda jbr L370
1414 00019CFD .data
1414 00032CD5 .data
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