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1.1 ! root 1: #include "fpp_defs.h" ! 2: ! 3: ! 4: /***************************************************************************** ! 5: * ! 6: * DIVF - SINGLE PRECISION FLOATING POINT ADD TEST ! 7: * ! 8: *****************************************************************************/ ! 9: divf() ! 10: { ! 11: asm(".globl _divf_t"); ! 12: asm("_divf_t:"); /* entry address */ ! 13: if( ( cycle == 1 ) && ( prt_hdrs ) ) /* print headers on 1st pass */ ! 14: writes(" DIVF"); ! 15: divf_1(); /* div through a register */ ! 16: divf_2(); /* div through the cache */ ! 17: divf_3(); /* wait 3 NOPs */ ! 18: divf_4(); /* wait 2 NOPs */ ! 19: divf_5(); /* wait 1 NOP before storing */ ! 20: divf_6(); /* register stability test */ ! 21: divf_7(); /* PSL stability test */ ! 22: divf_8(); /* pipelined entry test */ ! 23: divf_9(); /* pipelined exit test */ ! 24: asm("jmp *return"); /* return to the test monitor */ ! 25: } ! 26: ! 27: ! 28: ! 29: /************************************************************************ ! 30: * ! 31: * SUBTEST 1 - divide through a register ! 32: * ! 33: ************************************************************************/ ! 34: divf_1() ! 35: { ! 36: force_loop = FALSE; ! 37: subtest = 1; ! 38: for( index = 0; index < max_divf_1_index; index++ ) { ! 39: sgl_ld_acc = divf_1_data[index].op_1; /* get operand 1 */ ! 40: sgl_value_1 = divf_1_data[index].op_2; /* get operand 2 */ ! 41: sgl_expected = divf_1_data[index].exp; /* get expected result */ ! 42: /* ! 43: * If LOOP ON ERROR is set, this is the loop for this subtest. ! 44: * The force loop flag is set after the first error. ! 45: */ ! 46: asm("_divf_1_lp1:"); ! 47: asm("movl _sgl_ld_acc,r3"); /* move the 1st data to r3 */ ! 48: asm("movl _sgl_value_1,r4"); /* move the 2nd data to r4 */ ! 49: asm("ldf r3"); /* load the 1st operand */ ! 50: asm("divf r4"); /* divide the 2nd operand */ ! 51: asm("stf _sgl_st_acc"); /* store the result */ ! 52: if( force_loop ) ! 53: asm("brb _divf_1_lp1");; /* loop on the error */ ! 54: /* ! 55: * end error loop - test the results ! 56: */ ! 57: if( sgl_st_acc != sgl_expected ) { /* COMPARE the values */ ! 58: errcnt++; /* bump the error count */ ! 59: if( prt_error ) { ! 60: writes(" \n"); /* start a new print line */ ! 61: writes("cycle: "); ! 62: writed( cycle ); ! 63: writes(" DIVF test "); ! 64: writed( test_no ); ! 65: writes(", subtest 1 (Reg. Data) - BAD FINAL ACC\n"); ! 66: print_divf_data(); ! 67: } ! 68: if( halt_flg ) ! 69: divf_er_halt( BAD_ACC_HLT ); /* halt on the error */ ! 70: if( loop_on_err ) { ! 71: force_loop = TRUE; /* set the force loop flag */ ! 72: asm("brw _divf_1_lp1");; /* and loop on the error */ ! 73: } /* end of loop on error */ ! 74: } /* end of compare error */ ! 75: } /* end of WHILE loop */ ! 76: } /* end of subtest 1 */ ! 77: ! 78: ! 79: ! 80: /************************************************************************ ! 81: * ! 82: * SUBTEST 2 - divide through memory ! 83: * ! 84: ************************************************************************/ ! 85: divf_2() ! 86: { ! 87: force_loop = FALSE; ! 88: subtest = 2; ! 89: for( index = 0; index < max_divf_1_index; index++ ) { ! 90: sgl_ld_acc = divf_1_data[index].op_1; /* get operand 1 */ ! 91: sgl_value_1 = divf_1_data[index].op_2; /* get operand 2 */ ! 92: sgl_expected = divf_1_data[index].exp; /* get expected result */ ! 93: /* ! 94: * If LOOP ON ERROR is set, this is the loop for this subtest. ! 95: * The force loop flag is set after the first error. ! 96: */ ! 97: asm("_divf_2_lp1:"); ! 98: asm("ldf _sgl_ld_acc"); /* load the 1st operand */ ! 99: asm("divf _sgl_value_1"); /* divide the 2nd operand */ ! 100: asm("stf _sgl_st_acc"); /* store the result */ ! 101: if( force_loop ) ! 102: asm("brb _divf_2_lp1");; /* loop on the error */ ! 103: /* ! 104: * end error loop - test the results ! 105: */ ! 106: if( sgl_st_acc != sgl_expected ) { /* COMPARE the values */ ! 107: errcnt++; /* bump the error count */ ! 108: if( prt_error ) { ! 109: writes(" \n"); /* start a new print line */ ! 110: writes("cycle: "); ! 111: writed( cycle ); ! 112: writes(" DIVF test "); ! 113: writed( test_no ); ! 114: writes(", subtest 2 (Cache Data) - BAD FINAL ACC\n"); ! 115: print_divf_data(); ! 116: } ! 117: if( halt_flg ) ! 118: divf_er_halt( BAD_ACC_HLT ); /* halt on the error */ ! 119: if( loop_on_err ) { ! 120: force_loop = TRUE; /* set the force loop flag */ ! 121: asm("brw _divf_2_lp1");; /* and loop on the error */ ! 122: } /* end of loop on error */ ! 123: } /* end of compare error */ ! 124: } /* end of WHILE loop */ ! 125: } /* end of subtest 2 */ ! 126: ! 127: ! 128: ! 129: /************************************************************************ ! 130: * ! 131: * SUBTEST 3 - Divide, Wait 3 NOPs before storing the results ! 132: * ! 133: ************************************************************************/ ! 134: divf_3() ! 135: { ! 136: force_loop = FALSE; ! 137: subtest = 3; ! 138: for( index = 0; index < max_divf_1_index; index++ ) { ! 139: sgl_ld_acc = divf_1_data[index].op_1; /* get operand 1 */ ! 140: sgl_value_1 = divf_1_data[index].op_2; /* get operand 2 */ ! 141: sgl_expected = divf_1_data[index].exp; /* get expected result */ ! 142: /* ! 143: * If LOOP ON ERROR is set, this is the loop for this subtest. ! 144: * The force loop flag is set after the first error. ! 145: */ ! 146: asm("_divf_3_lp1:"); ! 147: asm("ldf _sgl_ld_acc"); /* load the 1st operand */ ! 148: asm("nop"); /* delay */ ! 149: asm("divf _sgl_value_1"); /* divide the 2nd operand */ ! 150: asm("nop"); /* delay before ... */ ! 151: asm("nop"); ! 152: asm("nop"); /* ... storing the result */ ! 153: asm("stf _sgl_st_acc"); /* store the result */ ! 154: if( force_loop ) ! 155: asm("brb _divf_3_lp1");; /* loop on the error */ ! 156: /* ! 157: * end error loop - test the results ! 158: */ ! 159: if( sgl_st_acc != sgl_expected ) { /* COMPARE the values */ ! 160: errcnt++; /* bump the error count */ ! 161: if( prt_error ) { ! 162: writes(" \n"); /* start a new print line */ ! 163: writes("cycle: "); ! 164: writed( cycle ); ! 165: writes(" DIVF test "); ! 166: writed( test_no ); ! 167: writes(", subtest 3 (Cache data - 3 NOPs) - BAD FINAL ACC\n"); ! 168: print_divf_data(); ! 169: } ! 170: if( halt_flg ) ! 171: divf_er_halt( BAD_ACC_HLT ); /* halt on the error */ ! 172: if( loop_on_err ) { ! 173: force_loop = TRUE; /* set the force loop flag */ ! 174: asm("brw _divf_3_lp1");; /* and loop on the error */ ! 175: } /* end of loop on error */ ! 176: } /* end of compare error */ ! 177: } /* end of WHILE loop */ ! 178: } /* end of subtest 3 */ ! 179: ! 180: ! 181: ! 182: /************************************************************************ ! 183: * ! 184: * SUBTEST 4 - Divide, Wait 2 NOPs before storing the results ! 185: * ! 186: ************************************************************************/ ! 187: divf_4() ! 188: { ! 189: force_loop = FALSE; ! 190: subtest = 4; ! 191: for( index = 0; index < max_divf_1_index; index++ ) { ! 192: sgl_ld_acc = divf_1_data[index].op_1; /* get operand 1 */ ! 193: sgl_value_1 = divf_1_data[index].op_2; /* get operand 2 */ ! 194: sgl_expected = divf_1_data[index].exp; /* get expected result */ ! 195: /* ! 196: * If LOOP ON ERROR is set, this is the loop for this subtest. ! 197: * The force loop flag is set after the first error. ! 198: */ ! 199: asm("_divf_4_lp1:"); ! 200: asm("ldf _sgl_ld_acc"); /* load the 1st operand */ ! 201: asm("nop"); /* delay */ ! 202: asm("divf _sgl_value_1"); /* divide the 2nd operand */ ! 203: asm("nop"); /* delay before ... */ ! 204: asm("nop"); /* ... storing the result */ ! 205: asm("stf _sgl_st_acc"); /* store the result */ ! 206: if( force_loop ) ! 207: asm("brb _divf_4_lp1");; /* loop on the error */ ! 208: /* ! 209: * end error loop - test the results ! 210: */ ! 211: if( sgl_st_acc != sgl_expected ) { /* COMPARE the values */ ! 212: errcnt++; /* bump the error count */ ! 213: if( prt_error ) { ! 214: writes(" \n"); /* start a new print line */ ! 215: writes("cycle: "); ! 216: writed( cycle ); ! 217: writes(" DIVF test "); ! 218: writed( test_no ); ! 219: writes(", subtest 4 (Cache Data - 2 NOPs) - BAD FINAL ACC\n"); ! 220: print_divf_data(); ! 221: } ! 222: if( halt_flg ) ! 223: divf_er_halt( BAD_ACC_HLT ); /* halt on the error */ ! 224: if( loop_on_err ) { ! 225: force_loop = TRUE; /* set the force loop flag */ ! 226: asm("brw _divf_4_lp1");; /* and loop on the error */ ! 227: } /* end of loop on error */ ! 228: } /* end of compare error */ ! 229: } /* end of WHILE loop */ ! 230: } /* end of subtest 4 */ ! 231: ! 232: ! 233: ! 234: /************************************************************************ ! 235: * ! 236: * SUBTEST 5 - DIvide, Wait 1 NOP before storing the results ! 237: * ! 238: ************************************************************************/ ! 239: divf_5() ! 240: { ! 241: force_loop = FALSE; ! 242: subtest = 5; ! 243: for( index = 0; index < max_divf_1_index; index++ ) { ! 244: sgl_ld_acc = divf_1_data[index].op_1; /* get operand 1 */ ! 245: sgl_value_1 = divf_1_data[index].op_2; /* get operand 2 */ ! 246: sgl_expected = divf_1_data[index].exp; /* get expected result */ ! 247: /* ! 248: * If LOOP ON ERROR is set, this is the loop for this subtest. ! 249: * The force loop flag is set after the first error. ! 250: */ ! 251: asm("_divf_5_lp1:"); ! 252: asm("ldf _sgl_ld_acc"); /* load the 1st operand */ ! 253: asm("nop"); /* delay */ ! 254: asm("divf _sgl_value_1"); /* divide the 2nd operand */ ! 255: asm("nop"); /* delay before storing */ ! 256: asm("stf _sgl_st_acc"); /* store the result */ ! 257: if( force_loop ) ! 258: asm("brb _divf_5_lp1");; /* loop on the error */ ! 259: /* ! 260: * end error loop - test the results ! 261: */ ! 262: if( sgl_st_acc != sgl_expected ) { /* COMPARE the values */ ! 263: errcnt++; /* bump the error count */ ! 264: if( prt_error ) { ! 265: writes(" \n"); /* start a new print line */ ! 266: writes("cycle: "); ! 267: writed( cycle ); ! 268: writes(" DIVF test "); ! 269: writed( test_no ); ! 270: writes(", subtest 5 (Cache Data - 1 NOP) - BAD FINAL ACC\n"); ! 271: print_divf_data(); ! 272: } ! 273: if( halt_flg ) ! 274: divf_er_halt( BAD_ACC_HLT ); /* halt on the error */ ! 275: if( loop_on_err ) { ! 276: force_loop = TRUE; /* set the force loop flag */ ! 277: asm("brw _divf_5_lp1");; /* and loop on the error */ ! 278: } /* end of loop on error */ ! 279: } /* end of compare error */ ! 280: } /* end of WHILE loop */ ! 281: } /* end of subtest 5 */ ! 282: ! 283: ! 284: ! 285: /************************************************************************ ! 286: * ! 287: * SUBTEST 6 - Check for register corruption ! 288: * ! 289: ************************************************************************/ ! 290: divf_6() ! 291: { ! 292: force_loop = FALSE; /* clear force_loop flg */ ! 293: subtest = 6; ! 294: fill_reg_buf( load_regs ); /* get patterns for regs */ ! 295: index = 0; ! 296: sgl_ld_acc = divf_1_data[0].op_1; /* get operand 1 */ ! 297: sgl_value_1 = divf_1_data[0].op_2; /* get operand 2 */ ! 298: sgl_expected = divf_1_data[0].exp; /* get expected result */ ! 299: /* ! 300: * If LOOP ON ERROR is set, this is the loop for this subtest. ! 301: * The force loop flag is set after the first error. ! 302: */ ! 303: asm("_divf_6_lp1:"); ! 304: asm("ldf _sgl_ld_acc"); /* LOAD the accumulator */ ! 305: asm("nop"); ! 306: asm("loadr $0x1fff,_load_regs"); /* load regs 0 - 12 */ ! 307: asm("nop"); ! 308: asm("divf _sgl_value_1"); /* do the divide */ ! 309: asm("nop"); ! 310: asm("storer $0x1fff,_store_regs"); /* store regs 0 - 12 */ ! 311: asm("stf _sgl_st_acc"); /* save the accumulator */ ! 312: if( force_loop ) ! 313: asm("brb _divf_6_lp1");; /* loop on the error */ ! 314: /* ! 315: * Now compare the stored register values to those that were loaded ! 316: */ ! 317: index2 = 0; ! 318: while( (load_regs[index2] == store_regs[index2]) && (index2 < 13) ) ! 319: index2++; /* check reg values */ ! 320: if( index2 < 13 ) { /* error if index2 < 13 */ ! 321: errcnt++; /* bump the error count */ ! 322: if( prt_error ) { ! 323: writes(" \n"); /* start a new print line */ ! 324: writes("cycle: "); ! 325: writed( cycle ); ! 326: writes(" DIVF test "); ! 327: writed( test_no ); ! 328: writes(", subtest 6 - A REGISTER WAS CHANGED\n"); ! 329: print_divf_data(); /* print the operands */ ! 330: writes("register "); /* print the information */ ! 331: writed( index2 ); /* about the corrupted */ ! 332: writes(" = "); /* register */ ! 333: write32h( store_regs[index2] ); ! 334: writes(", should be = "); ! 335: write32h( load_regs[index2] ); ! 336: writes("\n"); ! 337: } ! 338: if( halt_flg ) ! 339: divf_er_halt( BAD_REG_HLT ); /* halt on the error */ ! 340: if( loop_on_err ) { ! 341: force_loop = TRUE; /* set the force loop flag */ ! 342: asm("brw _divf_6_lp1");; /* and loop on the error */ ! 343: } /* end of loop on error */ ! 344: } /* end of register corruption error */ ! 345: } /* end of subtest 6 */ ! 346: ! 347: ! 348: ! 349: /************************************************************************ ! 350: * ! 351: * SUBTEST 7 - Check for PSL corruption ! 352: * ! 353: ************************************************************************/ ! 354: divf_7() ! 355: { ! 356: force_loop = FALSE; /* clear force_loop flg */ ! 357: subtest = 7; ! 358: fill_reg_buf( load_regs ); /* get patterns for regs */ ! 359: for( index = 0; index < 3; index++ ) { ! 360: sgl_ld_acc = divf_1_data[index].op_1; /* get operand 1 */ ! 361: sgl_value_1 = divf_1_data[index].op_2; /* get operand 2 */ ! 362: sgl_expected = divf_1_data[index].exp; /* get expected */ ! 363: sgl_dummy1 = status_array[status_index]; /* status = +, -, 0 */ ! 364: /* ! 365: * If LOOP ON ERROR is set, this is the loop for this subtest. ! 366: * The force loop flag is set after the first error. ! 367: */ ! 368: asm("_divf_7_lp1:"); ! 369: asm("ldf _sgl_ld_acc"); /* LOAD the accumulator */ ! 370: asm("nop"); ! 371: asm("tstl _sgl_dummy1"); /* set the PSL status */ ! 372: asm("movpsl _init_psl"); /* save the initial PSL */ ! 373: asm("nop"); ! 374: asm("divf _sgl_value_1"); /* do the divide */ ! 375: asm("nop"); ! 376: asm("movpsl _psl_val"); /* save the final PSL */ ! 377: asm("stf _sgl_st_acc"); /* save the accumulator */ ! 378: if( force_loop ) ! 379: asm("brb _divf_7_lp1");; /* loop on the error */ ! 380: /* ! 381: * Now compare the final PSL to the initial PSL -they should be the same ! 382: */ ! 383: exp_psl = init_psl; ! 384: if( psl_val != exp_psl ) { ! 385: errcnt++; /* bump the error count */ ! 386: if( prt_error ) { ! 387: writes(" \n"); /* start a new print line */ ! 388: writes("cycle: "); ! 389: writed( cycle ); ! 390: writes(" DIVF test "); ! 391: writed( test_no ); ! 392: writes(", subtest 7 - INCORRECT FINAL PSL\n"); ! 393: print_divf_data(); /* print the operands */ ! 394: writes("initial PSL = "); ! 395: write32h( init_psl ); ! 396: writes(", final PSL = "); ! 397: write32h( psl_val ); ! 398: writes(", expected PSL = "); ! 399: write32h( exp_psl ); ! 400: writes("\n"); ! 401: } ! 402: if( halt_flg ) ! 403: divf_er_halt( BAD_PSL_HLT ); /* halt on the error */ ! 404: if( loop_on_err ) { ! 405: force_loop = TRUE; /* set the force loop flag */ ! 406: asm("brw _divf_7_lp1");; /* and loop on the error */ ! 407: } /* end of loop on error */ ! 408: } /* end of PSL corruption error */ ! 409: } /* end of WHILE loop */ ! 410: } /* end of subtest 7 */ ! 411: ! 412: ! 413: ! 414: /************************************************************************ ! 415: * ! 416: * SUBTEST 8 - pipelined entry test ! 417: * ! 418: ************************************************************************/ ! 419: divf_8() ! 420: { ! 421: force_loop = FALSE; ! 422: subtest = 8; ! 423: for( index = 0; index < max_divf_1_index; index++ ) { ! 424: sgl_ld_acc = divf_1_data[index].op_1; /* get operand 1 */ ! 425: sgl_value_1 = divf_1_data[index].op_2; /* get operand 2 */ ! 426: sgl_expected = divf_1_data[index].exp; /* get expected result */ ! 427: /* ! 428: * If LOOP ON ERROR is set, this is the loop for this subtest. ! 429: * The force loop flag is set after the first error. ! 430: */ ! 431: asm("_divf_8_lp1:"); ! 432: asm("movl $0,r0"); /* clear r0 */ ! 433: asm("ldf r0"); /* load the Acc. with 0.0 */ ! 434: asm("addf _sgl_ld_acc"); /* add the 1st operand */ ! 435: asm("divf _sgl_value_1"); /* div the 2nd operand */ ! 436: asm("stf _sgl_st_acc"); /* store the result */ ! 437: if( force_loop ) ! 438: asm("brb _divf_8_lp1");; /* loop on the error */ ! 439: /* ! 440: * end error loop - test the results ! 441: */ ! 442: if( sgl_st_acc != sgl_expected ) { /* COMPARE the values */ ! 443: errcnt++; /* bump the error count */ ! 444: if( prt_error ) { ! 445: writes(" \n"); /* start a new print line */ ! 446: writes("cycle: "); ! 447: writed( cycle ); ! 448: writes(" DIVF test "); ! 449: writed( test_no ); ! 450: writes(", subtest 8 (Piped Entry) - BAD FINAL ACC\n"); ! 451: print_divf_data(); ! 452: } ! 453: if( halt_flg ) ! 454: divf_er_halt( BAD_ACC_HLT ); /* halt on the error */ ! 455: if( loop_on_err ) { ! 456: force_loop = TRUE; /* set the force loop flag */ ! 457: asm("brw _divf_8_lp1");; /* and loop on the error */ ! 458: } /* end of loop on error */ ! 459: } /* end of compare error */ ! 460: } /* end of WHILE loop */ ! 461: } /* end of subtest 8 */ ! 462: ! 463: ! 464: ! 465: /************************************************************************ ! 466: * ! 467: * SUBTEST 9 - pipelined exit test ! 468: * ! 469: ************************************************************************/ ! 470: divf_9() ! 471: { ! 472: force_loop = FALSE; ! 473: subtest = 9; ! 474: for( index = 0; index < max_divf_1_index; index++ ) { ! 475: sgl_ld_acc = divf_1_data[index].op_1; /* get operand 1 */ ! 476: sgl_value_1 = divf_1_data[index].op_2; /* get operand 2 */ ! 477: sgl_expected = divf_1_data[index].exp; /* get expected result */ ! 478: /* ! 479: * If LOOP ON ERROR is set, this is the loop for this subtest. ! 480: * The force loop flag is set after the first error. ! 481: */ ! 482: asm("_divf_9_lp1:"); ! 483: asm("movl $0,r0"); /* clear r0 */ ! 484: asm("ldf _sgl_ld_acc"); /* load the 1st operand */ ! 485: asm("divf _sgl_value_1"); /* divide the 2nd operand */ ! 486: asm("addf r0"); /* add a 0.0 to the result */ ! 487: asm("stf _sgl_st_acc"); /* store the result */ ! 488: if( force_loop ) ! 489: asm("brb _divf_9_lp1");; /* loop on the error */ ! 490: /* ! 491: * end error loop - test the results ! 492: */ ! 493: if( sgl_st_acc != sgl_expected ) { /* COMPARE the values */ ! 494: errcnt++; /* bump the error count */ ! 495: if( prt_error ) { ! 496: writes(" \n"); /* start a new print line */ ! 497: writes("cycle: "); ! 498: writed( cycle ); ! 499: writes(" DIVF test "); ! 500: writed( test_no ); ! 501: writes(", subtest 9 (Piped Exit) - BAD FINAL ACC\n"); ! 502: print_divf_data(); ! 503: } ! 504: if( halt_flg ) ! 505: divf_er_halt( BAD_ACC_HLT ); /* halt on the error */ ! 506: if( loop_on_err ) { ! 507: force_loop = TRUE; /* set the force loop flag */ ! 508: asm("brw _divf_9_lp1");; /* and loop on the error */ ! 509: } /* end of loop on error */ ! 510: } /* end of compare error */ ! 511: } /* end of WHILE loop */ ! 512: } /* end of subtest 9 */ ! 513: ! 514: ! 515: ! 516: /************************************************************************** ! 517: * ! 518: * PRINT THE DATA AND STORE RESULTS ! 519: * ! 520: * initial Acc = xxxxxxxx, stored = xxxxxxxx, data index = xx ! 521: * operand = xxxxxxxx, expected = xxxxxxxx ! 522: **************************************************************************/ ! 523: print_divf_data() ! 524: { ! 525: writes("initial Acc = "); ! 526: write32h( sgl_ld_acc ); ! 527: writes(", stored = "); ! 528: write32h( sgl_st_acc ); ! 529: writes(", data index = "); ! 530: writed( index ); ! 531: writec('\n'); ! 532: writes(" operand = "); ! 533: write32h( sgl_value_1 ); ! 534: writes(", expected = "); ! 535: write32h( sgl_expected ); ! 536: writec('\n'); ! 537: } ! 538: ! 539: ! 540: ! 541: /************************************************************************** ! 542: * ! 543: * HALT ON ERROR ROUTINE ! 544: * ! 545: **************************************************************************/ ! 546: divf_er_halt( halt_code ) ! 547: int halt_code; ! 548: { ! 549: sgl_dummy1 = halt_code; /* get the error type */ ! 550: asm("movl _test_no,r0"); /* r0 = test number */ ! 551: asm("movl _subtest,r1"); /* r1 = subtest number */ ! 552: asm("movl _sgl_dummy1,r2"); /* r2 = error code */ ! 553: asm("movl _cycle,r3"); /* r3 = cycle count */ ! 554: asm("movl _sgl_ld_acc,r4"); /* r4 = initial data */ ! 555: asm("movl _sgl_value_1,r5"); /* r5 = data dived */ ! 556: asm("movl _sgl_st_acc,r6"); /* r6 = data stored */ ! 557: if( halt_code == BAD_ACC_HLT ) { ! 558: asm("movl _sgl_expected,r7"); /* r7 = data expected */ ! 559: asm("movl _index,r8"); /* r8 = data index */ ! 560: } else ! 561: if( halt_code == BAD_REG_HLT ) { ! 562: sgl_dummy1 = load_regs[index2]; ! 563: sgl_dummy2 = store_regs[index2]; ! 564: asm("movl _index2,r7"); /* r7 = bad register # */ ! 565: asm("movl _sgl_dummy2,r8"); /* r8 = actual value */ ! 566: asm("movl _sgl_dummy1,r9"); /* r9 = expected value */ ! 567: } else ! 568: if( halt_code == BAD_PSL_HLT ) { ! 569: asm("movl _init_psl,r7"); /* r7 = initial PSL */ ! 570: asm("movl _psl_val,r8"); /* r8 = final PSL */ ! 571: asm("movl _exp_psl,r9"); /* r9 = expected PSL */ ! 572: }; ! 573: asm("halt"); /* HALT ... */ ! 574: }
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