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Up to [Power 6/32 Unix Tahoe 4.2BSD] / cci / d / macro4|
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1.1 ! root 1: 1 00000000 LL0: ! 2: 2 00000000 .data ! 3: 3 00000d28 * .text ! 4: 4 00000000 .align 1 ! 5: 5 00000000 .globl _divf ! 6: 6 00000000 _divf: ! 7: 7 0000FAE8 0000 .word L215 ! 8: 8 0000FAEA # #include "fpp_defs.h" ! 9: 9 0000FAEA # ! 10: 10 0000FAEA # ! 11: 11 0000FAEA # /***************************************************************************** ! 12: 12 0000FAEA # * ! 13: 13 0000FAEA # * DIVF - SINGLE PRECISION FLOATING POINT ADD TEST ! 14: 14 0000FAEA # * ! 15: 15 0000FAEA # *****************************************************************************/ ! 16: 16 0000FAEA # divf() ! 17: 17 0000FAEA # { ! 18: 18 0000FAEA 11 64 jbr L217 ! 19: 19 0000FAEC L218: ! 20: 20 0000FAEC # asm(".globl _divf_t"); ! 21: 21 0000FAEC .globl _divf_t ! 22: 22 0000FAEC # asm("_divf_t:"); /* entry address */ ! 23: 23 0000FAEC _divf_t: ! 24: 24 0000FAEC # if( ( cycle == 1 ) && ( prt_hdrs ) ) /* print headers on 1st pass */ ! 25: 25 0000FAEC 1d effffffff6 01 cmpl _cycle,$1 ! 26: 26 0000FAF3 21 15 jneq L219 ! 27: 27 0000FAF5 5d efffffffed tstl _prt_hdrs ! 28: 28 0000FAFB 31 0d jeql L219 ! 29: 29 0000FAFD # writes(" DIVF"); ! 30: 30 0000FAFD .data 1 ! 31: 31 00000d28 * L221: ! 32: 32 00000d28 * 204449564600 .ascii " DIVF\0" ! 33: 33 00000d2e * .text ! 34: 34 0000FAFD dd 8f00000d28 pushl $L221 ! 35: 35 0000FB03 fe 08 efffffffde callf $8,_writes ! 36: 36 0000FB0A # divf_1(); /* div through a register */ ! 37: 37 0000FB0A L219: ! 38: 38 0000FB0A fe 04 ef00000041 callf $4,_divf_1 ! 39: 39 0000FB11 # divf_2(); /* div through the cache */ ! 40: 40 0000FB11 fe 04 ef00000160 callf $4,_divf_2 ! 41: 41 0000FB18 # divf_3(); /* wait 3 NOPs */ ! 42: 42 0000FB18 fe 04 ef00000279 callf $4,_divf_3 ! 43: 43 0000FB1F # divf_4(); /* wait 2 NOPs */ ! 44: 44 0000FB1F fe 04 ef00000396 callf $4,_divf_4 ! 45: 45 0000FB26 # divf_5(); /* wait 1 NOP before storing */ ! 46: 46 0000FB26 fe 04 ef000004b3 callf $4,_divf_5 ! 47: 47 0000FB2D # divf_6(); /* register stability test */ ! 48: 48 0000FB2D fe 04 ef000005ce callf $4,_divf_6 ! 49: 49 0000FB34 # divf_7(); /* PSL stability test */ ! 50: 50 0000FB34 fe 04 ef00000777 callf $4,_divf_7 ! 51: 51 0000FB3B # divf_8(); /* pipelined entry test */ ! 52: 52 0000FB3B fe 04 ef0000092a callf $4,_divf_8 ! 53: 53 0000FB42 # divf_9(); /* pipelined exit test */ ! 54: 54 0000FB42 fe 04 ef00000a49 callf $4,_divf_9 ! 55: 55 0000FB49 # asm("jmp *return"); /* return to the test monitor */ ! 56: 56 0000FB49 71 ffffffff99 jmp *return ! 57: 57 0000FB4F # } ! 58: 58 0000FB4F 40 ret#2 ! 59: 59 0000FB50 .set L215,0x0 ! 60: 60 0000FB50 L217: ! 61: 61 0000FB50 11 9a jbr L218 ! 62: 62 0000FB52 .data ! 63: 63 00000d28 * .text ! 64: 64 0000FB52 .align 1 ! 65: 65 0000FB52 .globl _divf_1 ! 66: 66 0000FB52 _divf_1: ! 67: 67 0000FB52 0000 .word L231 ! 68: 68 0000FB54 # ! 69: 69 0000FB54 # ! 70: 70 0000FB54 # ! 71: 71 0000FB54 # /************************************************************************ ! 72: 72 0000FB54 # * ! 73: 73 0000FB54 # * SUBTEST 1 - divide through a register ! 74: 74 0000FB54 # * ! 75: 75 0000FB54 # ************************************************************************/ ! 76: 76 0000FB54 # divf_1() ! 77: 77 0000FB54 # { ! 78: 78 0000FB54 13 011e jbr L233 ! 79: 79 0000FB57 L234: ! 80: 80 0000FB57 # force_loop = FALSE; ! 81: 81 0000FB57 4d efffffff8b clrl _force_loop ! 82: 82 0000FB5D # subtest = 1; ! 83: 83 0000FB5D 0d 01 efffffff84 movl $1,_subtest ! 84: 84 0000FB64 # for( index = 0; index < max_divf_1_index; index++ ) { ! 85: 85 0000FB64 4d efffffff7e clrl _index ! 86: 86 0000FB6A L237: ! 87: 87 0000FB6A 1d efffffff78 efffffff73 cmpl _index,_max_divf_1_index ! 88: 88 0000FB75 91 03 13 00fa jgeq L236 ! 89: 89 0000FB7A # sgl_ld_acc = divf_1_data[index].op_1; /* get operand 1 */ ! 90: 90 0000FB7A 5c 0c efffffff67 50 mull3 $12,_index,r0 ! 91: 91 0000FB82 0d e000000000 efffffff5b movl _divf_1_data(r0),_sgl_ld_acc ! 92: 92 0000FB8D # sgl_value_1 = divf_1_data[index].op_2; /* get operand 2 */ ! 93: 93 0000FB8D 5c 0c efffffff54 50 mull3 $12,_index,r0 ! 94: 94 0000FB95 0d e000000004 efffffff48 movl _divf_1_data+4(r0),_sgl_value_1 ! 95: 95 0000FBA0 # sgl_expected = divf_1_data[index].exp; /* get expected result */ ! 96: 96 0000FBA0 5c 0c efffffff41 50 mull3 $12,_index,r0 ! 97: 97 0000FBA8 0d e000000008 efffffff35 movl _divf_1_data+8(r0),_sgl_expected ! 98: 98 0000FBB3 # /* ! 99: 99 0000FBB3 # * If LOOP ON ERROR is set, this is the loop for this subtest. ! 100: 100 0000FBB3 # * The force loop flag is set after the first error. ! 101: 101 0000FBB3 # */ ! 102: 102 0000FBB3 # asm("_divf_1_lp1:"); ! 103: 103 0000FBB3 _divf_1_lp1: ! 104: 104 0000FBB3 # asm("movl _sgl_ld_acc,r3"); /* move the 1st data to r3 */ ! 105: 105 0000FBB3 0d efffffff2f 53 movl _sgl_ld_acc,r3 ! 106: 106 0000FBBA # asm("movl _sgl_value_1,r4"); /* move the 2nd data to r4 */ ! 107: 107 0000FBBA 0d efffffff28 54 movl _sgl_value_1,r4 ! 108: 108 0000FBC1 # asm("ldf r3"); /* load the 1st operand */ ! 109: 109 0000FBC1 06 53 ldf r3 ! 110: 110 0000FBC3 # asm("divf r4"); /* divide the 2nd operand */ ! 111: 111 0000FBC3 f6 54 divf r4 ! 112: 112 0000FBC5 # asm("stf _sgl_st_acc"); /* store the result */ ! 113: 113 0000FBC5 26 efffffff1d stf _sgl_st_acc ! 114: 114 0000FBCB # if( force_loop ) ! 115: 115 0000FBCB 5d efffffff17 tstl _force_loop ! 116: 116 0000FBD1 31 02 jeql L238 ! 117: 117 0000FBD3 # asm("brb _divf_1_lp1");; /* loop on the error */ ! 118: 118 0000FBD3 11 de brb _divf_1_lp1 ! 119: 119 0000FBD5 L238: ! 120: 120 0000FBD5 # /* ! 121: 121 0000FBD5 # * end error loop - test the results ! 122: 122 0000FBD5 # */ ! 123: 123 0000FBD5 # if( sgl_st_acc != sgl_expected ) { /* COMPARE the values */ ! 124: 124 0000FBD5 1d efffffff0d efffffff08 cmpl _sgl_st_acc,_sgl_expected ! 125: 125 0000FBE0 21 03 13 0086 jeql L239 ! 126: 126 0000FBE5 # errcnt++; /* bump the error count */ ! 127: 127 0000FBE5 6d effffffefd incl _errcnt ! 128: 128 0000FBEB # if( prt_error ) { ! 129: 129 0000FBEB 5d effffffef7 tstl _prt_error ! 130: 130 0000FBF1 31 55 jeql L240 ! 131: 131 0000FBF3 # writes(" \n"); /* start a new print line */ ! 132: 132 0000FBF3 .data 1 ! 133: 133 00000d2e * L241: ! 134: 134 00000d2e * 200A00 .ascii " \12\0" ! 135: 135 00000d31 * .text ! 136: 136 0000FBF3 dd 8f00000d2e pushl $L241 ! 137: 137 0000FBF9 fe 08 effffffee8 callf $8,_writes ! 138: 138 0000FC00 # writes("cycle: "); ! 139: 139 0000FC00 .data 1 ! 140: 140 00000d31 * L242: ! 141: 141 00000d31 * 6379636C653A2000 .ascii "cycle: \0" ! 142: 142 00000d39 * .text ! 143: 143 0000FC00 dd 8f00000d31 pushl $L242 ! 144: 144 0000FC06 fe 08 effffffedb callf $8,_writes ! 145: 145 0000FC0D # writed( cycle ); ! 146: 146 0000FC0D dd effffffed5 pushl _cycle ! 147: 147 0000FC13 fe 08 effffffece callf $8,_writed ! 148: 148 0000FC1A # writes(" DIVF test "); ! 149: 149 0000FC1A .data 1 ! 150: 150 00000d39 * L244: ! 151: 151 00000d39 * 2020444956462074657374200 .ascii " DIVF test \0" ! 152: 0 ! 153: 152 00000d46 * .text ! 154: 153 0000FC1A dd 8f00000d39 pushl $L244 ! 155: 154 0000FC20 fe 08 effffffec1 callf $8,_writes ! 156: 155 0000FC27 # writed( test_no ); ! 157: 156 0000FC27 dd effffffebb pushl _test_no ! 158: 157 0000FC2D fe 08 effffffeb4 callf $8,_writed ! 159: 158 0000FC34 # writes(", subtest 1 (Reg. Data) - BAD FINAL ACC\n"); ! 160: 159 0000FC34 .data 1 ! 161: 160 00000d46 * L245: ! 162: 161 00000d46 * 2C20737562746573742031202 .ascii ", subtest 1 (Reg. Data) - BAD FINAL ACC\12\0" ! 163: 85265672E204461746129202D ! 164: 204241442046494E414C20414 ! 165: 3430A00 ! 166: 162 00000d6f * .text ! 167: 163 0000FC34 dd 8f00000d46 pushl $L245 ! 168: 164 0000FC3A fe 08 effffffea7 callf $8,_writes ! 169: 165 0000FC41 # print_divf_data(); ! 170: 166 0000FC41 fe 04 ef00000a70 callf $4,_print_divf_data ! 171: 167 0000FC48 # } ! 172: 168 0000FC48 # if( halt_flg ) ! 173: 169 0000FC48 L240: ! 174: 170 0000FC48 5d effffffe9a tstl _halt_flg ! 175: 171 0000FC4E 31 09 jeql L247 ! 176: 172 0000FC50 # divf_er_halt( BAD_ACC_HLT ); /* halt on the error */ ! 177: 173 0000FC50 dd 01 pushl $1 ! 178: 174 0000FC52 fe 08 ef00000afd callf $8,_divf_er_halt ! 179: 175 0000FC59 # if( loop_on_err ) { ! 180: 176 0000FC59 L247: ! 181: 177 0000FC59 5d effffffe89 tstl _loop_on_err ! 182: 178 0000FC5F 31 0a jeql L249 ! 183: 179 0000FC61 # force_loop = TRUE; /* set the force loop flag */ ! 184: 180 0000FC61 0d 01 effffffe80 movl $1,_force_loop ! 185: 181 0000FC68 # asm("brw _divf_1_lp1");; /* and loop on the error */ ! 186: 182 0000FC68 13 ff48 brw _divf_1_lp1 ! 187: 183 0000FC6B # } /* end of loop on error */ ! 188: 184 0000FC6B # } /* end of compare error */ ! 189: 185 0000FC6B L249: ! 190: 186 0000FC6B # } /* end of WHILE loop */ ! 191: 187 0000FC6B L239: ! 192: 188 0000FC6B L235: ! 193: 189 0000FC6B 6d effffffe77 incl _index ! 194: 190 0000FC71 13 fef6 jbr L237 ! 195: 191 0000FC74 L236: ! 196: 192 0000FC74 # } /* end of subtest 1 */ ! 197: 193 0000FC74 40 ret#2 ! 198: 194 0000FC75 .set L231,0x0 ! 199: 195 0000FC75 L233: ! 200: 196 0000FC75 13 fedf jbr L234 ! 201: 197 0000FC78 .data ! 202: 198 00000d28 * .text ! 203: 199 0000FC78 .align 1 ! 204: 200 0000FC78 .globl _divf_2 ! 205: 201 0000FC78 _divf_2: ! 206: 202 0000FC78 0000 .word L250 ! 207: 203 0000FC7A # ! 208: 204 0000FC7A # ! 209: 205 0000FC7A # ! 210: 206 0000FC7A # /************************************************************************ ! 211: 207 0000FC7A # * ! 212: 208 0000FC7A # * SUBTEST 2 - divide through memory ! 213: 209 0000FC7A # * ! 214: 210 0000FC7A # ************************************************************************/ ! 215: 211 0000FC7A # divf_2() ! 216: 212 0000FC7A # { ! 217: 213 0000FC7A 13 0118 jbr L252 ! 218: 214 0000FC7D L253: ! 219: 215 0000FC7D # force_loop = FALSE; ! 220: 216 0000FC7D 4d effffffe65 clrl _force_loop ! 221: 217 0000FC83 # subtest = 2; ! 222: 218 0000FC83 0d 02 effffffe5e movl $2,_subtest ! 223: 219 0000FC8A # for( index = 0; index < max_divf_1_index; index++ ) { ! 224: 220 0000FC8A 4d effffffe58 clrl _index ! 225: 221 0000FC90 L256: ! 226: 222 0000FC90 1d effffffe52 effffffe4d cmpl _index,_max_divf_1_index ! 227: 223 0000FC9B 91 03 13 00f4 jgeq L255 ! 228: 224 0000FCA0 # sgl_ld_acc = divf_1_data[index].op_1; /* get operand 1 */ ! 229: 225 0000FCA0 5c 0c effffffe41 50 mull3 $12,_index,r0 ! 230: 226 0000FCA8 0d e000000000 effffffe35 movl _divf_1_data(r0),_sgl_ld_acc ! 231: 227 0000FCB3 # sgl_value_1 = divf_1_data[index].op_2; /* get operand 2 */ ! 232: 228 0000FCB3 5c 0c effffffe2e 50 mull3 $12,_index,r0 ! 233: 229 0000FCBB 0d e000000004 effffffe22 movl _divf_1_data+4(r0),_sgl_value_1 ! 234: 230 0000FCC6 # sgl_expected = divf_1_data[index].exp; /* get expected result */ ! 235: 231 0000FCC6 5c 0c effffffe1b 50 mull3 $12,_index,r0 ! 236: 232 0000FCCE 0d e000000008 effffffe0f movl _divf_1_data+8(r0),_sgl_expected ! 237: 233 0000FCD9 # /* ! 238: 234 0000FCD9 # * If LOOP ON ERROR is set, this is the loop for this subtest. ! 239: 235 0000FCD9 # * The force loop flag is set after the first error. ! 240: 236 0000FCD9 # */ ! 241: 237 0000FCD9 # asm("_divf_2_lp1:"); ! 242: 238 0000FCD9 _divf_2_lp1: ! 243: 239 0000FCD9 # asm("ldf _sgl_ld_acc"); /* load the 1st operand */ ! 244: 240 0000FCD9 06 effffffe09 ldf _sgl_ld_acc ! 245: 241 0000FCDF # asm("divf _sgl_value_1"); /* divide the 2nd operand */ ! 246: 242 0000FCDF f6 effffffe03 divf _sgl_value_1 ! 247: 243 0000FCE5 # asm("stf _sgl_st_acc"); /* store the result */ ! 248: 244 0000FCE5 26 effffffdfd stf _sgl_st_acc ! 249: 245 0000FCEB # if( force_loop ) ! 250: 246 0000FCEB 5d effffffdf7 tstl _force_loop ! 251: 247 0000FCF1 31 02 jeql L257 ! 252: 248 0000FCF3 # asm("brb _divf_2_lp1");; /* loop on the error */ ! 253: 249 0000FCF3 11 e4 brb _divf_2_lp1 ! 254: 250 0000FCF5 L257: ! 255: 251 0000FCF5 # /* ! 256: 252 0000FCF5 # * end error loop - test the results ! 257: 253 0000FCF5 # */ ! 258: 254 0000FCF5 # if( sgl_st_acc != sgl_expected ) { /* COMPARE the values */ ! 259: 255 0000FCF5 1d effffffded effffffde8 cmpl _sgl_st_acc,_sgl_expected ! 260: 256 0000FD00 21 03 13 0086 jeql L258 ! 261: 257 0000FD05 # errcnt++; /* bump the error count */ ! 262: 258 0000FD05 6d effffffddd incl _errcnt ! 263: 259 0000FD0B # if( prt_error ) { ! 264: 260 0000FD0B 5d effffffdd7 tstl _prt_error ! 265: 261 0000FD11 31 55 jeql L259 ! 266: 262 0000FD13 # writes(" \n"); /* start a new print line */ ! 267: 263 0000FD13 .data 1 ! 268: 264 00000d6f * L260: ! 269: 265 00000d6f * 200A00 .ascii " \12\0" ! 270: 266 00000d72 * .text ! 271: 267 0000FD13 dd 8f00000d6f pushl $L260 ! 272: 268 0000FD19 fe 08 effffffdc8 callf $8,_writes ! 273: 269 0000FD20 # writes("cycle: "); ! 274: 270 0000FD20 .data 1 ! 275: 271 00000d72 * L261: ! 276: 272 00000d72 * 6379636C653A2000 .ascii "cycle: \0" ! 277: 273 00000d7a * .text ! 278: 274 0000FD20 dd 8f00000d72 pushl $L261 ! 279: 275 0000FD26 fe 08 effffffdbb callf $8,_writes ! 280: 276 0000FD2D # writed( cycle ); ! 281: 277 0000FD2D dd effffffdb5 pushl _cycle ! 282: 278 0000FD33 fe 08 effffffdae callf $8,_writed ! 283: 279 0000FD3A # writes(" DIVF test "); ! 284: 280 0000FD3A .data 1 ! 285: 281 00000d7a * L262: ! 286: 282 00000d7a * 2020444956462074657374200 .ascii " DIVF test \0" ! 287: 0 ! 288: 283 00000d87 * .text ! 289: 284 0000FD3A dd 8f00000d7a pushl $L262 ! 290: 285 0000FD40 fe 08 effffffda1 callf $8,_writes ! 291: 286 0000FD47 # writed( test_no ); ! 292: 287 0000FD47 dd effffffd9b pushl _test_no ! 293: 288 0000FD4D fe 08 effffffd94 callf $8,_writed ! 294: 289 0000FD54 # writes(", subtest 2 (Cache Data) - BAD FINAL ACC\n"); ! 295: 290 0000FD54 .data 1 ! 296: 291 00000d87 * L263: ! 297: 292 00000d87 * 2C20737562746573742032202 .ascii ", subtest 2 (Cache Data) - BAD FINAL ACC\12\0" ! 298: 8436163686520446174612920 ! 299: 2D204241442046494E414C204 ! 300: 143430A00 ! 301: 293 00000db1 * .text ! 302: 294 0000FD54 dd 8f00000d87 pushl $L263 ! 303: 295 0000FD5A fe 08 effffffd87 callf $8,_writes ! 304: 296 0000FD61 # print_divf_data(); ! 305: 297 0000FD61 fe 04 ef00000950 callf $4,_print_divf_data ! 306: 298 0000FD68 # } ! 307: 299 0000FD68 # if( halt_flg ) ! 308: 300 0000FD68 L259: ! 309: 301 0000FD68 5d effffffd7a tstl _halt_flg ! 310: 302 0000FD6E 31 09 jeql L264 ! 311: 303 0000FD70 # divf_er_halt( BAD_ACC_HLT ); /* halt on the error */ ! 312: 304 0000FD70 dd 01 pushl $1 ! 313: 305 0000FD72 fe 08 ef000009dd callf $8,_divf_er_halt ! 314: 306 0000FD79 # if( loop_on_err ) { ! 315: 307 0000FD79 L264: ! 316: 308 0000FD79 5d effffffd69 tstl _loop_on_err ! 317: 309 0000FD7F 31 0a jeql L265 ! 318: 310 0000FD81 # force_loop = TRUE; /* set the force loop flag */ ! 319: 311 0000FD81 0d 01 effffffd60 movl $1,_force_loop ! 320: 312 0000FD88 # asm("brw _divf_2_lp1");; /* and loop on the error */ ! 321: 313 0000FD88 13 ff4e brw _divf_2_lp1 ! 322: 314 0000FD8B # } /* end of loop on error */ ! 323: 315 0000FD8B # } /* end of compare error */ ! 324: 316 0000FD8B L265: ! 325: 317 0000FD8B # } /* end of WHILE loop */ ! 326: 318 0000FD8B L258: ! 327: 319 0000FD8B L254: ! 328: 320 0000FD8B 6d effffffd57 incl _index ! 329: 321 0000FD91 13 fefc jbr L256 ! 330: 322 0000FD94 L255: ! 331: 323 0000FD94 # } /* end of subtest 2 */ ! 332: 324 0000FD94 40 ret#2 ! 333: 325 0000FD95 .set L250,0x0 ! 334: 326 0000FD95 L252: ! 335: 327 0000FD95 13 fee5 jbr L253 ! 336: 328 0000FD98 .data ! 337: 329 00000d28 * .text ! 338: 330 0000FD98 .align 1 ! 339: 331 0000FD98 .globl _divf_3 ! 340: 332 0000FD98 _divf_3: ! 341: 333 0000FD98 0000 .word L266 ! 342: 334 0000FD9A # ! 343: 335 0000FD9A # ! 344: 336 0000FD9A # ! 345: 337 0000FD9A # /************************************************************************ ! 346: 338 0000FD9A # * ! 347: 339 0000FD9A # * SUBTEST 3 - Divide, Wait 3 NOPs before storing the results ! 348: 340 0000FD9A # * ! 349: 341 0000FD9A # ************************************************************************/ ! 350: 342 0000FD9A # divf_3() ! 351: 343 0000FD9A # { ! 352: 344 0000FD9A 13 011c jbr L268 ! 353: 345 0000FD9D L269: ! 354: 346 0000FD9D # force_loop = FALSE; ! 355: 347 0000FD9D 4d effffffd45 clrl _force_loop ! 356: 348 0000FDA3 # subtest = 3; ! 357: 349 0000FDA3 0d 03 effffffd3e movl $3,_subtest ! 358: 350 0000FDAA # for( index = 0; index < max_divf_1_index; index++ ) { ! 359: 351 0000FDAA 4d effffffd38 clrl _index ! 360: 352 0000FDB0 L272: ! 361: 353 0000FDB0 1d effffffd32 effffffd2d cmpl _index,_max_divf_1_index ! 362: 354 0000FDBB 91 03 13 00f8 jgeq L271 ! 363: 355 0000FDC0 # sgl_ld_acc = divf_1_data[index].op_1; /* get operand 1 */ ! 364: 356 0000FDC0 5c 0c effffffd21 50 mull3 $12,_index,r0 ! 365: 357 0000FDC8 0d e000000000 effffffd15 movl _divf_1_data(r0),_sgl_ld_acc ! 366: 358 0000FDD3 # sgl_value_1 = divf_1_data[index].op_2; /* get operand 2 */ ! 367: 359 0000FDD3 5c 0c effffffd0e 50 mull3 $12,_index,r0 ! 368: 360 0000FDDB 0d e000000004 effffffd02 movl _divf_1_data+4(r0),_sgl_value_1 ! 369: 361 0000FDE6 # sgl_expected = divf_1_data[index].exp; /* get expected result */ ! 370: 362 0000FDE6 5c 0c effffffcfb 50 mull3 $12,_index,r0 ! 371: 363 0000FDEE 0d e000000008 effffffcef movl _divf_1_data+8(r0),_sgl_expected ! 372: 364 0000FDF9 # /* ! 373: 365 0000FDF9 # * If LOOP ON ERROR is set, this is the loop for this subtest. ! 374: 366 0000FDF9 # * The force loop flag is set after the first error. ! 375: 367 0000FDF9 # */ ! 376: 368 0000FDF9 # asm("_divf_3_lp1:"); ! 377: 369 0000FDF9 _divf_3_lp1: ! 378: 370 0000FDF9 # asm("ldf _sgl_ld_acc"); /* load the 1st operand */ ! 379: 371 0000FDF9 06 effffffce9 ldf _sgl_ld_acc ! 380: 372 0000FDFF # asm("nop"); /* delay */ ! 381: 373 0000FDFF 10 nop ! 382: 374 0000FE00 # asm("divf _sgl_value_1"); /* divide the 2nd operand */ ! 383: 375 0000FE00 f6 effffffce2 divf _sgl_value_1 ! 384: 376 0000FE06 # asm("nop"); /* delay before ... */ ! 385: 377 0000FE06 10 nop ! 386: 378 0000FE07 # asm("nop"); ! 387: 379 0000FE07 10 nop ! 388: 380 0000FE08 # asm("nop"); /* ... storing the result */ ! 389: 381 0000FE08 10 nop ! 390: 382 0000FE09 # asm("stf _sgl_st_acc"); /* store the result */ ! 391: 383 0000FE09 26 effffffcd9 stf _sgl_st_acc ! 392: 384 0000FE0F # if( force_loop ) ! 393: 385 0000FE0F 5d effffffcd3 tstl _force_loop ! 394: 386 0000FE15 31 02 jeql L273 ! 395: 387 0000FE17 # asm("brb _divf_3_lp1");; /* loop on the error */ ! 396: 388 0000FE17 11 e0 brb _divf_3_lp1 ! 397: 389 0000FE19 L273: ! 398: 390 0000FE19 # /* ! 399: 391 0000FE19 # * end error loop - test the results ! 400: 392 0000FE19 # */ ! 401: 393 0000FE19 # if( sgl_st_acc != sgl_expected ) { /* COMPARE the values */ ! 402: 394 0000FE19 1d effffffcc9 effffffcc4 cmpl _sgl_st_acc,_sgl_expected ! 403: 395 0000FE24 21 03 13 0086 jeql L274 ! 404: 396 0000FE29 # errcnt++; /* bump the error count */ ! 405: 397 0000FE29 6d effffffcb9 incl _errcnt ! 406: 398 0000FE2F # if( prt_error ) { ! 407: 399 0000FE2F 5d effffffcb3 tstl _prt_error ! 408: 400 0000FE35 31 55 jeql L275 ! 409: 401 0000FE37 # writes(" \n"); /* start a new print line */ ! 410: 402 0000FE37 .data 1 ! 411: 403 00000db1 * L276: ! 412: 404 00000db1 * 200A00 .ascii " \12\0" ! 413: 405 00000db4 * .text ! 414: 406 0000FE37 dd 8f00000db1 pushl $L276 ! 415: 407 0000FE3D fe 08 effffffca4 callf $8,_writes ! 416: 408 0000FE44 # writes("cycle: "); ! 417: 409 0000FE44 .data 1 ! 418: 410 00000db4 * L277: ! 419: 411 00000db4 * 6379636C653A2000 .ascii "cycle: \0" ! 420: 412 00000dbc * .text ! 421: 413 0000FE44 dd 8f00000db4 pushl $L277 ! 422: 414 0000FE4A fe 08 effffffc97 callf $8,_writes ! 423: 415 0000FE51 # writed( cycle ); ! 424: 416 0000FE51 dd effffffc91 pushl _cycle ! 425: 417 0000FE57 fe 08 effffffc8a callf $8,_writed ! 426: 418 0000FE5E # writes(" DIVF test "); ! 427: 419 0000FE5E .data 1 ! 428: 420 00000dbc * L278: ! 429: 421 00000dbc * 2020444956462074657374200 .ascii " DIVF test \0" ! 430: 0 ! 431: 422 00000dc9 * .text ! 432: 423 0000FE5E dd 8f00000dbc pushl $L278 ! 433: 424 0000FE64 fe 08 effffffc7d callf $8,_writes ! 434: 425 0000FE6B # writed( test_no ); ! 435: 426 0000FE6B dd effffffc77 pushl _test_no ! 436: 427 0000FE71 fe 08 effffffc70 callf $8,_writed ! 437: 428 0000FE78 # writes(", subtest 3 (Cache data - 3 NOPs) - BAD FINAL ACC\n"); ! 438: 429 0000FE78 .data 1 ! 439: 430 00000dc9 * L279: ! 440: 431 00000dc9 * 2C20737562746573742033202 .ascii ", subtest 3 (Cache data - 3 NOPs) - BAD FINAL ACC\12\0" ! 441: 843616368652064617461202D ! 442: 2033204E4F507329202D20424 ! 443: 1442046494E414C204143430A ! 444: 00 ! 445: 432 00000dfc * .text ! 446: 433 0000FE78 dd 8f00000dc9 pushl $L279 ! 447: 434 0000FE7E fe 08 effffffc63 callf $8,_writes ! 448: 435 0000FE85 # print_divf_data(); ! 449: 436 0000FE85 fe 04 ef0000082c callf $4,_print_divf_data ! 450: 437 0000FE8C # } ! 451: 438 0000FE8C # if( halt_flg ) ! 452: 439 0000FE8C L275: ! 453: 440 0000FE8C 5d effffffc56 tstl _halt_flg ! 454: 441 0000FE92 31 09 jeql L280 ! 455: 442 0000FE94 # divf_er_halt( BAD_ACC_HLT ); /* halt on the error */ ! 456: 443 0000FE94 dd 01 pushl $1 ! 457: 444 0000FE96 fe 08 ef000008b9 callf $8,_divf_er_halt ! 458: 445 0000FE9D # if( loop_on_err ) { ! 459: 446 0000FE9D L280: ! 460: 447 0000FE9D 5d effffffc45 tstl _loop_on_err ! 461: 448 0000FEA3 31 0a jeql L281 ! 462: 449 0000FEA5 # force_loop = TRUE; /* set the force loop flag */ ! 463: 450 0000FEA5 0d 01 effffffc3c movl $1,_force_loop ! 464: 451 0000FEAC # asm("brw _divf_3_lp1");; /* and loop on the error */ ! 465: 452 0000FEAC 13 ff4a brw _divf_3_lp1 ! 466: 453 0000FEAF # } /* end of loop on error */ ! 467: 454 0000FEAF # } /* end of compare error */ ! 468: 455 0000FEAF L281: ! 469: 456 0000FEAF # } /* end of WHILE loop */ ! 470: 457 0000FEAF L274: ! 471: 458 0000FEAF L270: ! 472: 459 0000FEAF 6d effffffc33 incl _index ! 473: 460 0000FEB5 13 fef8 jbr L272 ! 474: 461 0000FEB8 L271: ! 475: 462 0000FEB8 # } /* end of subtest 3 */ ! 476: 463 0000FEB8 40 ret#2 ! 477: 464 0000FEB9 .set L266,0x0 ! 478: 465 0000FEB9 L268: ! 479: 466 0000FEB9 13 fee1 jbr L269 ! 480: 467 0000FEBC .data ! 481: 468 00000d28 * .text ! 482: 469 0000FEBC .align 1 ! 483: 470 0000FEBC .globl _divf_4 ! 484: 471 0000FEBC _divf_4: ! 485: 472 0000FEBC 0000 .word L282 ! 486: 473 0000FEBE # ! 487: 474 0000FEBE # ! 488: 475 0000FEBE # ! 489: 476 0000FEBE # /************************************************************************ ! 490: 477 0000FEBE # * ! 491: 478 0000FEBE # * SUBTEST 4 - Divide, Wait 2 NOPs before storing the results ! 492: 479 0000FEBE # * ! 493: 480 0000FEBE # ************************************************************************/ ! 494: 481 0000FEBE # divf_4() ! 495: 482 0000FEBE # { ! 496: 483 0000FEBE 13 011b jbr L284 ! 497: 484 0000FEC1 L285: ! 498: 485 0000FEC1 # force_loop = FALSE; ! 499: 486 0000FEC1 4d effffffc21 clrl _force_loop ! 500: 487 0000FEC7 # subtest = 4; ! 501: 488 0000FEC7 0d 04 effffffc1a movl $4,_subtest ! 502: 489 0000FECE # for( index = 0; index < max_divf_1_index; index++ ) { ! 503: 490 0000FECE 4d effffffc14 clrl _index ! 504: 491 0000FED4 L288: ! 505: 492 0000FED4 1d effffffc0e effffffc09 cmpl _index,_max_divf_1_index ! 506: 493 0000FEDF 91 03 13 00f7 jgeq L287 ! 507: 494 0000FEE4 # sgl_ld_acc = divf_1_data[index].op_1; /* get operand 1 */ ! 508: 495 0000FEE4 5c 0c effffffbfd 50 mull3 $12,_index,r0 ! 509: 496 0000FEEC 0d e000000000 effffffbf1 movl _divf_1_data(r0),_sgl_ld_acc ! 510: 497 0000FEF7 # sgl_value_1 = divf_1_data[index].op_2; /* get operand 2 */ ! 511: 498 0000FEF7 5c 0c effffffbea 50 mull3 $12,_index,r0 ! 512: 499 0000FEFF 0d e000000004 effffffbde movl _divf_1_data+4(r0),_sgl_value_1 ! 513: 500 0000FF0A # sgl_expected = divf_1_data[index].exp; /* get expected result */ ! 514: 501 0000FF0A 5c 0c effffffbd7 50 mull3 $12,_index,r0 ! 515: 502 0000FF12 0d e000000008 effffffbcb movl _divf_1_data+8(r0),_sgl_expected ! 516: 503 0000FF1D # /* ! 517: 504 0000FF1D # * If LOOP ON ERROR is set, this is the loop for this subtest. ! 518: 505 0000FF1D # * The force loop flag is set after the first error. ! 519: 506 0000FF1D # */ ! 520: 507 0000FF1D # asm("_divf_4_lp1:"); ! 521: 508 0000FF1D _divf_4_lp1: ! 522: 509 0000FF1D # asm("ldf _sgl_ld_acc"); /* load the 1st operand */ ! 523: 510 0000FF1D 06 effffffbc5 ldf _sgl_ld_acc ! 524: 511 0000FF23 # asm("nop"); /* delay */ ! 525: 512 0000FF23 10 nop ! 526: 513 0000FF24 # asm("divf _sgl_value_1"); /* divide the 2nd operand */ ! 527: 514 0000FF24 f6 effffffbbe divf _sgl_value_1 ! 528: 515 0000FF2A # asm("nop"); /* delay before ... */ ! 529: 516 0000FF2A 10 nop ! 530: 517 0000FF2B # asm("nop"); /* ... storing the result */ ! 531: 518 0000FF2B 10 nop ! 532: 519 0000FF2C # asm("stf _sgl_st_acc"); /* store the result */ ! 533: 520 0000FF2C 26 effffffbb6 stf _sgl_st_acc ! 534: 521 0000FF32 # if( force_loop ) ! 535: 522 0000FF32 5d effffffbb0 tstl _force_loop ! 536: 523 0000FF38 31 02 jeql L289 ! 537: 524 0000FF3A # asm("brb _divf_4_lp1");; /* loop on the error */ ! 538: 525 0000FF3A 11 e1 brb _divf_4_lp1 ! 539: 526 0000FF3C L289: ! 540: 527 0000FF3C # /* ! 541: 528 0000FF3C # * end error loop - test the results ! 542: 529 0000FF3C # */ ! 543: 530 0000FF3C # if( sgl_st_acc != sgl_expected ) { /* COMPARE the values */ ! 544: 531 0000FF3C 1d effffffba6 effffffba1 cmpl _sgl_st_acc,_sgl_expected ! 545: 532 0000FF47 21 03 13 0086 jeql L290 ! 546: 533 0000FF4C # errcnt++; /* bump the error count */ ! 547: 534 0000FF4C 6d effffffb96 incl _errcnt ! 548: 535 0000FF52 # if( prt_error ) { ! 549: 536 0000FF52 5d effffffb90 tstl _prt_error ! 550: 537 0000FF58 31 55 jeql L291 ! 551: 538 0000FF5A # writes(" \n"); /* start a new print line */ ! 552: 539 0000FF5A .data 1 ! 553: 540 00000dfc * L292: ! 554: 541 00000dfc * 200A00 .ascii " \12\0" ! 555: 542 00000dff * .text ! 556: 543 0000FF5A dd 8f00000dfc pushl $L292 ! 557: 544 0000FF60 fe 08 effffffb81 callf $8,_writes ! 558: 545 0000FF67 # writes("cycle: "); ! 559: 546 0000FF67 .data 1 ! 560: 547 00000dff * L293: ! 561: 548 00000dff * 6379636C653A2000 .ascii "cycle: \0" ! 562: 549 00000e07 * .text ! 563: 550 0000FF67 dd 8f00000dff pushl $L293 ! 564: 551 0000FF6D fe 08 effffffb74 callf $8,_writes ! 565: 552 0000FF74 # writed( cycle ); ! 566: 553 0000FF74 dd effffffb6e pushl _cycle ! 567: 554 0000FF7A fe 08 effffffb67 callf $8,_writed ! 568: 555 0000FF81 # writes(" DIVF test "); ! 569: 556 0000FF81 .data 1 ! 570: 557 00000e07 * L294: ! 571: 558 00000e07 * 2020444956462074657374200 .ascii " DIVF test \0" ! 572: 0 ! 573: 559 00000e14 * .text ! 574: 560 0000FF81 dd 8f00000e07 pushl $L294 ! 575: 561 0000FF87 fe 08 effffffb5a callf $8,_writes ! 576: 562 0000FF8E # writed( test_no ); ! 577: 563 0000FF8E dd effffffb54 pushl _test_no ! 578: 564 0000FF94 fe 08 effffffb4d callf $8,_writed ! 579: 565 0000FF9B # writes(", subtest 4 (Cache Data - 2 NOPs) - BAD FINAL ACC\n"); ! 580: 566 0000FF9B .data 1 ! 581: 567 00000e14 * L295: ! 582: 568 00000e14 * 2C20737562746573742034202 .ascii ", subtest 4 (Cache Data - 2 NOPs) - BAD FINAL ACC\12\0" ! 583: 843616368652044617461202D ! 584: 2032204E4F507329202D20424 ! 585: 1442046494E414C204143430A ! 586: 00 ! 587: 569 00000e47 * .text ! 588: 570 0000FF9B dd 8f00000e14 pushl $L295 ! 589: 571 0000FFA1 fe 08 effffffb40 callf $8,_writes ! 590: 572 0000FFA8 # print_divf_data(); ! 591: 573 0000FFA8 fe 04 ef00000709 callf $4,_print_divf_data ! 592: 574 0000FFAF # } ! 593: 575 0000FFAF # if( halt_flg ) ! 594: 576 0000FFAF L291: ! 595: 577 0000FFAF 5d effffffb33 tstl _halt_flg ! 596: 578 0000FFB5 31 09 jeql L296 ! 597: 579 0000FFB7 # divf_er_halt( BAD_ACC_HLT ); /* halt on the error */ ! 598: 580 0000FFB7 dd 01 pushl $1 ! 599: 581 0000FFB9 fe 08 ef00000796 callf $8,_divf_er_halt ! 600: 582 0000FFC0 # if( loop_on_err ) { ! 601: 583 0000FFC0 L296: ! 602: 584 0000FFC0 5d effffffb22 tstl _loop_on_err ! 603: 585 0000FFC6 31 0a jeql L297 ! 604: 586 0000FFC8 # force_loop = TRUE; /* set the force loop flag */ ! 605: 587 0000FFC8 0d 01 effffffb19 movl $1,_force_loop ! 606: 588 0000FFCF # asm("brw _divf_4_lp1");; /* and loop on the error */ ! 607: 589 0000FFCF 13 ff4b brw _divf_4_lp1 ! 608: 590 0000FFD2 # } /* end of loop on error */ ! 609: 591 0000FFD2 # } /* end of compare error */ ! 610: 592 0000FFD2 L297: ! 611: 593 0000FFD2 # } /* end of WHILE loop */ ! 612: 594 0000FFD2 L290: ! 613: 595 0000FFD2 L286: ! 614: 596 0000FFD2 6d effffffb10 incl _index ! 615: 597 0000FFD8 13 fef9 jbr L288 ! 616: 598 0000FFDB L287: ! 617: 599 0000FFDB # } /* end of subtest 4 */ ! 618: 600 0000FFDB 40 ret#2 ! 619: 601 0000FFDC .set L282,0x0 ! 620: 602 0000FFDC L284: ! 621: 603 0000FFDC 13 fee2 jbr L285 ! 622: 604 0000FFDF .data ! 623: 605 00000d28 * .text ! 624: 606 0000FFDF 00 .align 1 ! 625: 607 0000FFE0 .globl _divf_5 ! 626: 608 0000FFE0 _divf_5: ! 627: 609 0000FFE0 0000 .word L298 ! 628: 610 0000FFE2 # ! 629: 611 0000FFE2 # ! 630: 612 0000FFE2 # ! 631: 613 0000FFE2 # /************************************************************************ ! 632: 614 0000FFE2 # * ! 633: 615 0000FFE2 # * SUBTEST 5 - DIvide, Wait 1 NOP before storing the results ! 634: 616 0000FFE2 # * ! 635: 617 0000FFE2 # ************************************************************************/ ! 636: 618 0000FFE2 # divf_5() ! 637: 619 0000FFE2 # { ! 638: 620 0000FFE2 13 011a jbr L300 ! 639: 621 0000FFE5 L301: ! 640: 622 0000FFE5 # force_loop = FALSE; ! 641: 623 0000FFE5 4d effffffafd clrl _force_loop ! 642: 624 0000FFEB # subtest = 5; ! 643: 625 0000FFEB 0d 05 effffffaf6 movl $5,_subtest ! 644: 626 0000FFF2 # for( index = 0; index < max_divf_1_index; index++ ) { ! 645: 627 0000FFF2 4d effffffaf0 clrl _index ! 646: 628 0000FFF8 L304: ! 647: 629 0000FFF8 1d effffffaea effffffae5 cmpl _index,_max_divf_1_index ! 648: 630 00010003 91 03 13 00f6 jgeq L303 ! 649: 631 00010008 # sgl_ld_acc = divf_1_data[index].op_1; /* get operand 1 */ ! 650: 632 00010008 5c 0c effffffad9 50 mull3 $12,_index,r0 ! 651: 633 00010010 0d e000000000 effffffacd movl _divf_1_data(r0),_sgl_ld_acc ! 652: 634 0001001B # sgl_value_1 = divf_1_data[index].op_2; /* get operand 2 */ ! 653: 635 0001001B 5c 0c effffffac6 50 mull3 $12,_index,r0 ! 654: 636 00010023 0d e000000004 effffffaba movl _divf_1_data+4(r0),_sgl_value_1 ! 655: 637 0001002E # sgl_expected = divf_1_data[index].exp; /* get expected result */ ! 656: 638 0001002E 5c 0c effffffab3 50 mull3 $12,_index,r0 ! 657: 639 00010036 0d e000000008 effffffaa7 movl _divf_1_data+8(r0),_sgl_expected ! 658: 640 00010041 # /* ! 659: 641 00010041 # * If LOOP ON ERROR is set, this is the loop for this subtest. ! 660: 642 00010041 # * The force loop flag is set after the first error. ! 661: 643 00010041 # */ ! 662: 644 00010041 # asm("_divf_5_lp1:"); ! 663: 645 00010041 _divf_5_lp1: ! 664: 646 00010041 # asm("ldf _sgl_ld_acc"); /* load the 1st operand */ ! 665: 647 00010041 06 effffffaa1 ldf _sgl_ld_acc ! 666: 648 00010047 # asm("nop"); /* delay */ ! 667: 649 00010047 10 nop ! 668: 650 00010048 # asm("divf _sgl_value_1"); /* divide the 2nd operand */ ! 669: 651 00010048 f6 effffffa9a divf _sgl_value_1 ! 670: 652 0001004E # asm("nop"); /* delay before storing */ ! 671: 653 0001004E 10 nop ! 672: 654 0001004F # asm("stf _sgl_st_acc"); /* store the result */ ! 673: 655 0001004F 26 effffffa93 stf _sgl_st_acc ! 674: 656 00010055 # if( force_loop ) ! 675: 657 00010055 5d effffffa8d tstl _force_loop ! 676: 658 0001005B 31 02 jeql L305 ! 677: 659 0001005D # asm("brb _divf_5_lp1");; /* loop on the error */ ! 678: 660 0001005D 11 e2 brb _divf_5_lp1 ! 679: 661 0001005F L305: ! 680: 662 0001005F # /* ! 681: 663 0001005F # * end error loop - test the results ! 682: 664 0001005F # */ ! 683: 665 0001005F # if( sgl_st_acc != sgl_expected ) { /* COMPARE the values */ ! 684: 666 0001005F 1d effffffa83 effffffa7e cmpl _sgl_st_acc,_sgl_expected ! 685: 667 0001006A 21 03 13 0086 jeql L306 ! 686: 668 0001006F # errcnt++; /* bump the error count */ ! 687: 669 0001006F 6d effffffa73 incl _errcnt ! 688: 670 00010075 # if( prt_error ) { ! 689: 671 00010075 5d effffffa6d tstl _prt_error ! 690: 672 0001007B 31 55 jeql L307 ! 691: 673 0001007D # writes(" \n"); /* start a new print line */ ! 692: 674 0001007D .data 1 ! 693: 675 00000e47 * L308: ! 694: 676 00000e47 * 200A00 .ascii " \12\0" ! 695: 677 00000e4a * .text ! 696: 678 0001007D dd 8f00000e47 pushl $L308 ! 697: 679 00010083 fe 08 effffffa5e callf $8,_writes ! 698: 680 0001008A # writes("cycle: "); ! 699: 681 0001008A .data 1 ! 700: 682 00000e4a * L309: ! 701: 683 00000e4a * 6379636C653A2000 .ascii "cycle: \0" ! 702: 684 00000e52 * .text ! 703: 685 0001008A dd 8f00000e4a pushl $L309 ! 704: 686 00010090 fe 08 effffffa51 callf $8,_writes ! 705: 687 00010097 # writed( cycle ); ! 706: 688 00010097 dd effffffa4b pushl _cycle ! 707: 689 0001009D fe 08 effffffa44 callf $8,_writed ! 708: 690 000100A4 # writes(" DIVF test "); ! 709: 691 000100A4 .data 1 ! 710: 692 00000e52 * L310: ! 711: 693 00000e52 * 2020444956462074657374200 .ascii " DIVF test \0" ! 712: 0 ! 713: 694 00000e5f * .text ! 714: 695 000100A4 dd 8f00000e52 pushl $L310 ! 715: 696 000100AA fe 08 effffffa37 callf $8,_writes ! 716: 697 000100B1 # writed( test_no ); ! 717: 698 000100B1 dd effffffa31 pushl _test_no ! 718: 699 000100B7 fe 08 effffffa2a callf $8,_writed ! 719: 700 000100BE # writes(", subtest 5 (Cache Data - 1 NOP) - BAD FINAL ACC\n"); ! 720: 701 000100BE .data 1 ! 721: 702 00000e5f * L311: ! 722: 703 00000e5f * 2C20737562746573742035202 .ascii ", subtest 5 (Cache Data - 1 NOP) - BAD FINAL ACC\12\0" ! 723: 843616368652044617461202D ! 724: 2031204E4F5029202D2042414 ! 725: 42046494E414C204143430A00 ! 726: 704 00000e91 * .text ! 727: 705 000100BE dd 8f00000e5f pushl $L311 ! 728: 706 000100C4 fe 08 effffffa1d callf $8,_writes ! 729: 707 000100CB # print_divf_data(); ! 730: 708 000100CB fe 04 ef000005e6 callf $4,_print_divf_data ! 731: 709 000100D2 # } ! 732: 710 000100D2 # if( halt_flg ) ! 733: 711 000100D2 L307: ! 734: 712 000100D2 5d effffffa10 tstl _halt_flg ! 735: 713 000100D8 31 09 jeql L312 ! 736: 714 000100DA # divf_er_halt( BAD_ACC_HLT ); /* halt on the error */ ! 737: 715 000100DA dd 01 pushl $1 ! 738: 716 000100DC fe 08 ef00000673 callf $8,_divf_er_halt ! 739: 717 000100E3 # if( loop_on_err ) { ! 740: 718 000100E3 L312: ! 741: 719 000100E3 5d effffff9ff tstl _loop_on_err ! 742: 720 000100E9 31 0a jeql L313 ! 743: 721 000100EB # force_loop = TRUE; /* set the force loop flag */ ! 744: 722 000100EB 0d 01 effffff9f6 movl $1,_force_loop ! 745: 723 000100F2 # asm("brw _divf_5_lp1");; /* and loop on the error */ ! 746: 724 000100F2 13 ff4c brw _divf_5_lp1 ! 747: 725 000100F5 # } /* end of loop on error */ ! 748: 726 000100F5 # } /* end of compare error */ ! 749: 727 000100F5 L313: ! 750: 728 000100F5 # } /* end of WHILE loop */ ! 751: 729 000100F5 L306: ! 752: 730 000100F5 L302: ! 753: 731 000100F5 6d effffff9ed incl _index ! 754: 732 000100FB 13 fefa jbr L304 ! 755: 733 000100FE L303: ! 756: 734 000100FE # } /* end of subtest 5 */ ! 757: 735 000100FE 40 ret#2 ! 758: 736 000100FF .set L298,0x0 ! 759: 737 000100FF L300: ! 760: 738 000100FF 13 fee3 jbr L301 ! 761: 739 00010102 .data ! 762: 740 00000d28 * .text ! 763: 741 00010102 .align 1 ! 764: 742 00010102 .globl _divf_6 ! 765: 743 00010102 _divf_6: ! 766: 744 00010102 0000 .word L314 ! 767: 745 00010104 # ! 768: 746 00010104 # ! 769: 747 00010104 # ! 770: 748 00010104 # /************************************************************************ ! 771: 749 00010104 # * ! 772: 750 00010104 # * SUBTEST 6 - Check for register corruption ! 773: 751 00010104 # * ! 774: 752 00010104 # ************************************************************************/ ! 775: 753 00010104 # divf_6() ! 776: 754 00010104 # { ! 777: 755 00010104 13 01a7 jbr L316 ! 778: 756 00010107 L317: ! 779: 757 00010107 # force_loop = FALSE; /* clear force_loop flg */ ! 780: 758 00010107 4d effffff9db clrl _force_loop ! 781: 759 0001010D # subtest = 6; ! 782: 760 0001010D 0d 06 effffff9d4 movl $6,_subtest ! 783: 761 00010114 # fill_reg_buf( load_regs ); /* get patterns for regs */ ! 784: 762 00010114 dd 8f00000000 pushl $_load_regs ! 785: 763 0001011A fe 08 effffff9c7 callf $8,_fill_reg_buf ! 786: 764 00010121 # index = 0; ! 787: 765 00010121 4d effffff9c1 clrl _index ! 788: 766 00010127 # sgl_ld_acc = divf_1_data[0].op_1; /* get operand 1 */ ! 789: 767 00010127 0d effffff9bb effffff9b6 movl _divf_1_data,_sgl_ld_acc ! 790: 768 00010132 # sgl_value_1 = divf_1_data[0].op_2; /* get operand 2 */ ! 791: 769 00010132 0d effffff9b4 effffff9ab movl _divf_1_data+4,_sgl_value_1 ! 792: 770 0001013D # sgl_expected = divf_1_data[0].exp; /* get expected result */ ! 793: 771 0001013D 0d effffff9ad effffff9a0 movl _divf_1_data+8,_sgl_expected ! 794: 772 00010148 # /* ! 795: 773 00010148 # * If LOOP ON ERROR is set, this is the loop for this subtest. ! 796: 774 00010148 # * The force loop flag is set after the first error. ! 797: 775 00010148 # */ ! 798: 776 00010148 # asm("_divf_6_lp1:"); ! 799: 777 00010148 _divf_6_lp1: ! 800: 778 00010148 # asm("ldf _sgl_ld_acc"); /* LOAD the accumulator */ ! 801: 779 00010148 06 effffff99a ldf _sgl_ld_acc ! 802: 780 0001014E # asm("nop"); ! 803: 781 0001014E 10 nop ! 804: 782 0001014F # asm("loadr $0x1fff,_load_regs"); /* load regs 0 - 12 */ ! 805: 783 0001014F ab 891fff effffff990 loadr $0x1fff,_load_regs ! 806: 784 00010158 # asm("nop"); ! 807: 785 00010158 10 nop ! 808: 786 00010159 # asm("divf _sgl_value_1"); /* do the divide */ ! 809: 787 00010159 f6 effffff989 divf _sgl_value_1 ! 810: 788 0001015F # asm("nop"); ! 811: 789 0001015F 10 nop ! 812: 790 00010160 # asm("storer $0x1fff,_store_regs"); /* store regs 0 - 12 */ ! 813: 791 00010160 bb 891fff effffff97f storer $0x1fff,_store_regs ! 814: 792 00010169 # asm("stf _sgl_st_acc"); /* save the accumulator */ ! 815: 793 00010169 26 effffff979 stf _sgl_st_acc ! 816: 794 0001016F # if( force_loop ) ! 817: 795 0001016F 5d effffff973 tstl _force_loop ! 818: 796 00010175 31 02 jeql L319 ! 819: 797 00010177 # asm("brb _divf_6_lp1");; /* loop on the error */ ! 820: 798 00010177 11 cf brb _divf_6_lp1 ! 821: 799 00010179 L319: ! 822: 800 00010179 # /* ! 823: 801 00010179 # * Now compare the stored register values to those that were loaded ! 824: 802 00010179 # */ ! 825: 803 00010179 # index2 = 0; ! 826: 804 00010179 4d effffff969 clrl _index2 ! 827: 805 0001017F # while( (load_regs[index2] == store_regs[index2]) && (index2 < 13) ) ! 828: 806 0001017F L320: ! 829: 807 0001017F 0d effffff963 50 movl _index2,r0 ! 830: 808 00010186 0d effffff95c 51 movl _index2,r1 ! 831: 809 0001018D 1d 40effffff954 cmpl _load_regs[r0],_store_regs[r1] ! 832: 41effffff94e ! 833: 810 0001019A 21 11 jneq L321 ! 834: 811 0001019C 1d effffff946 0d cmpl _index2,$13 ! 835: 812 000101A3 81 08 jgeq L321 ! 836: 813 000101A5 # index2++; /* check reg values */ ! 837: 814 000101A5 6d effffff93d incl _index2 ! 838: 815 000101AB 11 d2 jbr L320 ! 839: 816 000101AD L321: ! 840: 817 000101AD # if( index2 < 13 ) { /* error if index2 < 13 */ ! 841: 818 000101AD 1d effffff935 0d cmpl _index2,$13 ! 842: 819 000101B4 91 03 13 00f4 jgeq L322 ! 843: 820 000101B9 # errcnt++; /* bump the error count */ ! 844: 821 000101B9 6d effffff929 incl _errcnt ! 845: 822 000101BF # if( prt_error ) { ! 846: 823 000101BF 5d effffff923 tstl _prt_error ! 847: 824 000101C5 21 03 13 00c0 jeql L323 ! 848: 825 000101CA # writes(" \n"); /* start a new print line */ ! 849: 826 000101CA .data 1 ! 850: 827 00000e91 * L324: ! 851: 828 00000e91 * 200A00 .ascii " \12\0" ! 852: 829 00000e94 * .text ! 853: 830 000101CA dd 8f00000e91 pushl $L324 ! 854: 831 000101D0 fe 08 effffff911 callf $8,_writes ! 855: 832 000101D7 # writes("cycle: "); ! 856: 833 000101D7 .data 1 ! 857: 834 00000e94 * L325: ! 858: 835 00000e94 * 6379636C653A2000 .ascii "cycle: \0" ! 859: 836 00000e9c * .text ! 860: 837 000101D7 dd 8f00000e94 pushl $L325 ! 861: 838 000101DD fe 08 effffff904 callf $8,_writes ! 862: 839 000101E4 # writed( cycle ); ! 863: 840 000101E4 dd effffff8fe pushl _cycle ! 864: 841 000101EA fe 08 effffff8f7 callf $8,_writed ! 865: 842 000101F1 # writes(" DIVF test "); ! 866: 843 000101F1 .data 1 ! 867: 844 00000e9c * L326: ! 868: 845 00000e9c * 2020444956462074657374200 .ascii " DIVF test \0" ! 869: 0 ! 870: 846 00000ea9 * .text ! 871: 847 000101F1 dd 8f00000e9c pushl $L326 ! 872: 848 000101F7 fe 08 effffff8ea callf $8,_writes ! 873: 849 000101FE # writed( test_no ); ! 874: 850 000101FE dd effffff8e4 pushl _test_no ! 875: 851 00010204 fe 08 effffff8dd callf $8,_writed ! 876: 852 0001020B # writes(", subtest 6 - A REGISTER WAS CHANGED\n"); ! 877: 853 0001020B .data 1 ! 878: 854 00000ea9 * L327: ! 879: 855 00000ea9 * 2C20737562746573742036202 .ascii ", subtest 6 - A REGISTER WAS CHANGED\12\0" ! 880: D204120524547495354455220 ! 881: 574153204348414E4745440A0 ! 882: 0 ! 883: 856 00000ecf * .text ! 884: 857 0001020B dd 8f00000ea9 pushl $L327 ! 885: 858 00010211 fe 08 effffff8d0 callf $8,_writes ! 886: 859 00010218 # print_divf_data(); /* print the operands */ ! 887: 860 00010218 fe 04 ef00000499 callf $4,_print_divf_data ! 888: 861 0001021F # writes("register "); /* print the information */ ! 889: 862 0001021F .data 1 ! 890: 863 00000ecf * L328: ! 891: 864 00000ecf * 72656769737465722000 .ascii "register \0" ! 892: 865 00000ed9 * .text ! 893: 866 0001021F dd 8f00000ecf pushl $L328 ! 894: 867 00010225 fe 08 effffff8bc callf $8,_writes ! 895: 868 0001022C # writed( index2 ); /* about the corrupted */ ! 896: 869 0001022C dd effffff8b6 pushl _index2 ! 897: 870 00010232 fe 08 effffff8af callf $8,_writed ! 898: 871 00010239 # writes(" = "); /* register */ ! 899: 872 00010239 .data 1 ! 900: 873 00000ed9 * L329: ! 901: 874 00000ed9 * 203D2000 .ascii " = \0" ! 902: 875 00000edd * .text ! 903: 876 00010239 dd 8f00000ed9 pushl $L329 ! 904: 877 0001023F fe 08 effffff8a2 callf $8,_writes ! 905: 878 00010246 # write32h( store_regs[index2] ); ! 906: 879 00010246 0d effffff89c 50 movl _index2,r0 ! 907: 880 0001024D dd 40effffff894 pushl _store_regs[r0] ! 908: 881 00010254 fe 08 effffff88d callf $8,_write32h ! 909: 882 0001025B # writes(", should be = "); ! 910: 883 0001025B .data 1 ! 911: 884 00000edd * L331: ! 912: 885 00000edd * 2C202073686F756C642062652 .ascii ", should be = \0" ! 913: 03D2000 ! 914: 886 00000eed * .text ! 915: 887 0001025B dd 8f00000edd pushl $L331 ! 916: 888 00010261 fe 08 effffff880 callf $8,_writes ! 917: 889 00010268 # write32h( load_regs[index2] ); ! 918: 890 00010268 0d effffff87a 50 movl _index2,r0 ! 919: 891 0001026F dd 40effffff872 pushl _load_regs[r0] ! 920: 892 00010276 fe 08 effffff86b callf $8,_write32h ! 921: 893 0001027D # writes("\n"); ! 922: 894 0001027D .data 1 ! 923: 895 00000eed * L332: ! 924: 896 00000eed * 0A00 .ascii "\12\0" ! 925: 897 00000eef * .text ! 926: 898 0001027D dd 8f00000eed pushl $L332 ! 927: 899 00010283 fe 08 effffff85e callf $8,_writes ! 928: 900 0001028A # } ! 929: 901 0001028A # if( halt_flg ) ! 930: 902 0001028A L323: ! 931: 903 0001028A 5d effffff858 tstl _halt_flg ! 932: 904 00010290 31 09 jeql L333 ! 933: 905 00010292 # divf_er_halt( BAD_REG_HLT ); /* halt on the error */ ! 934: 906 00010292 dd 02 pushl $2 ! 935: 907 00010294 fe 08 ef000004bb callf $8,_divf_er_halt ! 936: 908 0001029B # if( loop_on_err ) { ! 937: 909 0001029B L333: ! 938: 910 0001029B 5d effffff847 tstl _loop_on_err ! 939: 911 000102A1 31 0a jeql L334 ! 940: 912 000102A3 # force_loop = TRUE; /* set the force loop flag */ ! 941: 913 000102A3 0d 01 effffff83e movl $1,_force_loop ! 942: 914 000102AA # asm("brw _divf_6_lp1");; /* and loop on the error */ ! 943: 915 000102AA 13 fe9b brw _divf_6_lp1 ! 944: 916 000102AD # } /* end of loop on error */ ! 945: 917 000102AD # } /* end of register corruption error */ ! 946: 918 000102AD L334: ! 947: 919 000102AD # } /* end of subtest 6 */ ! 948: 920 000102AD L322: ! 949: 921 000102AD 40 ret#2 ! 950: 922 000102AE .set L314,0x0 ! 951: 923 000102AE L316: ! 952: 924 000102AE 13 fe56 jbr L317 ! 953: 925 000102B1 .data ! 954: 926 00000d28 * .text ! 955: 927 000102B1 00 .align 1 ! 956: 928 000102B2 .globl _divf_7 ! 957: 929 000102B2 _divf_7: ! 958: 930 000102B2 0000 .word L335 ! 959: 931 000102B4 # ! 960: 932 000102B4 # ! 961: 933 000102B4 # ! 962: 934 000102B4 # /************************************************************************ ! 963: 935 000102B4 # * ! 964: 936 000102B4 # * SUBTEST 7 - Check for PSL corruption ! 965: 937 000102B4 # * ! 966: 938 000102B4 # ************************************************************************/ ! 967: 939 000102B4 # divf_7() ! 968: 940 000102B4 # { ! 969: 941 000102B4 13 01b2 jbr L337 ! 970: 942 000102B7 L338: ! 971: 943 000102B7 # force_loop = FALSE; /* clear force_loop flg */ ! 972: 944 000102B7 4d effffff82b clrl _force_loop ! 973: 945 000102BD # subtest = 7; ! 974: 946 000102BD 0d 07 effffff824 movl $7,_subtest ! 975: 947 000102C4 # fill_reg_buf( load_regs ); /* get patterns for regs */ ! 976: 948 000102C4 dd 8f00000000 pushl $_load_regs ! 977: 949 000102CA fe 08 effffff817 callf $8,_fill_reg_buf ! 978: 950 000102D1 # for( index = 0; index < 3; index++ ) { ! 979: 951 000102D1 4d effffff811 clrl _index ! 980: 952 000102D7 L341: ! 981: 953 000102D7 1d effffff80b 03 cmpl _index,$3 ! 982: 954 000102DE 91 03 13 0185 jgeq L340 ! 983: 955 000102E3 # sgl_ld_acc = divf_1_data[index].op_1; /* get operand 1 */ ! 984: 956 000102E3 5c 0c effffff7fe 50 mull3 $12,_index,r0 ! 985: 957 000102EB 0d e000000000 effffff7f2 movl _divf_1_data(r0),_sgl_ld_acc ! 986: 958 000102F6 # sgl_value_1 = divf_1_data[index].op_2; /* get operand 2 */ ! 987: 959 000102F6 5c 0c effffff7eb 50 mull3 $12,_index,r0 ! 988: 960 000102FE 0d e000000004 effffff7df movl _divf_1_data+4(r0),_sgl_value_1 ! 989: 961 00010309 # sgl_expected = divf_1_data[index].exp; /* get expected */ ! 990: 962 00010309 5c 0c effffff7d8 50 mull3 $12,_index,r0 ! 991: 963 00010311 0d e000000008 effffff7cc movl _divf_1_data+8(r0),_sgl_expected ! 992: 964 0001031C # sgl_dummy1 = status_array[status_index]; /* status = +, -, 0 */ ! 993: 965 0001031C 0d effffff7c6 50 movl _status_index,r0 ! 994: 966 00010323 0d 40effffff7be movl _status_array[r0],_sgl_dummy1 ! 995: effffff7b9 ! 996: 967 0001032F # /* ! 997: 968 0001032F # * If LOOP ON ERROR is set, this is the loop for this subtest. ! 998: 969 0001032F # * The force loop flag is set after the first error. ! 999: 970 0001032F # */ ! 1000: 971 0001032F # asm("_divf_7_lp1:"); ! 1001: 972 0001032F _divf_7_lp1: ! 1002: 973 0001032F # asm("ldf _sgl_ld_acc"); /* LOAD the accumulator */ ! 1003: 974 0001032F 06 effffff7b3 ldf _sgl_ld_acc ! 1004: 975 00010335 # asm("nop"); ! 1005: 976 00010335 10 nop ! 1006: 977 00010336 # asm("tstl _sgl_dummy1"); /* set the PSL status */ ! 1007: 978 00010336 5d effffff7ac tstl _sgl_dummy1 ! 1008: 979 0001033C # asm("movpsl _init_psl"); /* save the initial PSL */ ! 1009: 980 0001033C cd effffff7a6 movpsl _init_psl ! 1010: 981 00010342 # asm("nop"); ! 1011: 982 00010342 10 nop ! 1012: 983 00010343 # asm("divf _sgl_value_1"); /* do the divide */ ! 1013: 984 00010343 f6 effffff79f divf _sgl_value_1 ! 1014: 985 00010349 # asm("nop"); ! 1015: 986 00010349 10 nop ! 1016: 987 0001034A # asm("movpsl _psl_val"); /* save the final PSL */ ! 1017: 988 0001034A cd effffff798 movpsl _psl_val ! 1018: 989 00010350 # asm("stf _sgl_st_acc"); /* save the accumulator */ ! 1019: 990 00010350 26 effffff792 stf _sgl_st_acc ! 1020: 991 00010356 # if( force_loop ) ! 1021: 992 00010356 5d effffff78c tstl _force_loop ! 1022: 993 0001035C 31 02 jeql L342 ! 1023: 994 0001035E # asm("brb _divf_7_lp1");; /* loop on the error */ ! 1024: 995 0001035E 11 cf brb _divf_7_lp1 ! 1025: 996 00010360 L342: ! 1026: 997 00010360 # /* ! 1027: 998 00010360 # * Now compare the final PSL to the initial PSL -they should be the same ! 1028: 999 00010360 # */ ! 1029: 1000 00010360 # exp_psl = init_psl; ! 1030: 1001 00010360 0d effffff782 effffff77d movl _init_psl,_exp_psl ! 1031: 1002 0001036B # if( psl_val != exp_psl ) { ! 1032: 1003 0001036B 1d effffff777 effffff772 cmpl _psl_val,_exp_psl ! 1033: 1004 00010376 21 03 13 00e4 jeql L343 ! 1034: 1005 0001037B # errcnt++; /* bump the error count */ ! 1035: 1006 0001037B 6d effffff767 incl _errcnt ! 1036: 1007 00010381 # if( prt_error ) { ! 1037: 1008 00010381 5d effffff761 tstl _prt_error ! 1038: 1009 00010387 21 03 13 00b0 jeql L344 ! 1039: 1010 0001038C # writes(" \n"); /* start a new print line */ ! 1040: 1011 0001038C .data 1 ! 1041: 1012 00000eef * L345: ! 1042: 1013 00000eef * 200A00 .ascii " \12\0" ! 1043: 1014 00000ef2 * .text ! 1044: 1015 0001038C dd 8f00000eef pushl $L345 ! 1045: 1016 00010392 fe 08 effffff74f callf $8,_writes ! 1046: 1017 00010399 # writes("cycle: "); ! 1047: 1018 00010399 .data 1 ! 1048: 1019 00000ef2 * L346: ! 1049: 1020 00000ef2 * 6379636C653A2000 .ascii "cycle: \0" ! 1050: 1021 00000efa * .text ! 1051: 1022 00010399 dd 8f00000ef2 pushl $L346 ! 1052: 1023 0001039F fe 08 effffff742 callf $8,_writes ! 1053: 1024 000103A6 # writed( cycle ); ! 1054: 1025 000103A6 dd effffff73c pushl _cycle ! 1055: 1026 000103AC fe 08 effffff735 callf $8,_writed ! 1056: 1027 000103B3 # writes(" DIVF test "); ! 1057: 1028 000103B3 .data 1 ! 1058: 1029 00000efa * L347: ! 1059: 1030 00000efa * 2020444956462074657374200 .ascii " DIVF test \0" ! 1060: 0 ! 1061: 1031 00000f07 * .text ! 1062: 1032 000103B3 dd 8f00000efa pushl $L347 ! 1063: 1033 000103B9 fe 08 effffff728 callf $8,_writes ! 1064: 1034 000103C0 # writed( test_no ); ! 1065: 1035 000103C0 dd effffff722 pushl _test_no ! 1066: 1036 000103C6 fe 08 effffff71b callf $8,_writed ! 1067: 1037 000103CD # writes(", subtest 7 - INCORRECT FINAL PSL\n"); ! 1068: 1038 000103CD .data 1 ! 1069: 1039 00000f07 * L348: ! 1070: 1040 00000f07 * 2C20737562746573742037202 .ascii ", subtest 7 - INCORRECT FINAL PSL\12\0" ! 1071: D20494E434F52524543542046 ! 1072: 494E414C2050534C0A00 ! 1073: 1041 00000f2a * .text ! 1074: 1042 000103CD dd 8f00000f07 pushl $L348 ! 1075: 1043 000103D3 fe 08 effffff70e callf $8,_writes ! 1076: 1044 000103DA # print_divf_data(); /* print the operands */ ! 1077: 1045 000103DA fe 04 ef000002d7 callf $4,_print_divf_data ! 1078: 1046 000103E1 # writes("initial PSL = "); ! 1079: 1047 000103E1 .data 1 ! 1080: 1048 00000f2a * L349: ! 1081: 1049 00000f2a * 696E697469616C2050534C203 .ascii "initial PSL = \0" ! 1082: D2000 ! 1083: 1050 00000f39 * .text ! 1084: 1051 000103E1 dd 8f00000f2a pushl $L349 ! 1085: 1052 000103E7 fe 08 effffff6fa callf $8,_writes ! 1086: 1053 000103EE # write32h( init_psl ); ! 1087: 1054 000103EE dd effffff6f4 pushl _init_psl ! 1088: 1055 000103F4 fe 08 effffff6ed callf $8,_write32h ! 1089: 1056 000103FB # writes(", final PSL = "); ! 1090: 1057 000103FB .data 1 ! 1091: 1058 00000f39 * L350: ! 1092: 1059 00000f39 * 2C2066696E616C2050534C203 .ascii ", final PSL = \0" ! 1093: D2000 ! 1094: 1060 00000f48 * .text ! 1095: 1061 000103FB dd 8f00000f39 pushl $L350 ! 1096: 1062 00010401 fe 08 effffff6e0 callf $8,_writes ! 1097: 1063 00010408 # write32h( psl_val ); ! 1098: 1064 00010408 dd effffff6da pushl _psl_val ! 1099: 1065 0001040E fe 08 effffff6d3 callf $8,_write32h ! 1100: 1066 00010415 # writes(", expected PSL = "); ! 1101: 1067 00010415 .data 1 ! 1102: 1068 00000f48 * L351: ! 1103: 1069 00000f48 * 2C20657870656374656420505 .ascii ", expected PSL = \0" ! 1104: 34C203D2000 ! 1105: 1070 00000f5a * .text ! 1106: 1071 00010415 dd 8f00000f48 pushl $L351 ! 1107: 1072 0001041B fe 08 effffff6c6 callf $8,_writes ! 1108: 1073 00010422 # write32h( exp_psl ); ! 1109: 1074 00010422 dd effffff6c0 pushl _exp_psl ! 1110: 1075 00010428 fe 08 effffff6b9 callf $8,_write32h ! 1111: 1076 0001042F # writes("\n"); ! 1112: 1077 0001042F .data 1 ! 1113: 1078 00000f5a * L352: ! 1114: 1079 00000f5a * 0A00 .ascii "\12\0" ! 1115: 1080 00000f5c * .text ! 1116: 1081 0001042F dd 8f00000f5a pushl $L352 ! 1117: 1082 00010435 fe 08 effffff6ac callf $8,_writes ! 1118: 1083 0001043C # } ! 1119: 1084 0001043C # if( halt_flg ) ! 1120: 1085 0001043C L344: ! 1121: 1086 0001043C 5d effffff6a6 tstl _halt_flg ! 1122: 1087 00010442 31 09 jeql L353 ! 1123: 1088 00010444 # divf_er_halt( BAD_PSL_HLT ); /* halt on the error */ ! 1124: 1089 00010444 dd 03 pushl $3 ! 1125: 1090 00010446 fe 08 ef00000309 callf $8,_divf_er_halt ! 1126: 1091 0001044D # if( loop_on_err ) { ! 1127: 1092 0001044D L353: ! 1128: 1093 0001044D 5d effffff695 tstl _loop_on_err ! 1129: 1094 00010453 31 0a jeql L354 ! 1130: 1095 00010455 # force_loop = TRUE; /* set the force loop flag */ ! 1131: 1096 00010455 0d 01 effffff68c movl $1,_force_loop ! 1132: 1097 0001045C # asm("brw _divf_7_lp1");; /* and loop on the error */ ! 1133: 1098 0001045C 13 fed0 brw _divf_7_lp1 ! 1134: 1099 0001045F # } /* end of loop on error */ ! 1135: 1100 0001045F # } /* end of PSL corruption error */ ! 1136: 1101 0001045F L354: ! 1137: 1102 0001045F # } /* end of WHILE loop */ ! 1138: 1103 0001045F L343: ! 1139: 1104 0001045F L339: ! 1140: 1105 0001045F 6d effffff683 incl _index ! 1141: 1106 00010465 13 fe6f jbr L341 ! 1142: 1107 00010468 L340: ! 1143: 1108 00010468 # } /* end of subtest 7 */ ! 1144: 1109 00010468 40 ret#2 ! 1145: 1110 00010469 .set L335,0x0 ! 1146: 1111 00010469 L337: ! 1147: 1112 00010469 13 fe4b jbr L338 ! 1148: 1113 0001046C .data ! 1149: 1114 00000d28 * .text ! 1150: 1115 0001046C .align 1 ! 1151: 1116 0001046C .globl _divf_8 ! 1152: 1117 0001046C _divf_8: ! 1153: 1118 0001046C 0000 .word L355 ! 1154: 1119 0001046E # ! 1155: 1120 0001046E # ! 1156: 1121 0001046E # ! 1157: 1122 0001046E # /************************************************************************ ! 1158: 1123 0001046E # * ! 1159: 1124 0001046E # * SUBTEST 8 - pipelined entry test ! 1160: 1125 0001046E # * ! 1161: 1126 0001046E # ************************************************************************/ ! 1162: 1127 0001046E # divf_8() ! 1163: 1128 0001046E # { ! 1164: 1129 0001046E 13 011d jbr L357 ! 1165: 1130 00010471 L358: ! 1166: 1131 00010471 # force_loop = FALSE; ! 1167: 1132 00010471 4d effffff671 clrl _force_loop ! 1168: 1133 00010477 # subtest = 8; ! 1169: 1134 00010477 0d 08 effffff66a movl $8,_subtest ! 1170: 1135 0001047E # for( index = 0; index < max_divf_1_index; index++ ) { ! 1171: 1136 0001047E 4d effffff664 clrl _index ! 1172: 1137 00010484 L361: ! 1173: 1138 00010484 1d effffff65e effffff659 cmpl _index,_max_divf_1_index ! 1174: 1139 0001048F 91 03 13 00f9 jgeq L360 ! 1175: 1140 00010494 # sgl_ld_acc = divf_1_data[index].op_1; /* get operand 1 */ ! 1176: 1141 00010494 5c 0c effffff64d 50 mull3 $12,_index,r0 ! 1177: 1142 0001049C 0d e000000000 effffff641 movl _divf_1_data(r0),_sgl_ld_acc ! 1178: 1143 000104A7 # sgl_value_1 = divf_1_data[index].op_2; /* get operand 2 */ ! 1179: 1144 000104A7 5c 0c effffff63a 50 mull3 $12,_index,r0 ! 1180: 1145 000104AF 0d e000000004 effffff62e movl _divf_1_data+4(r0),_sgl_value_1 ! 1181: 1146 000104BA # sgl_expected = divf_1_data[index].exp; /* get expected result */ ! 1182: 1147 000104BA 5c 0c effffff627 50 mull3 $12,_index,r0 ! 1183: 1148 000104C2 0d e000000008 effffff61b movl _divf_1_data+8(r0),_sgl_expected ! 1184: 1149 000104CD # /* ! 1185: 1150 000104CD # * If LOOP ON ERROR is set, this is the loop for this subtest. ! 1186: 1151 000104CD # * The force loop flag is set after the first error. ! 1187: 1152 000104CD # */ ! 1188: 1153 000104CD # asm("_divf_8_lp1:"); ! 1189: 1154 000104CD _divf_8_lp1: ! 1190: 1155 000104CD # asm("movl $0,r0"); /* clear r0 */ ! 1191: 1156 000104CD 0d 00 50 movl $0,r0 ! 1192: 1157 000104D0 # asm("ldf r0"); /* load the Acc. with 0.0 */ ! 1193: 1158 000104D0 06 50 ldf r0 ! 1194: 1159 000104D2 # asm("addf _sgl_ld_acc"); /* add the 1st operand */ ! 1195: 1160 000104D2 c6 effffff610 addf _sgl_ld_acc ! 1196: 1161 000104D8 # asm("divf _sgl_value_1"); /* div the 2nd operand */ ! 1197: 1162 000104D8 f6 effffff60a divf _sgl_value_1 ! 1198: 1163 000104DE # asm("stf _sgl_st_acc"); /* store the result */ ! 1199: 1164 000104DE 26 effffff604 stf _sgl_st_acc ! 1200: 1165 000104E4 # if( force_loop ) ! 1201: 1166 000104E4 5d effffff5fe tstl _force_loop ! 1202: 1167 000104EA 31 02 jeql L362 ! 1203: 1168 000104EC # asm("brb _divf_8_lp1");; /* loop on the error */ ! 1204: 1169 000104EC 11 df brb _divf_8_lp1 ! 1205: 1170 000104EE L362: ! 1206: 1171 000104EE # /* ! 1207: 1172 000104EE # * end error loop - test the results ! 1208: 1173 000104EE # */ ! 1209: 1174 000104EE # if( sgl_st_acc != sgl_expected ) { /* COMPARE the values */ ! 1210: 1175 000104EE 1d effffff5f4 effffff5ef cmpl _sgl_st_acc,_sgl_expected ! 1211: 1176 000104F9 21 03 13 0086 jeql L363 ! 1212: 1177 000104FE # errcnt++; /* bump the error count */ ! 1213: 1178 000104FE 6d effffff5e4 incl _errcnt ! 1214: 1179 00010504 # if( prt_error ) { ! 1215: 1180 00010504 5d effffff5de tstl _prt_error ! 1216: 1181 0001050A 31 55 jeql L364 ! 1217: 1182 0001050C # writes(" \n"); /* start a new print line */ ! 1218: 1183 0001050C .data 1 ! 1219: 1184 00000f5c * L365: ! 1220: 1185 00000f5c * 200A00 .ascii " \12\0" ! 1221: 1186 00000f5f * .text ! 1222: 1187 0001050C dd 8f00000f5c pushl $L365 ! 1223: 1188 00010512 fe 08 effffff5cf callf $8,_writes ! 1224: 1189 00010519 # writes("cycle: "); ! 1225: 1190 00010519 .data 1 ! 1226: 1191 00000f5f * L366: ! 1227: 1192 00000f5f * 6379636C653A2000 .ascii "cycle: \0" ! 1228: 1193 00000f67 * .text ! 1229: 1194 00010519 dd 8f00000f5f pushl $L366 ! 1230: 1195 0001051F fe 08 effffff5c2 callf $8,_writes ! 1231: 1196 00010526 # writed( cycle ); ! 1232: 1197 00010526 dd effffff5bc pushl _cycle ! 1233: 1198 0001052C fe 08 effffff5b5 callf $8,_writed ! 1234: 1199 00010533 # writes(" DIVF test "); ! 1235: 1200 00010533 .data 1 ! 1236: 1201 00000f67 * L367: ! 1237: 1202 00000f67 * 2020444956462074657374200 .ascii " DIVF test \0" ! 1238: 0 ! 1239: 1203 00000f74 * .text ! 1240: 1204 00010533 dd 8f00000f67 pushl $L367 ! 1241: 1205 00010539 fe 08 effffff5a8 callf $8,_writes ! 1242: 1206 00010540 # writed( test_no ); ! 1243: 1207 00010540 dd effffff5a2 pushl _test_no ! 1244: 1208 00010546 fe 08 effffff59b callf $8,_writed ! 1245: 1209 0001054D # writes(", subtest 8 (Piped Entry) - BAD FINAL ACC\n"); ! 1246: 1210 0001054D .data 1 ! 1247: 1211 00000f74 * L368: ! 1248: 1212 00000f74 * 2C20737562746573742038202 .ascii ", subtest 8 (Piped Entry) - BAD FINAL ACC\12\0" ! 1249: 8506970656420456E74727929 ! 1250: 202D204241442046494E414C2 ! 1251: 04143430A00 ! 1252: 1213 00000f9f * .text ! 1253: 1214 0001054D dd 8f00000f74 pushl $L368 ! 1254: 1215 00010553 fe 08 effffff58e callf $8,_writes ! 1255: 1216 0001055A # print_divf_data(); ! 1256: 1217 0001055A fe 04 ef00000157 callf $4,_print_divf_data ! 1257: 1218 00010561 # } ! 1258: 1219 00010561 # if( halt_flg ) ! 1259: 1220 00010561 L364: ! 1260: 1221 00010561 5d effffff581 tstl _halt_flg ! 1261: 1222 00010567 31 09 jeql L369 ! 1262: 1223 00010569 # divf_er_halt( BAD_ACC_HLT ); /* halt on the error */ ! 1263: 1224 00010569 dd 01 pushl $1 ! 1264: 1225 0001056B fe 08 ef000001e4 callf $8,_divf_er_halt ! 1265: 1226 00010572 # if( loop_on_err ) { ! 1266: 1227 00010572 L369: ! 1267: 1228 00010572 5d effffff570 tstl _loop_on_err ! 1268: 1229 00010578 31 0a jeql L370 ! 1269: 1230 0001057A # force_loop = TRUE; /* set the force loop flag */ ! 1270: 1231 0001057A 0d 01 effffff567 movl $1,_force_loop ! 1271: 1232 00010581 # asm("brw _divf_8_lp1");; /* and loop on the error */ ! 1272: 1233 00010581 13 ff49 brw _divf_8_lp1 ! 1273: 1234 00010584 # } /* end of loop on error */ ! 1274: 1235 00010584 # } /* end of compare error */ ! 1275: 1236 00010584 L370: ! 1276: 1237 00010584 # } /* end of WHILE loop */ ! 1277: 1238 00010584 L363: ! 1278: 1239 00010584 L359: ! 1279: 1240 00010584 6d effffff55e incl _index ! 1280: 1241 0001058A 13 fef7 jbr L361 ! 1281: 1242 0001058D L360: ! 1282: 1243 0001058D # } /* end of subtest 8 */ ! 1283: 1244 0001058D 40 ret#2 ! 1284: 1245 0001058E .set L355,0x0 ! 1285: 1246 0001058E L357: ! 1286: 1247 0001058E 13 fee0 jbr L358 ! 1287: 1248 00010591 .data ! 1288: 1249 00000d28 * .text ! 1289: 1250 00010591 00 .align 1 ! 1290: 1251 00010592 .globl _divf_9 ! 1291: 1252 00010592 _divf_9: ! 1292: 1253 00010592 0000 .word L371 ! 1293: 1254 00010594 # ! 1294: 1255 00010594 # ! 1295: 1256 00010594 # ! 1296: 1257 00010594 # /************************************************************************ ! 1297: 1258 00010594 # * ! 1298: 1259 00010594 # * SUBTEST 9 - pipelined exit test ! 1299: 1260 00010594 # * ! 1300: 1261 00010594 # ************************************************************************/ ! 1301: 1262 00010594 # divf_9() ! 1302: 1263 00010594 # { ! 1303: 1264 00010594 13 011d jbr L373 ! 1304: 1265 00010597 L374: ! 1305: 1266 00010597 # force_loop = FALSE; ! 1306: 1267 00010597 4d effffff54b clrl _force_loop ! 1307: 1268 0001059D # subtest = 9; ! 1308: 1269 0001059D 0d 09 effffff544 movl $9,_subtest ! 1309: 1270 000105A4 # for( index = 0; index < max_divf_1_index; index++ ) { ! 1310: 1271 000105A4 4d effffff53e clrl _index ! 1311: 1272 000105AA L377: ! 1312: 1273 000105AA 1d effffff538 effffff533 cmpl _index,_max_divf_1_index ! 1313: 1274 000105B5 91 03 13 00f9 jgeq L376 ! 1314: 1275 000105BA # sgl_ld_acc = divf_1_data[index].op_1; /* get operand 1 */ ! 1315: 1276 000105BA 5c 0c effffff527 50 mull3 $12,_index,r0 ! 1316: 1277 000105C2 0d e000000000 effffff51b movl _divf_1_data(r0),_sgl_ld_acc ! 1317: 1278 000105CD # sgl_value_1 = divf_1_data[index].op_2; /* get operand 2 */ ! 1318: 1279 000105CD 5c 0c effffff514 50 mull3 $12,_index,r0 ! 1319: 1280 000105D5 0d e000000004 effffff508 movl _divf_1_data+4(r0),_sgl_value_1 ! 1320: 1281 000105E0 # sgl_expected = divf_1_data[index].exp; /* get expected result */ ! 1321: 1282 000105E0 5c 0c effffff501 50 mull3 $12,_index,r0 ! 1322: 1283 000105E8 0d e000000008 effffff4f5 movl _divf_1_data+8(r0),_sgl_expected ! 1323: 1284 000105F3 # /* ! 1324: 1285 000105F3 # * If LOOP ON ERROR is set, this is the loop for this subtest. ! 1325: 1286 000105F3 # * The force loop flag is set after the first error. ! 1326: 1287 000105F3 # */ ! 1327: 1288 000105F3 # asm("_divf_9_lp1:"); ! 1328: 1289 000105F3 _divf_9_lp1: ! 1329: 1290 000105F3 # asm("movl $0,r0"); /* clear r0 */ ! 1330: 1291 000105F3 0d 00 50 movl $0,r0 ! 1331: 1292 000105F6 # asm("ldf _sgl_ld_acc"); /* load the 1st operand */ ! 1332: 1293 000105F6 06 effffff4ec ldf _sgl_ld_acc ! 1333: 1294 000105FC # asm("divf _sgl_value_1"); /* divide the 2nd operand */ ! 1334: 1295 000105FC f6 effffff4e6 divf _sgl_value_1 ! 1335: 1296 00010602 # asm("addf r0"); /* add a 0.0 to the result */ ! 1336: 1297 00010602 c6 50 addf r0 ! 1337: 1298 00010604 # asm("stf _sgl_st_acc"); /* store the result */ ! 1338: 1299 00010604 26 effffff4de stf _sgl_st_acc ! 1339: 1300 0001060A # if( force_loop ) ! 1340: 1301 0001060A 5d effffff4d8 tstl _force_loop ! 1341: 1302 00010610 31 02 jeql L378 ! 1342: 1303 00010612 # asm("brb _divf_9_lp1");; /* loop on the error */ ! 1343: 1304 00010612 11 df brb _divf_9_lp1 ! 1344: 1305 00010614 L378: ! 1345: 1306 00010614 # /* ! 1346: 1307 00010614 # * end error loop - test the results ! 1347: 1308 00010614 # */ ! 1348: 1309 00010614 # if( sgl_st_acc != sgl_expected ) { /* COMPARE the values */ ! 1349: 1310 00010614 1d effffff4ce effffff4c9 cmpl _sgl_st_acc,_sgl_expected ! 1350: 1311 0001061F 21 03 13 0086 jeql L379 ! 1351: 1312 00010624 # errcnt++; /* bump the error count */ ! 1352: 1313 00010624 6d effffff4be incl _errcnt ! 1353: 1314 0001062A # if( prt_error ) { ! 1354: 1315 0001062A 5d effffff4b8 tstl _prt_error ! 1355: 1316 00010630 31 55 jeql L380 ! 1356: 1317 00010632 # writes(" \n"); /* start a new print line */ ! 1357: 1318 00010632 .data 1 ! 1358: 1319 00000f9f * L381: ! 1359: 1320 00000f9f * 200A00 .ascii " \12\0" ! 1360: 1321 00000fa2 * .text ! 1361: 1322 00010632 dd 8f00000f9f pushl $L381 ! 1362: 1323 00010638 fe 08 effffff4a9 callf $8,_writes ! 1363: 1324 0001063F # writes("cycle: "); ! 1364: 1325 0001063F .data 1 ! 1365: 1326 00000fa2 * L382: ! 1366: 1327 00000fa2 * 6379636C653A2000 .ascii "cycle: \0" ! 1367: 1328 00000faa * .text ! 1368: 1329 0001063F dd 8f00000fa2 pushl $L382 ! 1369: 1330 00010645 fe 08 effffff49c callf $8,_writes ! 1370: 1331 0001064C # writed( cycle ); ! 1371: 1332 0001064C dd effffff496 pushl _cycle ! 1372: 1333 00010652 fe 08 effffff48f callf $8,_writed ! 1373: 1334 00010659 # writes(" DIVF test "); ! 1374: 1335 00010659 .data 1 ! 1375: 1336 00000faa * L383: ! 1376: 1337 00000faa * 2020444956462074657374200 .ascii " DIVF test \0" ! 1377: 0 ! 1378: 1338 00000fb7 * .text ! 1379: 1339 00010659 dd 8f00000faa pushl $L383 ! 1380: 1340 0001065F fe 08 effffff482 callf $8,_writes ! 1381: 1341 00010666 # writed( test_no ); ! 1382: 1342 00010666 dd effffff47c pushl _test_no ! 1383: 1343 0001066C fe 08 effffff475 callf $8,_writed ! 1384: 1344 00010673 # writes(", subtest 9 (Piped Exit) - BAD FINAL ACC\n"); ! 1385: 1345 00010673 .data 1 ! 1386: 1346 00000fb7 * L384: ! 1387: 1347 00000fb7 * 2C20737562746573742039202 .ascii ", subtest 9 (Piped Exit) - BAD FINAL ACC\12\0" ! 1388: 8506970656420457869742920 ! 1389: 2D204241442046494E414C204 ! 1390: 143430A00 ! 1391: 1348 00000fe1 * .text ! 1392: 1349 00010673 dd 8f00000fb7 pushl $L384 ! 1393: 1350 00010679 fe 08 effffff468 callf $8,_writes ! 1394: 1351 00010680 # print_divf_data(); ! 1395: 1352 00010680 fe 04 ef00000031 callf $4,_print_divf_data ! 1396: 1353 00010687 # } ! 1397: 1354 00010687 # if( halt_flg ) ! 1398: 1355 00010687 L380: ! 1399: 1356 00010687 5d effffff45b tstl _halt_flg ! 1400: 1357 0001068D 31 09 jeql L385 ! 1401: 1358 0001068F # divf_er_halt( BAD_ACC_HLT ); /* halt on the error */ ! 1402: 1359 0001068F dd 01 pushl $1 ! 1403: 1360 00010691 fe 08 ef000000be callf $8,_divf_er_halt ! 1404: 1361 00010698 # if( loop_on_err ) { ! 1405: 1362 00010698 L385: ! 1406: 1363 00010698 5d effffff44a tstl _loop_on_err ! 1407: 1364 0001069E 31 0a jeql L386 ! 1408: 1365 000106A0 # force_loop = TRUE; /* set the force loop flag */ ! 1409: 1366 000106A0 0d 01 effffff441 movl $1,_force_loop ! 1410: 1367 000106A7 # asm("brw _divf_9_lp1");; /* and loop on the error */ ! 1411: 1368 000106A7 13 ff49 brw _divf_9_lp1 ! 1412: 1369 000106AA # } /* end of loop on error */ ! 1413: 1370 000106AA # } /* end of compare error */ ! 1414: 1371 000106AA L386: ! 1415: 1372 000106AA # } /* end of WHILE loop */ ! 1416: 1373 000106AA L379: ! 1417: 1374 000106AA L375: ! 1418: 1375 000106AA 6d effffff438 incl _index ! 1419: 1376 000106B0 13 fef7 jbr L377 ! 1420: 1377 000106B3 L376: ! 1421: 1378 000106B3 # } /* end of subtest 9 */ ! 1422: 1379 000106B3 40 ret#2 ! 1423: 1380 000106B4 .set L371,0x0 ! 1424: 1381 000106B4 L373: ! 1425: 1382 000106B4 13 fee0 jbr L374 ! 1426: 1383 000106B7 .data ! 1427: 1384 00000d28 * .text ! 1428: 1385 000106B7 00 .align 1 ! 1429: 1386 000106B8 .globl _print_divf_data ! 1430: 1387 000106B8 _print_divf_data: ! 1431: 1388 000106B8 0000 .word L387 ! 1432: 1389 000106BA # ! 1433: 1390 000106BA # ! 1434: 1391 000106BA # ! 1435: 1392 000106BA # /************************************************************************** ! 1436: 1393 000106BA # * ! 1437: 1394 000106BA # * PRINT THE DATA AND STORE RESULTS ! 1438: 1395 000106BA # * ! 1439: 1396 000106BA # * initial Acc = xxxxxxxx, stored = xxxxxxxx, data index = xx ! 1440: 1397 000106BA # * operand = xxxxxxxx, expected = xxxxxxxx ! 1441: 1398 000106BA # **************************************************************************/ ! 1442: 1399 000106BA # print_divf_data() ! 1443: 1400 000106BA # { ! 1444: 1401 000106BA 13 0095 jbr L389 ! 1445: 1402 000106BD L390: ! 1446: 1403 000106BD # writes("initial Acc = "); ! 1447: 1404 000106BD .data 1 ! 1448: 1405 00000fe1 * L391: ! 1449: 1406 00000fe1 * 696E697469616C20416363203 .ascii "initial Acc = \0" ! 1450: D2000 ! 1451: 1407 00000ff0 * .text ! 1452: 1408 000106BD dd 8f00000fe1 pushl $L391 ! 1453: 1409 000106C3 fe 08 effffff41e callf $8,_writes ! 1454: 1410 000106CA # write32h( sgl_ld_acc ); ! 1455: 1411 000106CA dd effffff418 pushl _sgl_ld_acc ! 1456: 1412 000106D0 fe 08 effffff411 callf $8,_write32h ! 1457: 1413 000106D7 # writes(", stored = "); ! 1458: 1414 000106D7 .data 1 ! 1459: 1415 00000ff0 * L392: ! 1460: 1416 00000ff0 * 2C2020202073746F726564203 .ascii ", stored = \0" ! 1461: D2000 ! 1462: 1417 00000fff * .text ! 1463: 1418 000106D7 dd 8f00000ff0 pushl $L392 ! 1464: 1419 000106DD fe 08 effffff404 callf $8,_writes ! 1465: 1420 000106E4 # write32h( sgl_st_acc ); ! 1466: 1421 000106E4 dd effffff3fe pushl _sgl_st_acc ! 1467: 1422 000106EA fe 08 effffff3f7 callf $8,_write32h ! 1468: 1423 000106F1 # writes(", data index = "); ! 1469: 1424 000106F1 .data 1 ! 1470: 1425 00000fff * L393: ! 1471: 1426 00000fff * 2C20206461746120696E64657 .ascii ", data index = \0" ! 1472: 8203D2000 ! 1473: 1427 00001010 * .text ! 1474: 1428 000106F1 dd 8f00000fff pushl $L393 ! 1475: 1429 000106F7 fe 08 effffff3ea callf $8,_writes ! 1476: 1430 000106FE # writed( index ); ! 1477: 1431 000106FE dd effffff3e4 pushl _index ! 1478: 1432 00010704 fe 08 effffff3dd callf $8,_writed ! 1479: 1433 0001070B # writec('\n'); ! 1480: 1434 0001070B dd 0a pushl $10 ! 1481: 1435 0001070D fe 08 effffff3d4 callf $8,_writec ! 1482: 1436 00010714 # writes(" operand = "); ! 1483: 1437 00010714 .data 1 ! 1484: 1438 00001010 * L395: ! 1485: 1439 00001010 * 202020206F706572616E64203 .ascii " operand = \0" ! 1486: D2000 ! 1487: 1440 0000101f * .text ! 1488: 1441 00010714 dd 8f00001010 pushl $L395 ! 1489: 1442 0001071A fe 08 effffff3c7 callf $8,_writes ! 1490: 1443 00010721 # write32h( sgl_value_1 ); ! 1491: 1444 00010721 dd effffff3c1 pushl _sgl_value_1 ! 1492: 1445 00010727 fe 08 effffff3ba callf $8,_write32h ! 1493: 1446 0001072E # writes(", expected = "); ! 1494: 1447 0001072E .data 1 ! 1495: 1448 0000101f * L396: ! 1496: 1449 0000101f * 2C20206578706563746564203 .ascii ", expected = \0" ! 1497: D2000 ! 1498: 1450 0000102e * .text ! 1499: 1451 0001072E dd 8f0000101f pushl $L396 ! 1500: 1452 00010734 fe 08 effffff3ad callf $8,_writes ! 1501: 1453 0001073B # write32h( sgl_expected ); ! 1502: 1454 0001073B dd effffff3a7 pushl _sgl_expected ! 1503: 1455 00010741 fe 08 effffff3a0 callf $8,_write32h ! 1504: 1456 00010748 # writec('\n'); ! 1505: 1457 00010748 dd 0a pushl $10 ! 1506: 1458 0001074A fe 08 effffff397 callf $8,_writec ! 1507: 1459 00010751 # } ! 1508: 1460 00010751 40 ret#2 ! 1509: 1461 00010752 .set L387,0x0 ! 1510: 1462 00010752 L389: ! 1511: 1463 00010752 13 ff68 jbr L390 ! 1512: 1464 00010755 .data ! 1513: 1465 00000d28 * .text ! 1514: 1466 00010755 00 .align 1 ! 1515: 1467 00010756 .globl _divf_er_halt ! 1516: 1468 00010756 _divf_er_halt: ! 1517: 1469 00010756 0000 .word L397 ! 1518: 1470 00010758 # ! 1519: 1471 00010758 # ! 1520: 1472 00010758 # ! 1521: 1473 00010758 # /************************************************************************** ! 1522: 1474 00010758 # * ! 1523: 1475 00010758 # * HALT ON ERROR ROUTINE ! 1524: 1476 00010758 # * ! 1525: 1477 00010758 # **************************************************************************/ ! 1526: 1478 00010758 # divf_er_halt( halt_code ) ! 1527: 1479 00010758 # int halt_code; ! 1528: 1480 00010758 # { ! 1529: 1481 00010758 13 00af jbr L399 ! 1530: 1482 0001075B L400: ! 1531: 1483 0001075B # sgl_dummy1 = halt_code; /* get the error type */ ! 1532: 1484 0001075B 0d ad04 effffff385 movl 4(fp),_sgl_dummy1 ! 1533: 1485 00010763 # asm("movl _test_no,r0"); /* r0 = test number */ ! 1534: 1486 00010763 0d effffff37f 50 movl _test_no,r0 ! 1535: 1487 0001076A # asm("movl _subtest,r1"); /* r1 = subtest number */ ! 1536: 1488 0001076A 0d effffff378 51 movl _subtest,r1 ! 1537: 1489 00010771 # asm("movl _sgl_dummy1,r2"); /* r2 = error code */ ! 1538: 1490 00010771 0d effffff371 52 movl _sgl_dummy1,r2 ! 1539: 1491 00010778 # asm("movl _cycle,r3"); /* r3 = cycle count */ ! 1540: 1492 00010778 0d effffff36a 53 movl _cycle,r3 ! 1541: 1493 0001077F # asm("movl _sgl_ld_acc,r4"); /* r4 = initial data */ ! 1542: 1494 0001077F 0d effffff363 54 movl _sgl_ld_acc,r4 ! 1543: 1495 00010786 # asm("movl _sgl_value_1,r5"); /* r5 = data dived */ ! 1544: 1496 00010786 0d effffff35c 55 movl _sgl_value_1,r5 ! 1545: 1497 0001078D # asm("movl _sgl_st_acc,r6"); /* r6 = data stored */ ! 1546: 1498 0001078D 0d effffff355 56 movl _sgl_st_acc,r6 ! 1547: 1499 00010794 # if( halt_code == BAD_ACC_HLT ) { ! 1548: 1500 00010794 1d ad04 01 cmpl 4(fp),$1 ! 1549: 1501 00010798 21 10 jneq L401 ! 1550: 1502 0001079A # asm("movl _sgl_expected,r7"); /* r7 = data expected */ ! 1551: 1503 0001079A 0d effffff348 57 movl _sgl_expected,r7 ! 1552: 1504 000107A1 # asm("movl _index,r8"); /* r8 = data index */ ! 1553: 1505 000107A1 0d effffff341 58 movl _index,r8 ! 1554: 1506 000107A8 # } else ! 1555: 1507 000107A8 11 5e jbr L402 ! 1556: 1508 000107AA L401: ! 1557: 1509 000107AA # if( halt_code == BAD_REG_HLT ) { ! 1558: 1510 000107AA 1d ad04 02 cmpl 4(fp),$2 ! 1559: 1511 000107AE 21 3d jneq L403 ! 1560: 1512 000107B0 # sgl_dummy1 = load_regs[index2]; ! 1561: 1513 000107B0 0d effffff332 50 movl _index2,r0 ! 1562: 1514 000107B7 0d 40effffff32a movl _load_regs[r0],_sgl_dummy1 ! 1563: effffff325 ! 1564: 1515 000107C3 # sgl_dummy2 = store_regs[index2]; ! 1565: 1516 000107C3 0d effffff31f 50 movl _index2,r0 ! 1566: 1517 000107CA 0d 40effffff317 movl _store_regs[r0],_sgl_dummy2 ! 1567: effffff312 ! 1568: 1518 000107D6 # asm("movl _index2,r7"); /* r7 = bad register # */ ! 1569: 1519 000107D6 0d effffff30c 57 movl _index2,r7 ! 1570: 1520 000107DD # asm("movl _sgl_dummy2,r8"); /* r8 = actual value */ ! 1571: 1521 000107DD 0d effffff305 58 movl _sgl_dummy2,r8 ! 1572: 1522 000107E4 # asm("movl _sgl_dummy1,r9"); /* r9 = expected value */ ! 1573: 1523 000107E4 0d effffff2fe 59 movl _sgl_dummy1,r9 ! 1574: 1524 000107EB # } else ! 1575: 1525 000107EB 11 1b jbr L404 ! 1576: 1526 000107ED L403: ! 1577: 1527 000107ED # if( halt_code == BAD_PSL_HLT ) { ! 1578: 1528 000107ED 1d ad04 03 cmpl 4(fp),$3 ! 1579: 1529 000107F1 21 15 jneq L405 ! 1580: 1530 000107F3 # asm("movl _init_psl,r7"); /* r7 = initial PSL */ ! 1581: 1531 000107F3 0d effffff2ef 57 movl _init_psl,r7 ! 1582: 1532 000107FA # asm("movl _psl_val,r8"); /* r8 = final PSL */ ! 1583: 1533 000107FA 0d effffff2e8 58 movl _psl_val,r8 ! 1584: 1534 00010801 # asm("movl _exp_psl,r9"); /* r9 = expected PSL */ ! 1585: 1535 00010801 0d effffff2e1 59 movl _exp_psl,r9 ! 1586: 1536 00010808 # }; ! 1587: 1537 00010808 L405: ! 1588: 1538 00010808 L404: ! 1589: 1539 00010808 L402: ! 1590: 1540 00010808 # asm("halt"); /* HALT ... */ ! 1591: 1541 00010808 00 halt ! 1592: 1542 00010809 # } ! 1593: 1543 00010809 40 ret#2 ! 1594: 1544 0001080A .set L397,0x0 ! 1595: 1545 0001080A L399: ! 1596: 1546 0001080A 13 ff4e jbr L400 ! 1597: 1547 0001080D .data ! 1598: 1547 000202F5 .data
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