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Up to [Power 6/32 Unix Tahoe 4.2BSD] / cci / d / macro4|
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1.1 ! root 1: 1 00000000 ! 2: 2 00000000 /* privileged registers constants (addresses) */ ! 3: 3 00000000 ! 4: 4 00000000 ! 5: 5 00000000 ! 6: 6 00000000 .set SBR,0 /*system base register */ ! 7: 7 00000000 .set SLR,1 /*system length reg */ ! 8: 8 00000000 .set P0BR,2 /*p0 base reg */ ! 9: 9 00000000 .set P0LR,3 /*p0 length reg */ ! 10: 10 00000000 .set P1BR,4 /*p1 base reg */ ! 11: 11 00000000 .set P1LR,5 /*p1 length reg */ ! 12: 12 00000000 .set P2BR,6 /*p2 base reg */ ! 13: 13 00000000 .set P2LR,7 /*p2 length reg */ ! 14: 14 00000000 .set IPL,8 /*int priority level reg */ ! 15: 15 00000000 .set MME,9 /*memory mgmt enable reg */ ! 16: 16 00000000 .set TBIA,10 /*trans buf invalidate all */ ! 17: 17 00000000 /*entries */ ! 18: 18 00000000 .set TBIS,11 /*trans buf invalidate single */ ! 19: 19 00000000 /*entry */ ! 20: 20 00000000 .set DCK,12 /*data cache key */ ! 21: 21 00000000 .set CCK,13 /*code cache key */ ! 22: 22 00000000 .set PCBB,14 /*process control block base */ ! 23: 23 00000000 .set ISP,15 /*interrupt stack pointer */ ! 24: 24 00000000 .set SIRR,16 /*software int request reg */ ! 25: 25 00000000 .set SISR,17 /*software int summary reg */ ! 26: 26 00000000 .set SCBB,18 /*system control block base reg */ ! 27: 27 00000000 .set KSP,19 /*kernel stack pointer reg */ ! 28: 28 00000000 .set USP,20 /*user stack pointer */ ! 29: 29 00000000 .set DCB,21 /*CPU2 DCB */ ! 30: 30 00000000 .set PACC,23 /*purge (invalidate) all pages */ ! 31: 31 00000000 /*of process in code cache */ ! 32: 32 00000000 .set P1DC,24 /*purge one page of data cache */ ! 33: 33 00000000 .set PADC,25 /*purge all the pages of */ ! 34: 34 00000000 /*process in data cache */ ! 35: 35 00000000 .set HISR,26 /* Hardware interrupt summary reg */ ! 36: 36 00000000 .set DCR,27 /* Diagnostic control register */ ! 37: 37 00000000 .set PDCS,28 /* Purge 1 data cache slot */ ! 38: 38 00000000 ! 39: 39 00000000 # ! 40: 40 00000000 #TAHOE program status longword ! 41: 41 00000000 # ! 42: 42 00000000 ! 43: 43 00000000 .set PSL_C,0x00000001 /* carry bit */ ! 44: 44 00000000 .set PSL_V,0x00000002 /* overflow bit */ ! 45: 45 00000000 .set PSL_Z,0x00000004 /* zero bit */ ! 46: 46 00000000 .set Z,0x00000004 ! 47: 47 00000000 .set PSL_N,0x00000008 /* negative bit */ ! 48: 48 00000000 .set PSL_T,0x00000010 /* trace enable bit */ ! 49: 49 00000000 .set PSL_I,0x00000020 /* integer overflow enable bit */ ! 50: 50 00000000 .set PSL_EN_OVFL,0x20 /* integer overflow enable bit */ ! 51: 51 00000000 .set PSL_EN_UNDFL,0x40 /* floating underflow enable */ ! 52: 52 00000000 .set PSL_DBL,0x80 /* dbl precision Accumulator bit */ ! 53: 53 00000000 .set PSL_IPL,0x001f0000 /* interrupt priority level */ ! 54: 54 00000000 .set PSL_MOD,0x01000000 /* mode = 1 means user */ ! 55: 55 00000000 .set PSL_IS,0x04000000 /* interrupt stack */ ! 56: 56 00000000 .set PSL_TP,0x40000000 /* trace pending */ ! 57: 57 00000000 ! 58: 58 00000000 # ! 59: 59 00000000 # TAHOE page table entry ! 60: 60 00000000 #/ ! 61: 61 00000000 .set PG_V,0x8000000 ! 62: 62 00000000 .set PG_PROT,0x78000000 ! 63: 63 00000000 .set PG_M,0x04000000 ! 64: 64 00000000 .set PG_USED,0x02000000 ! 65: 65 00000000 .set PG_NC,0x01000000 ! 66: 66 00000000 .set PG_PFNUM,0x003fffff ! 67: 67 00000000 ! 68: 68 00000000 .set PG_NOACC,0 ! 69: 69 00000000 .set PG_KR,0x40000000 ! 70: 70 00000000 .set PG_KW,0x60000000 ! 71: 71 00000000 .set PG_URKR,0x50000000 ! 72: 72 00000000 .set PG_URKW,0x70000000 ! 73: 73 00000000 .set PG_UW,0x78000000 ! 74: 74 00000000 ! 75: 75 00000000 #* PCB offsets & diagnostic extension to pcb */ ! 76: 76 00000000 #* PCB is at pcb0 */ ! 77: 77 00000000 ! 78: 78 00000000 ! 79: 79 00000000 .set PCB_SIZE, 24 ! 80: 80 00000000 .set PCB_KSP, 0 ! 81: 81 00000000 .set PCB_USP, 4 ! 82: 82 00000000 .set PCB_R0, 8 ! 83: 83 00000000 .set PCB_R1, 12 ! 84: 84 00000000 .set PCB_R2, 16 ! 85: 85 00000000 .set PCB_R3, 20 ! 86: 86 00000000 .set PCB_R4, 24 ! 87: 87 00000000 .set PCB_R5, 28 ! 88: 88 00000000 .set PCB_R6, 32 ! 89: 89 00000000 .set PCB_R7, 36 ! 90: 90 00000000 .set PCB_R8, 40 ! 91: 91 00000000 .set PCB_R9, 44 ! 92: 92 00000000 .set PCB_R10, 48 ! 93: 93 00000000 .set PCB_R11, 52 ! 94: 94 00000000 .set PCB_R12, 56 ! 95: 95 00000000 .set PCB_R13, 60 ! 96: 96 00000000 .set PCB_PC, 64 ! 97: 97 00000000 .set PCB_PSL, 68 ! 98: 98 00000000 .set PCB_P0BR, 72 ! 99: 99 00000000 .set PCB_P0LR, 76 ! 100: 100 00000000 .set PCB_P1BR, 80 ! 101: 101 00000000 .set PCB_P1LR, 84 ! 102: 102 00000000 .set PCB_P2BR, 88 ! 103: 103 00000000 .set PCB_P2LR, 92 ! 104: 104 00000000 .set PCB_ACCM, 96 ! 105: 105 00000000 .set PCB_ACCL, 100 ! 106: 106 00000000 #* ! 107: 107 00000000 # Diagnostic pcb extension ! 108: 108 00000000 #/ ! 109: 109 00000000 .set PCB_STAT, 104 /*process status,statistics,id,etc*/ ! 110: 110 00000000 ! 111: 111 00000000 ! 112: 112 00000000 ! 113: 113 00000000 #* fundamental constants */ ! 114: 114 00000000 ! 115: 115 00000000 #* ! 116: 116 00000000 # fundamental constants of the implementation-- ! 117: 117 00000000 # cannot be changed easily. ! 118: 118 00000000 #/ ! 119: 119 00000000 ! 120: 120 00000000 .set NBPG,1024 ! 121: 121 00000000 .set PGOFSET,(NBPG-1) /* byte offset into page */ ! 122: 122 00000000 .set PGSHIFT,10 /* LOG2(NBPG) */ ! 123: 123 00000000 .set HIGH,0x1f ! 124: 124 00000000 ! 125: 125 00000000 ! 126: 126 00000000 #* SCB offsets */ ! 127: 127 00000000 #* SCB is at scb */ ! 128: 128 00000000 ! 129: 129 00000000 .set PFVEC,1*4 /*power fail */ ! 130: 130 00000000 .set PRVEC,2*4 /*power restore */ ! 131: 131 00000000 .set CLOCKVEC,7*4 /*hard clock vector */ ! 132: 132 00000000 .set CRVEC,0xa*4 /*console receive */ ! 133: 133 00000000 .set CXVEC,44 /*console transmit */ ! 134: 134 00000000 .set SIVEC1,0x1e*4 /*software int vec #1 */ ! 135: 135 00000000 /*for 2,3,..15, sub 4,8,.. 56 */ ! 136: 136 00000000 /*from SIVEC1 */ ! 137: 137 00000000 .set BEVEC,0x20*4 /*bus error */ ! 138: 138 00000000 .set SYSVEC,0x2b*4 /*system call (kcall) */ ! 139: 139 00000000 .set PINSTVEC,0x2c*4 /*privileged instruction fault */ ! 140: 140 00000000 .set PRIVSVEC,0x2c*4 /*privileged instruction fault */ ! 141: 141 00000000 .set ROVEC,0x2d*4 /*reserved operand fault */ ! 142: 142 00000000 .set RAVEC,0x2e*4 /*reserved addressing fault */ ! 143: 143 00000000 .set PROTVEC,0x2f*4 /*access control violation */ ! 144: 144 00000000 .set TRANS,0x30 /*translation fault vector */ ! 145: 145 00000000 .set TRANSVEC,0x30*4 /*translation fault vector */ ! 146: 146 00000000 .set KSPVEC,0x31*4 /*kernel stack not valid vector */ ! 147: 147 00000000 .set TRACEVEC,0x32*4 /*trace vector */ ! 148: 148 00000000 .set BPTVEC,0x33*4 /*break point fault */ ! 149: 149 00000000 .set ARITHVEC,0x34*4 /*arithmetic trap */ ! 150: 150 00000000 .set ALIGNVEC,0x35*4 /*alignment vector */ ! 151: 151 00000000 .set FPMVEC,0x37*4 /*fpp emulation vector */ ! 152: 152 00000000 .set IO14VEC,256 /*io vector, ipl #14 */ ! 153: 153 00000000 .set IO15VEC,320 /*io vector, ipl #15 */ ! 154: 154 00000000 .set IO16VEC,384 /*io vector, ipl #16 */ ! 155: 155 00000000 .set IO17VEC,448 /*io vector, ipl #17 */ ! 156: 156 00000000 ! 157: 157 00000000 #* SPT (system page table) offsets */ ! 158: 158 00000000 #* SPT is at Sysmap */ ! 159: 159 00000000 ! 160: 160 00000000 .set SCBPTE,8 /*system control block pte offset*/ ! 161: 161 00000000 .set BUFPTE,12 /*buffer pte offset */ ! 162: 162 00000000 .set ISPTE,16 /*interrupt stack page 0 */ ! 163: 163 00000000 .set IS1PTE,20 /*interrupt stack page 1 */ ! 164: 164 00000000 .set SPTPTE,20 /*system page table page 1 */ ! 165: 165 00000000 .set SPT1PTE,20 /*system page table page 2 */ ! 166: 166 00000000 .set IOMAPPTE,24 /*io map */ ! 167: 167 00000000 .set PCBPTE,28 /*process control blocks pte */ ! 168: 168 00000000 .set U0P0PTE,32 /*U0 p0pt pte */ ! 169: 169 00000000 .set U0P1PTE,36 /*U0 p1pt pte */ ! 170: 170 00000000 .set U0P2PTE,40 /*U0 p2pt pte */ ! 171: 171 00000000 .set U1P0PTE,44 ! 172: 172 00000000 .set U1P1PTE,48 ! 173: 173 00000000 .set U1P2PTE,52 ! 174: 174 00000000 .set U2P0PTE,56 ! 175: 175 00000000 .set U2P1PTE,60 ! 176: 176 00000000 .set U2P2PTE,64 ! 177: 177 00000000 .set U3P0PTE,68 ! 178: 178 00000000 .set U3P1PTE,72 ! 179: 179 00000000 .set U3P2PTE,76 ! 180: 180 00000000 .set U4P0PTE,80 ! 181: 181 00000000 .set U4P1PTE,84 ! 182: 182 00000000 .set U4P2PTE,88 ! 183: 183 00000000 .set U5P0PTE,92 ! 184: 184 00000000 .set U5P1PTE,96 ! 185: 185 00000000 .set U5P2PTE,100 ! 186: 186 00000000 .set U6P0PTE,104 ! 187: 187 00000000 .set U6P1PTE,108 ! 188: 188 00000000 .set U6P2PTE,112 ! 189: 189 00000000 .set U7P0PTE,116 /*U7 p0pt pte */ ! 190: 190 00000000 .set U7P1PTE,120 /*U7 p1pt pte */ ! 191: 191 00000000 .set U7P2PTE,124 /*U7 p2pt pte */ ! 192: 192 00000000 .set IOB0PTE,128 /*io buffer 0 pte */ ! 193: 193 00000000 .set IOB1PTE,132 ! 194: 194 00000000 .set IOB2PTE,136 ! 195: 195 00000000 .set IOB3PTE,140 ! 196: 196 00000000 .set IOB4PTE,144 ! 197: 197 00000000 .set IOB5PTE,148 ! 198: 198 00000000 .set IOB6PTE,152 ! 199: 199 00000000 .set IOB7PTE,156 /*io buffer 7 pte */ ! 200: 200 00000000 ! 201: 201 00000000 ! 202: 202 00000000 #* trap.h 4.6 81/03/03 */ ! 203: 203 00000000 ! 204: 204 00000000 #* ! 205: 205 00000000 #* Trap type values ! 206: 206 00000000 #/ ! 207: 207 00000000 ! 208: 208 00000000 .set RESADFLT,0 /* reserved addressing fault */ ! 209: 209 00000000 .set PRIVINFLT,1 /* privileged instruction fault */ ! 210: 210 00000000 .set RESOPFLT,2 /* reserved operand fault */ ! 211: 211 00000000 .set BPTFLT,3 /* bpt instruction fault */ ! 212: 212 00000000 .set ALIGNFLT,4 /* alignment fault */ ! 213: 213 00000000 .set SYSCALL,5 /* kcall instruction (syscall trap) */ ! 214: 214 00000000 .set ARITHTRAP,6 /* arithmetic trap */ ! 215: 215 00000000 .set PROTFLT,7 /* protection fault */ ! 216: 216 00000000 .set TRCTRAP,8 /* trace trap */ ! 217: 217 00000000 .set TRANSFLT,9 /* translation not valid fault */ ! 218: 218 00000000 .set DONE,255 ! 219: 219 00000000 ! 220: 220 00000000 # ! 221: 221 00000000 # Event codes ! 222: 222 00000000 # ! 223: 223 00000000 .set RTCLOCK_CODE,7 /* real time clock event */ ! 224: 224 00000000 .set RESOP_CODE,0x2d /* reserved operand fault */ ! 225: 225 00000000 .set RESAD_CODE,0x2e /* reserved address fault */ ! 226: 226 00000000 .set ARITH_CODE,0x34 /* arithmetic fault */ ! 227: 227 00000000 .set FPM_CODE,0x37 /* fpp emulation trap */ ! 228: 228 00000000 .set INTEGER_OVERFLOW,1 /* code for arith. fault */ ! 229: 229 00000000 ! 230: 230 00000000 # ! 231: 231 00000000 # Arithmetic Event types ! 232: 232 00000000 # ! 233: 233 00000000 .set INT_OVFL_CODE,1 /* integer overflow */ ! 234: 234 00000000 .set INT_0_DIV_CODE,2 /* integer divide by 0 */ ! 235: 235 00000000 .set FLT_0_DIV_CODE,3 /* floating divide by 0 */ ! 236: 236 00000000 .set FLT_OVFL_CODE,4 /* floating overflow */ ! 237: 237 00000000 .set FLT_UNDFL_CODE,5 /* floating underflow */ ! 238: 238 00000000 ! 239: 239 00000000 # ! 240: 240 00000000 # Floating Point Instruction Op-Codes ! 241: 241 00000000 # ! 242: 242 00000000 .set LDF_OP_CODE,0x06 /* sgl load acc. instr */ ! 243: 243 00000000 .set LDD_OP_CODE,0x07 /* dbl load acc. instr */ ! 244: 244 00000000 .set LNF_OP_CODE,0x16 /* sgl load-neg acc. instr */ ! 245: 245 00000000 .set LND_OP_CODE,0x17 /* dbl load-neg acc. instr */ ! 246: 246 00000000 .set STF_OP_CODE,0x26 /* sgl store acc. instr */ ! 247: 247 00000000 .set STD_OP_CODE,0x27 /* dbl store acc. instr */ ! 248: 248 00000000 .set CMPF_OP_CODE,0x36 /* sgl compare instr */ ! 249: 249 00000000 .set CMPD_OP_CODE,0x37 /* dbl compare instr */ ! 250: 250 00000000 .set CMPF2_OP_CODE,0x46 /* sgl compare 2 instr */ ! 251: 251 00000000 .set CMPD2_OP_CODE,0x47 /* dbl compare 2 instr */ ! 252: 252 00000000 .set TSTF_OP_CODE,0x56 /* sgl test acc. instr */ ! 253: 253 00000000 .set TSTD_OP_CODE,0x57 /* dbl test acc. instr */ ! 254: 254 00000000 .set PUSHD_OP_CODE,0x67 /* dbl push acc. instr */ ! 255: 255 00000000 .set CVLF_OP_CODE,0x76 /* convert int to sgl instr */ ! 256: 256 00000000 .set CVLD_OP_CODE,0x77 /* convert int to dbl instr */ ! 257: 257 00000000 .set CVFL_OP_CODE,0x86 /* convert sgl to int instr */ ! 258: 258 00000000 .set CVDL_OP_CODE,0x87 /* convert dbl to int instr */ ! 259: 259 00000000 .set LDFD_OP_CODE,0x97 /* load sgl to dbl instr */ ! 260: 260 00000000 .set CVDF_OP_CODE,0xa6 /* convert dbl to sgl instr */ ! 261: 261 00000000 .set NEGF_OP_CODE,0xb6 /* negate sgl acc. instr */ ! 262: 262 00000000 .set NEGD_OP_CODE,0xb7 /* negate dbl acc. instr */ ! 263: 263 00000000 .set ADDF_OP_CODE,0xc6 /* sgl add instr */ ! 264: 264 00000000 .set ADDD_OP_CODE,0xc7 /* dbl add instr */ ! 265: 265 00000000 .set SUBF_OP_CODE,0xd6 /* sgl subtract instr */ ! 266: 266 00000000 .set SUBD_OP_CODE,0xd7 /* dbl subtract instr */ ! 267: 267 00000000 .set MULF_OP_CODE,0xe6 /* sgl multiply instr */ ! 268: 268 00000000 .set MULD_OP_CODE,0xe7 /* dbl multiply instr */ ! 269: 269 00000000 .set DIVF_OP_CODE,0xf6 /* sgl divide instr */ ! 270: 270 00000000 .set DIVD_OP_CODE,0xf7 /* dbl divide instr */ ! 271: 271 00000000 .set SINF_OP_CODE,0x05 /* sgl sine instr */ ! 272: 272 00000000 .set COSF_OP_CODE,0x15 /* sgl cosine instr */ ! 273: 273 00000000 .set ATANF_OP_CODE,0x25 /* sgl arc-tangent instr */ ! 274: 274 00000000 .set LOGF_OP_CODE,0x35 /* sgl natural log instr */ ! 275: 275 00000000 .set SQRTF_OP_CODE,0x45 /* sgl square root instr */ ! 276: 276 00000000 .set EXPF_OP_CODE,0x55 /* sgl "e to the x" instr */ ! 277: 277 00000000 .set MULL2_OP_CODE,0x4c /* integer multiply - 2 ops */ ! 278: 278 00000000 .set MULL3_OP_CODE,0x5c /* integer multiply - 3 ops */ ! 279: 279 00000000 ! 280: 280 00000000 ! 281: 281 00000000 # ! 282: 282 00000000 # Addressing test constants - These must agree with "fpp_defs.h" ! 283: 283 00000000 # ! 284: 284 00000000 .set ADR_ABSOLUTE,1 /* absolute address */ ! 285: 285 00000000 .set ADR_LITERAL,2 /* literal -short immediate byte */ ! 286: 286 00000000 .set ADR_IM_B,3 /* immediate byte */ ! 287: 287 00000000 .set ADR_IM_W,4 /* immediate word */ ! 288: 288 00000000 .set ADR_IM_L,5 /* immediate long-word */ ! 289: 289 00000000 .set ADR_B_DSP,6 /* byte displ relative */ ! 290: 290 00000000 .set ADR_W_DSP,7 /* word displ relative */ ! 291: 291 00000000 .set ADR_L_DSP,8 /* long-word displ relative */ ! 292: 292 00000000 .set ADR_B_DSP_DEF,9 /* byte displ relative deferred */ ! 293: 293 00000000 .set ADR_W_DSP_DEF,10 /* word displ relative deferred */ ! 294: 294 00000000 .set ADR_L_DSP_DEF,11 /* L-word displ relative deferred */ ! 295: 295 00000000 .set ADR_REG,12 /* direct register */ ! 296: 296 00000000 .set ADR_REG_DEF,13 /* register deferred */ ! 297: 297 00000000 .set ADR_FP_DEF,14 /* FP deferred */ ! 298: 298 00000000 .set ADR_SP_DEF,15 /* SP deferred */ ! 299: 299 00000000 .set ADR_PUSH,16 /* auto-decrement SP */ ! 300: 300 00000000 .set ADR_POP,17 /* auto-increment SP */ ! 301: 301 00000000 .set ADR_POP_DEF,18 /* auto-increment SP deferred */ ! 302: 302 00000000 .set ADR_REG_B,19 /* register + byte displ */ ! 303: 303 00000000 .set ADR_REG_W,20 /* register + word displ */ ! 304: 304 00000000 .set ADR_REG_L,21 /* register + long-word displ */ ! 305: 305 00000000 .set ADR_REG_B_DEF,22 /* register + byte displ deferred */ ! 306: 306 00000000 .set ADR_REG_W_DEF,23 /* register + word displ deferred */ ! 307: 307 00000000 .set ADR_REG_L_DEF,24 /* register + L-word displ deferred */ ! 308: 308 00000000 .set ADR_I_FP_DEF,25 /* indexed (frame pointer deferred) */ ! 309: 309 00000000 .set ADR_I_L,26 /* indexed (longword displacement) */ ! 310: 310 00000000 ! 311: 311 00000000 ! 312: 312 00000000 #************************************************************************* ! 313: 313 00000000 # ! 314: 314 00000000 # Stuff for the Demand Paging , Events, & Addressing Tests ! 315: 315 00000000 # ! 316: 316 00000000 #************************************************************************/ ! 317: 317 00000000 .set SGL,1 /* sgl precision data */ ! 318: 318 00000000 .set DBL,2 /* dbl precision data */ ! 319: 319 00000000 .set ENABLE_EVENTS,0x60 /* enable ovfl & undfl events */ ! 320: 320 00000000 .set NONE,0 /* no operand flag */ ! 321: 321 00000000 .set LOAD,1 /* read-the-operand flag */ ! 322: 322 00000000 .set STORE,2 /* store-the-operand flag */ ! 323: 323 00000000 ! 324: 324 00000000 .set NO_EVT_HLT,1 /* halt code: did not Get event */ ! 325: 325 00000000 .set EVT_MSK_HLT,2 /* halt code: got masked event */ ! 326: 326 00000000 .set BAD_PSL_HLT,3 /* halt code: wrong PSL value */ ! 327: 327 00000000 .set PUSH_CNT_HLT,4 /* halt code: wrong # ops on stk */ ! 328: 328 00000000 .set PUSH_PSL_HLT,5 /* halt code: bad PSL on stack */ ! 329: 329 00000000 .set PUSH_PC_HLT,6 /* halt code: bad PC on stack */ ! 330: 330 00000000 .set BAD_REG_HLT,7 /* halt code: bad final register */ ! 331: 331 00000000 .set BAD_ACC_HLT,8 /* halt code: bad final Acc. */ ! 332: 332 00000000 ! 333: 333 00000000 # ! 334: 334 00000000 # set DMP_PG_0 to the 1st empty page ! 335: 335 00000000 # ! 336: 336 00000000 .set DMP_PG_0,0x36000 ! 337: 337 00000000 .set DMP_PG_1,DMP_PG_0+0x400 ! 338: 338 00000000 .set DMP_PG_2,DMP_PG_1+0x400 ! 339: 339 00000000 .set DMP_PG_3,DMP_PG_2+0x400 ! 340: 340 00000000 .set DMP_PG_4,DMP_PG_3+0x400 ! 341: 341 00000000 .set DMP_PG_5,DMP_PG_4+0x400 ! 342: 342 00000000 .set DMP_PG_6,DMP_PG_5+0x400 ! 343: 343 00000000 .set DMP_PG_7,DMP_PG_6+0x400 ! 344: 344 00000000 .set DMP_PG_8,DMP_PG_7+0x400 ! 345: 345 00000000 .set DMP_PG_9,DMP_PG_8+0x400 ! 346: 346 00000000 .set DMP_PG_10,DMP_PG_9+0x400 ! 347: 347 00000000 .set DMP_PG_11,DMP_PG_10+0x400 ! 348: 348 00000000 .set DMP_PG_12,DMP_PG_11+0x400 ! 349: 349 00000000 .set DMP_PG_13,DMP_PG_12+0x400 ! 350: 350 00000000 ! 351: 351 00000000 # ! 352: 352 00000000 # test code space for the address / demand page tests ! 353: 353 00000000 # ! 354: 354 00000000 .set START_OF_CODE,DMP_PG_1-20 /* 1st addr of test-code space */ ! 355: 355 00000000 .set CODE_BUF_SIZE,40 /* # bytes in test-code space */ ! 356: 356 00000000 .set END_OF_CODE,START_OF_CODE+CODE_BUF_SIZE ! 357: 357 00000000 ! 358: 358 00000000 # ! 359: 359 00000000 # data locations used by the event and demand page tests ! 360: 360 00000000 # ! 361: 361 00000000 .set _dmp_byte_op_1,DMP_PG_1+0x40 /* 'byte offset' data */ ! 362: 362 00000000 .set _dmp_byte_op_2,DMP_PG_1+0x60 /* 'byte offset' data */ ! 363: 363 00000000 .set _dmp_byte_op_3,DMP_PG_1+0x80 /* 'byte offset' data */ ! 364: 364 00000000 .set _dmp_op_1,DMP_PG_3-4 /* 1st data word */ ! 365: 365 00000000 .set _dmp_op_1_ptr,DMP_PG_4+0x30 /* ptr to 1st data wd */ ! 366: 366 00000000 .set _dmp_op_2_ptr,DMP_PG_5+0x30 /* ptr to 2nd data wd */ ! 367: 367 00000000 .set _dmp_op_2,DMP_PG_7-4 /* 2nd data word */ ! 368: 368 00000000 .set _dmp_op_3,DMP_PG_8 /* 3rd data word */ ! 369: 369 00000000 .set _dmp_op_3_ptr,DMP_PG_9+0x30 /* ptr to 3rd data wd */ ! 370: 370 00000000 .set _dmp_op_4,DMP_PG_10 /* 4th data (for pipes) */ ! 371: 371 00000000 .set _dmp_op_5,DMP_PG_11 /* 5th data (for pipes) */ ! 372: 372 00000000 .set _sp_minus,DMP_PG_13-4 /* SP for POPs */ ! 373: 373 00000000 .set _sp_page,DMP_PG_13 /* SP page boundary */ ! 374: 374 00000000 .set _sp_plus,DMP_PG_13+4 /* SP for PUSHs */ ! 375: 375 00000000 ! 376: 376 00000000 ! 377: 377 00000000 ! 378: 378 00000000 /************************************************************************** ! 379: 383 00000000 * ! 380: 384 00000000 * FLOATING POINT MACRO TEST GLOBAL VARIABLES ! 381: 385 00000000 * ! 382: 386 00000000 **************************************************************************/ ! 383: 387 00000000 ! 384: 388 00000000 ! 385: Symbol _sp_plus,DMP_ not found --- ! 386: 389 00000000 00000000 filler: ! 387: 390 00000004 .align 2 /* longword align */ ! 388: 391 00000004 .globl _run_list ! 389: 392 00000004 _run_list: ! 390: 393 00000004 .long 0 /* user entered test to execute */ ! 391: 394 0000BC88 00000000 .align 2 /* longword align */ ! 392: 395 0000BC8C ! 393: 396 0000BC8C .globl _test_no ! 394: 397 0000BC8C _test_no: ! 395: 398 0000BC8C 00000000 .long 0 /* test # being executed */ ! 396: 399 0000BC90 ! 397: 400 0000BC90 .globl _subtest ! 398: 401 0000BC90 _subtest: ! 399: 402 0000BC90 00000000 .long 0 /* subtest # being executed */ ! 400: 403 0000BC94 ! 401: 404 0000BC94 .globl _cycle ! 402: 405 0000BC94 _cycle: ! 403: 406 0000BC94 00000000 .long 0 /* current test cycle */ ! 404: 407 0000BC98 ! 405: 408 0000BC98 .globl _run_all ! 406: 409 0000BC98 _run_all: ! 407: 410 0000BC98 .long 0 /* flag - if <> 0, run all tests */ ! 408: 411 0000BC98 6d efffffffe6 ! 409: 412 0000BC9E 20 .align 2 ! 410: 413 0000BC9F .globl _Hardclk ! 411: 414 0000BC9F 00 _Hardclk: ! 412: 415 0000BCA0 incl _clk_cnt ! 413: 416 0000BCA0 00000000 rei ! 414: 417 0000BCA4 ! 415: 418 0000BCA4 00000000 .align 2 ! 416: 419 0000BCA8 .globl _tstmsk ! 417: 420 0000BCA8 _tstmsk: .long 0 /* tests to run */ ! 418: 421 0000BCA8 .globl _ss1 ! 419: 422 0000BCA8 00000000 _ss1: .long 0 /* If 1 then do not print heading messages */ ! 420: 423 0000BCAC ! 421: 424 0000BCAC .globl _zero /* a known '0' data pattern */ ! 422: 425 0000BCAC _zero: ! 423: 426 0000BCAC 00000000 .long 0 ! 424: 427 0000BCB0 ! 425: 428 0000BCB0 .globl _nonstop /* continuous testing flag */ ! 426: 429 0000BCB0 _nonstop: ! 427: 430 0000BCB0 00000000 .long 0 ! 428: 431 0000BCB4 ! 429: 432 0000BCB4 .globl _OPTIONS /* r1 options */ ! 430: 433 0000BCB4 _OPTIONS: ! 431: 434 0000BCB4 00000000 .long 0 ! 432: 435 0000BCB8 ! 433: 436 0000BCB8 .globl _halt_flg /* b(0) flag -halt on error */ ! 434: 437 0000BCB8 _halt_flg: ! 435: 438 0000BCB8 00000000 .long 0 ! 436: 439 0000BCBC ! 437: 440 0000BCBC .globl _loop_on_err /* b(1) flag -loop on error */ ! 438: 441 0000BCBC _loop_on_err: ! 439: 442 0000BCBC 00000000 .long 0 ! 440: 443 0000BCC0 ! 441: 444 0000BCC0 .globl _prt_error /* b(2) flag -print error messages */ ! 442: 445 0000BCC0 _prt_error: ! 443: 446 0000BCC0 00000000 .long 0 ! 444: 447 0000BCC4 ! 445: 448 0000BCC4 .globl _prt_hdrs /* b(3) flag -print header messages */ ! 446: 449 0000BCC4 _prt_hdrs: ! 447: 450 0000BCC4 00000000 .long 0 ! 448: 451 0000BCC8 ! 449: 452 0000BCC8 .globl _en_data_cache /* b(4) flag -enable the data cache */ ! 450: 453 0000BCC8 _en_data_cache: ! 451: 454 0000BCC8 00000000 .long 0 ! 452: 455 0000BCCC ! 453: 456 0000BCCC .globl _user_mode /* b(5) flag -run DMP tests in user mode */ ! 454: 457 0000BCCC _user_mode: ! 455: 458 0000BCCC 00000000 .long 0 ! 456: 459 0000BCD0 ! 457: 460 0000BCD0 .globl _evt_inst /* R3 flag -instruction op-code to test */ ! 458: 461 0000BCD0 _evt_inst: ! 459: 462 0000BCD0 00000000 .long 0 ! 460: 463 0000BCD4 ! 461: 464 0000BCD4 .globl _no_fpp_wcs /* flag -the NO-FPP WCS was loaded */ ! 462: 465 0000BCD4 _no_fpp_wcs: ! 463: 466 0000BCD4 00000000 .long 0 ! 464: 467 0000BCD8 ! 465: 468 0000BCD8 .globl _emulated_inst /* flag -instr is emulated w/ no-fpp wcs */ ! 466: 469 0000BCD8 _emulated_inst: ! 467: 470 0000BCD8 00000000 .long 0 ! 468: 471 0000BCDC ! 469: 472 0000BCDC .globl _force_loop /* flag -force loop after error if set */ ! 470: 473 0000BCDC _force_loop: ! 471: 474 0000BCDC 00000000 .long 0 ! 472: 475 0000BCE0 ! 473: 476 0000BCE0 .globl _clock_event /* flag - a clock event occurred */ ! 474: 477 0000BCE0 _clock_event: ! 475: 478 0000BCE0 00000000 .long 0 ! 476: 479 0000BCE4 ! 477: 480 0000BCE4 .globl _test_event /* flag - type of event under test */ ! 478: 481 0000BCE4 _test_event: ! 479: 482 0000BCE4 00000000 .long 0 ! 480: 483 0000BCE8 ! 481: 484 0000BCE8 .globl _exp_event /* flag - expect fpp event & type expected */ ! 482: 485 0000BCE8 _exp_event: ! 483: 486 0000BCE8 00000000 .long 0 ! 484: 487 0000BCEC ! 485: 488 0000BCEC .globl _exp_code /* flag - type of arithmetic fault expected */ ! 486: 489 0000BCEC _exp_code: ! 487: 490 0000BCEC 00000000 .long 0 ! 488: 491 0000BCF0 ! 489: 492 0000BCF0 .globl _evt_disabled /* flag - event is disabled in the PSW */ ! 490: 493 0000BCF0 _evt_disabled: ! 491: 494 0000BCF0 0000 .long 0 ! 492: 495 0000BCF2 0000 ! 493: 496 0000BCF4 .globl _disable_mask /* mask to disable events in the PSW */ ! 494: 497 0000BCF4 _disable_mask: ! 495: 498 0000BCF4 .word 0 ! 496: 499 0000BCF4 00000000 .align 2 ! 497: 500 0000BCF8 ! 498: 501 0000BCF8 .globl _nop_cnt /* # of NOPs between test instructions */ ! 499: 502 0000BCF8 _nop_cnt: ! 500: 503 0000BCF8 00000000 .long 0 ! 501: 504 0000BCFC ! 502: 505 0000BCFC .globl _pipe_test /* flag - pipelineing test in progress */ ! 503: 506 0000BCFC _pipe_test: ! 504: 507 0000BCFC 00000000 .long 0 ! 505: 508 0000BD00 ! 506: 509 0000BD00 .globl _pipe_inst1 /* 1st instruction in pipelined test */ ! 507: 510 0000BD00 _pipe_inst1: ! 508: 511 0000BD00 00000000 .long 0 ! 509: 512 0000BD04 ! 510: 513 0000BD04 .globl _pipe_inst2 /* last instruction in pipelined test */ ! 511: 514 0000BD04 _pipe_inst2: ! 512: 515 0000BD04 00000000 .long 0 ! 513: 516 0000BD08 ! 514: 517 0000BD08 .globl _event_msg /* pointer to event message */ ! 515: 518 0000BD08 _event_msg: ! 516: 519 0000BD08 00000000 .long 0 ! 517: 520 0000BD0C ! 518: 521 0000BD0C .globl _event_return /* return address after fpp event */ ! 519: 522 0000BD0C _event_return: ! 520: 523 0000BD0C 00000000 .long 0 ! 521: 524 0000BD10 ! 522: 525 0000BD10 .globl _unexp_event_ret /* return address after unexpected event */ ! 523: 526 0000BD10 _unexp_event_ret: ! 524: 527 0000BD10 00000000 .long 0 ! 525: 528 0000BD14 ! 526: 529 0000BD14 .globl _event_type /* event type (arith, resop, etc.) */ ! 527: 530 0000BD14 _event_type: ! 528: 531 0000BD14 00000000 .long 0 ! 529: 532 0000BD18 ! 530: 533 0000BD18 .globl _event_code /* arith fault type (ovfl, undfl,...) */ ! 531: 534 0000BD18 _event_code: ! 532: 535 0000BD18 00000000 .long 0 ! 533: 536 0000BD1C ! 534: 537 0000BD1C .globl _fpm_trap_occurred /* flag -got an FPM trap */ ! 535: 538 0000BD1C _fpm_trap_occurred: ! 536: 539 0000BD1C 00000000 .long 0 ! 537: 540 0000BD20 ! 538: 541 0000BD20 .globl _push_cnt /* # longwords pushed on stack by an event */ ! 539: 542 0000BD20 _push_cnt: ! 540: 543 0000BD20 00000000 .long 0 ! 541: 544 0000BD24 ! 542: 545 0000BD24 .globl _exp_push_cnt /* # longwords expected to be pushed */ ! 543: 546 0000BD24 _exp_push_cnt: ! 544: 547 0000BD24 00000000 .long 0 ! 545: 548 0000BD28 ! 546: 549 0000BD28 .globl _i_cache_hit /* instruction cache hit flag */ ! 547: 550 0000BD28 _i_cache_hit: ! 548: 551 0000BD28 00000000 .long 0 ! 549: 552 0000BD2C ! 550: 553 0000BD2C .globl _monitor_fp /* the monitor's frame pointer */ ! 551: 554 0000BD2C _monitor_fp: ! 552: 555 0000BD2C 00000000 .long 0 ! 553: 556 0000BD30 ! 554: 557 0000BD30 .globl _monitor_sp /* the monitor's stack pointer */ ! 555: 558 0000BD30 _monitor_sp: ! 556: 559 0000BD30 00000000 .long 0 ! 557: 560 0000BD34 ! 558: 561 0000BD34 .globl _run_code_psl /* "run_code"'s entry PSL */ ! 559: 562 0000BD34 _run_code_psl: ! 560: 563 0000BD34 00000000 .long 0 ! 561: 564 0000BD38 ! 562: 565 0000BD38 .globl _event_pc /* PC pushed on the stack by an event */ ! 563: 566 0000BD38 _event_pc: ! 564: 567 0000BD38 00000000 .long 0 ! 565: 568 0000BD3C ! 566: 569 0000BD3C .globl _event_psl /* PSL pushed on the stack by an event */ ! 567: 570 0000BD3C _event_psl: ! 568: 571 0000BD3C 00000000 .long 0 ! 569: 572 0000BD40 00000000 ! 570: 573 0000BD44 .globl _post_evt_acc /* Accumulator value after an event */ ! 571: 574 0000BD44 _post_evt_acc: ! 572: 575 0000BD44 .long 0 ! 573: 576 0000BD44 00000000 .long 0 ! 574: 577 0000BD48 ! 575: 578 0000BD48 .globl _post_event_psl /* PSL after an FPM event */ ! 576: 579 0000BD48 _post_event_psl: ! 577: 580 0000BD48 00000000 .long 0 ! 578: 581 0000BD4C ! 579: 582 0000BD4C .globl _pre_event_fp /* frame pointer before an expected event */ ! 580: 583 0000BD4C _pre_event_fp: ! 581: 584 0000BD4C 00000000 .long 0 ! 582: 585 0000BD50 ! 583: 586 0000BD50 .globl _pre_event_sp /* stack pointer before an expected event */ ! 584: 587 0000BD50 _pre_event_sp: ! 585: 588 0000BD50 00000000 .long 0 ! 586: 589 0000BD54 ! 587: 590 0000BD54 .globl _post_event_sp /* stack pointer after an fpp event */ ! 588: 591 0000BD54 _post_event_sp: ! 589: 592 0000BD54 .long 0 ! 590: 593 0000BD54 00000000 ! 591: 594 0000BD58 /* post_event_fp is with STORE_REG */ ! 592: 595 0000BD58 ! 593: 596 0000BD58 00000000 .globl _count /* cycle count */ ! 594: 597 0000BD5C _count: .long 0 ! 595: 598 0000BD5C 00000000 ! 596: 599 0000BD60 .globl _tmp_mcbr ! 597: 600 0000BD60 _tmp_mcbr: .long 0 ! 598: 601 0000BD60 .globl _tmp_mear ! 599: 602 0000BD60 _tmp_mear: .long 0 ! 600: 603 0000BD60 ! 601: 604 0000BD60 00000000 ! 602: 605 0000BD64 00000000 ! 603: 606 0000BD68 .globl _dbl_value_1 /* 1st dbl test value */ ! 604: 607 0000BD68 _dbl_value_1: ! 605: 608 0000BD68 .long 0 ! 606: 609 0000BD68 00000000 .long 0 ! 607: 610 0000BD6C 00000000 ! 608: 611 0000BD70 .globl _dbl_value_2 /* 2nd dbl test value */ ! 609: 612 0000BD70 _dbl_value_2: ! 610: 613 0000BD70 .long 0 ! 611: 614 0000BD70 00000000 .long 0 ! 612: 615 0000BD74 00000000 ! 613: 616 0000BD78 .globl _dbl_value_3 /* 3rd dbl test value */ ! 614: 617 0000BD78 _dbl_value_3: ! 615: 618 0000BD78 .long 0 ! 616: 619 0000BD78 00000000 .long 0 ! 617: 620 0000BD7C 00000000 ! 618: 621 0000BD80 .globl _dbl_expected /* expected dbl data */ ! 619: 622 0000BD80 _dbl_expected: ! 620: 623 0000BD80 .long 0 ! 621: 624 0000BD80 00000000 .long 0 ! 622: 625 0000BD84 00000000 ! 623: 626 0000BD88 .globl _dbl_ld_acc /* load dbl acc. from here */ ! 624: 627 0000BD88 _dbl_ld_acc: ! 625: 628 0000BD88 .long 0 ! 626: 629 0000BD88 00000000 .long 0 ! 627: 630 0000BD8C 00000000 ! 628: 631 0000BD90 .globl _dbl_st_acc /* stored dbl accumulator */ ! 629: 632 0000BD90 _dbl_st_acc: ! 630: 633 0000BD90 .long 0 ! 631: 634 0000BD90 00000000 .long 0 ! 632: 635 0000BD94 00000000 ! 633: 636 0000BD98 .globl _dbl_dummy1 /* dummy quad word */ ! 634: 637 0000BD98 _dbl_dummy1: ! 635: 638 0000BD98 .long 0 ! 636: 639 0000BD98 00000000 .long 0 ! 637: 640 0000BD9C 00000000 ! 638: 641 0000BDA0 .globl _dbl_dummy2 /* ditto */ ! 639: 642 0000BDA0 _dbl_dummy2: ! 640: 643 0000BDA0 .long 0 ! 641: 644 0000BDA0 00000000 .long 0 ! 642: 645 0000BDA4 ! 643: 646 0000BDA4 .globl _sgl_value_1 /* 1st sgl data value */ ! 644: 647 0000BDA4 _sgl_value_1: ! 645: 648 0000BDA4 00000000 .long 0 ! 646: 649 0000BDA8 ! 647: 650 0000BDA8 .globl _sgl_value_2 /* 2nd sgl data value */ ! 648: 651 0000BDA8 _sgl_value_2: ! 649: 652 0000BDA8 00000000 .long 0 ! 650: 653 0000BDAC ! 651: 654 0000BDAC .globl _sgl_value_3 /* 3rd sgl data value */ ! 652: 655 0000BDAC _sgl_value_3: ! 653: 656 0000BDAC 00000000 .long 0 ! 654: 657 0000BDB0 ! 655: 658 0000BDB0 .globl _sgl_value_4 /* 4th sgl data value */ ! 656: 659 0000BDB0 _sgl_value_4: ! 657: 660 0000BDB0 00000000 .long 0 ! 658: 661 0000BDB4 ! 659: 662 0000BDB4 .globl _sgl_value_5 /* 5th sgl data value */ ! 660: 663 0000BDB4 _sgl_value_5: ! 661: 664 0000BDB4 00000000 .long 0 ! 662: 665 0000BDB8 ! 663: 666 0000BDB8 .globl _sgl_value_6 /* 6th sgl data value */ ! 664: 667 0000BDB8 _sgl_value_6: ! 665: 668 0000BDB8 00000000 .long 0 ! 666: 669 0000BDBC ! 667: 670 0000BDBC .globl _sgl_value_7 /* 7th sgl data value */ ! 668: 671 0000BDBC _sgl_value_7: ! 669: 672 0000BDBC 00000000 .long 0 ! 670: 673 0000BDC0 ! 671: 674 0000BDC0 .globl _sgl_value_8 /* 8th sgl data value */ ! 672: 675 0000BDC0 _sgl_value_8: ! 673: 676 0000BDC0 00000000 .long 0 ! 674: 677 0000BDC4 ! 675: 678 0000BDC4 .globl _sgl_value_9 /* 9th sgl data value */ ! 676: 679 0000BDC4 _sgl_value_9: ! 677: 680 0000BDC4 00000000 .long 0 ! 678: 681 0000BDC8 ! 679: 682 0000BDC8 .globl _sgl_value_10 /* 10th sgl data value */ ! 680: 683 0000BDC8 _sgl_value_10: ! 681: 684 0000BDC8 00000000 .long 0 ! 682: 685 0000BDCC ! 683: 686 0000BDCC .globl _sgl_expected /* expected sgl data */ ! 684: 687 0000BDCC _sgl_expected: ! 685: 688 0000BDCC 00000000 .long 0 ! 686: 689 0000BDD0 ! 687: 690 0000BDD0 .globl _sgl_ld_acc /* load sgl acc. from here */ ! 688: 691 0000BDD0 _sgl_ld_acc: ! 689: 692 0000BDD0 00000000 .long 0 ! 690: 693 0000BDD4 ! 691: 694 0000BDD4 .globl _sgl_st_acc /* stored sgl acc. */ ! 692: 695 0000BDD4 _sgl_st_acc: ! 693: 696 0000BDD4 00000000 .long 0 ! 694: 697 0000BDD8 ! 695: 698 0000BDD8 .globl _sgl_dummy1 /* a dummy variable */ ! 696: 699 0000BDD8 _sgl_dummy1: ! 697: 700 0000BDD8 00000000 .long 0 ! 698: 701 0000BDDC ! 699: 702 0000BDDC .globl _sgl_dummy2 /* a dummy variable, too */ ! 700: 703 0000BDDC _sgl_dummy2: ! 701: 704 0000BDDC 00000000 .long 0 ! 702: 705 0000BDE0 ! 703: 706 0000BDE0 .globl _psl_val /* PSL value */ ! 704: 707 0000BDE0 _psl_val: ! 705: 708 0000BDE0 00000000 .long 0 ! 706: 709 0000BDE4 ! 707: 710 0000BDE4 .globl _exp_psl /* expected PSL value */ ! 708: 711 0000BDE4 _exp_psl: ! 709: 712 0000BDE4 00000000 .long 0 ! 710: 713 0000BDE8 ! 711: 714 0000BDE8 .globl _init_psl /* initial PSL value */ ! 712: 715 0000BDE8 _init_psl: ! 713: 716 0000BDE8 000000ff .long 0 ! 714: 717 0000BDEC fffffff1 ! 715: 718 0000BDF0 00000000 .globl _status_array /* array of +, -, 0 data */ ! 716: 719 0000BDF4 _status_array: ! 717: 720 0000BDF4 .long 255 /* + */ ! 718: 721 0000BDF4 .long -15 /* - */ ! 719: 722 0000BDF4 00000000 .long 0 /* 0 */ ! 720: 723 0000BDF8 ! 721: 724 0000BDF8 .globl _status_index /* index to status array */ ! 722: 725 0000BDF8 _status_index: ! 723: 726 0000BDF8 00000000 .long 0 ! 724: 727 0000BDFC ! 725: 728 0000BDFC .globl _test_flags /* condition flags seen */ ! 726: 729 0000BDFC _test_flags: ! 727: 730 0000BDFC 00000000 .long 0 ! 728: 731 0000BE00 ! 729: 732 0000BE00 .globl _fpm_ms_op /* MS op on stack -FPM trap */ ! 730: 733 0000BE00 _fpm_ms_op: ! 731: 734 0000BE00 00000000 .long 0 ! 732: 735 0000BE04 ! 733: 736 0000BE04 .globl _fpm_ls_op /* LS op on stack -FPM trap */ ! 734: 737 0000BE04 _fpm_ls_op: ! 735: 738 0000BE04 00000000 .long 0 ! 736: 739 0000BE08 ! 737: 740 0000BE08 .globl _fpm_op_code /* stack's op-code -FPM trap */ ! 738: 741 0000BE08 _fpm_op_code: ! 739: 742 0000BE08 00000000 .long 0 ! 740: 743 0000BE0C ! 741: 744 0000BE0C .globl _fpm_pc /* stack's PC -FPM trap */ ! 742: 745 0000BE0C _fpm_pc: ! 743: 746 0000BE0C 00000000 .long 0 ! 744: 747 0000BE10 ! 745: 748 0000BE10 .globl _fpm_psl /* stack's PSL -FPM trap */ ! 746: 749 0000BE10 _fpm_psl: ! 747: 750 0000BE10 00000000 .long 0 ! 748: 751 0000BE14 ! 749: 752 0000BE14 .globl _rtc_occurred /* flag -clock event seen */ ! 750: 753 0000BE14 _rtc_occurred: ! 751: 754 0000BE14 00000000 .long 0 ! 752: 755 0000BE18 ! 753: 756 0000BE18 .globl _clock_retrys /* # times to wait for clock */ ! 754: 757 0000BE18 _clock_retrys: ! 755: 758 0000BE18 00000000 .long 0 ! 756: 759 0000BE1C ! 757: 760 0000BE1C .globl _pop_val_1 /* 1st popped stack data */ ! 758: 761 0000BE1C _pop_val_1: ! 759: 762 0000BE1C 00000000 .long 0 ! 760: 763 0000BE20 ! 761: 764 0000BE20 .globl _pop_val_2 /* 2nd popped stack data */ ! 762: 765 0000BE20 _pop_val_2: ! 763: 766 0000BE20 00000000 .long 0 ! 764: 767 0000BE24 ! 765: 768 0000BE24 .globl _pop_val_3 /* 3rd popped stack data */ ! 766: 769 0000BE24 _pop_val_3: ! 767: 770 0000BE24 00000000 .long 0 ! 768: 771 0000BE28 ! 769: 772 0000BE28 .globl _pop_val_4 /* 4th popped stack data */ ! 770: 773 0000BE28 _pop_val_4: ! 771: 774 0000BE28 00000000 .long 0 ! 772: 775 0000BE2C ! 773: 776 0000BE2C .globl _pop_val_5 /* 5th popped stack data */ ! 774: 777 0000BE2C _pop_val_5: ! 775: 778 0000BE2C 00000000 .long 0 ! 776: 779 0000BE30 ! 777: 780 0000BE30 .globl _pop_val_6 /* 6th popped stack data */ ! 778: 781 0000BE30 _pop_val_6: ! 779: 782 0000BE30 00000000 .long 0 ! 780: 783 0000BE34 ! 781: 784 0000BE34 .globl _exp_pc /* expected PC */ ! 782: 785 0000BE34 _exp_pc: ! 783: 786 0000BE34 00000000 .long 0 ! 784: 787 0000BE38 ! 785: 788 0000BE38 .globl _act_pc /* actual PC */ ! 786: 789 0000BE38 _act_pc: ! 787: 790 0000BE38 00000000 .long 0 ! 788: 791 0000BE3C ! 789: 792 0000BE3C .globl _op_code /* op-code of the inst. */ ! 790: 793 0000BE3C _op_code: ! 791: 794 0000BE3C 00000000 .long 0 ! 792: 795 0000BE40 ! 793: 796 0000BE40 .globl _op_name /* instruction name */ ! 794: 797 0000BE40 _op_name: ! 795: 798 0000BE40 00000000 .long 0 ! 796: 799 0000BE44 ! 797: 800 0000BE44 .globl _precision /* sgl / dbl precision inst */ ! 798: 801 0000BE44 _precision: ! 799: 802 0000BE44 00000000 .long 0 ! 800: 803 0000BE48 ! 801: 804 0000BE48 .globl _acc_ld_size /* sgl or dbl acc. loaded */ ! 802: 805 0000BE48 _acc_ld_size: ! 803: 806 0000BE48 00000000 .long 0 ! 804: 807 0000BE4C ! 805: 808 0000BE4C .globl _acc_st_size /* sgl or dbl acc. stored */ ! 806: 809 0000BE4C _acc_st_size: ! 807: 810 0000BE4C 00000000 .long 0 ! 808: 811 0000BE50 ! 809: 812 0000BE50 .globl _no_ops /* # of operands needed */ ! 810: 813 0000BE50 _no_ops: ! 811: 814 0000BE50 00000000 .long 0 ! 812: 815 0000BE54 ! 813: 816 0000BE54 .globl _op_type /* load / store operand */ ! 814: 817 0000BE54 _op_type: ! 815: 818 0000BE54 00000000 .long 0 ! 816: 819 0000BE58 ! 817: 820 0000BE58 .globl _load_type_inst /* flag -inst loads the Acc */ ! 818: 821 0000BE58 _load_type_inst: ! 819: 822 0000BE58 00000000 .long 0 ! 820: 823 0000BE5C ! 821: 824 0000BE5C .globl _sgl_op /* inst has sgl operand(s) */ ! 822: 825 0000BE5C _sgl_op: ! 823: 826 0000BE5C 00000000 .long 0 ! 824: 827 0000BE60 ! 825: 828 0000BE60 .globl _s_to_d /* inst converts sgl to dbl */ ! 826: 829 0000BE60 _s_to_d: ! 827: 830 0000BE60 00000000 .long 0 ! 828: 831 0000BE64 ! 829: 832 0000BE64 .globl _d_to_s /* inst converts dbl to sgl */ ! 830: 833 0000BE64 _d_to_s: ! 831: 834 0000BE64 00000000 .long 0 ! 832: 835 0000BE68 ! 833: 836 0000BE68 .globl _valid_test /* flag -some tests were run */ ! 834: 837 0000BE68 _valid_test: ! 835: 838 0000BE68 00000000 .long 0 ! 836: 839 0000BE6C ! 837: 840 0000BE6C .globl _insts_tested /* # of instructions tested */ ! 838: 841 0000BE6C _insts_tested: ! 839: 842 0000BE6C 00000000 .long 0 ! 840: 843 0000BE70 ! 841: 844 0000BE70 .globl _force_sp /* flag to set the SP value */ ! 842: 845 0000BE70 _force_sp: ! 843: 846 0000BE70 00000000 .long 0 ! 844: 847 0000BE74 ! 845: 848 0000BE74 .globl _data_ptr /* ptr to dmp test data tbl */ ! 846: 849 0000BE74 _data_ptr: ! 847: 850 0000BE74 00000000 .long 0 ! 848: 851 0000BE78 ! 849: 852 0000BE78 .globl _test_ptr /* ptr to result test func. */ ! 850: 853 0000BE78 _test_ptr: ! 851: 854 0000BE78 00000000 .long 0 ! 852: 855 0000BE7C ! 853: 856 0000BE7C .globl _no_page_faults /* # addr page faults found */ ! 854: 857 0000BE7C _no_page_faults: ! 855: 858 0000BE7C 00000000 .long 0 ! 856: 859 0000BE80 ! 857: 860 0000BE80 .globl _exp_page_faults /* # addr page faults exp'd */ ! 858: 861 0000BE80 _exp_page_faults: ! 859: 862 0000BE80 00000000 .long 0 ! 860: 863 0000BE84 ! 861: 864 0000BE84 .globl _trans_acc_error /* flag -bad Acc after pg flt */ ! 862: 865 0000BE84 _trans_acc_error: ! 863: 866 0000BE84 00000000 .long 0 ! 864: 867 0000BE88 00000000 ! 865: 868 0000BE8C .globl _trans_acc /* Acc. after a page fault */ ! 866: 869 0000BE8C _trans_acc: ! 867: 870 0000BE8C .long 0 ! 868: 871 0000BE8C 00000000 .long 0 ! 869: 872 0000BE90 00000000 ! 870: 873 0000BE94 .globl _exp_trans_acc /* Acc. expected after fault */ ! 871: 874 0000BE94 _exp_trans_acc: ! 872: 877 0000BE94 .long 0 ! 873: 878 0000BE94 .long 0 ! 874: 879 0000BE94 00000040 ! 875: 880 0000BE98 /* ! 876: 881 0000BE98 * OFFSETS FROM THE CODE BUFFER TO THE DMP DATA OPERANDS ! 877: 882 0000BE98 */ ! 878: 883 0000BE98 00000060 .globl _os_b_op1 /* offset to byte operand 1 */ ! 879: 884 0000BE9C _os_b_op1: ! 880: 885 0000BE9C .long _dmp_byte_op_1-DMP_PG_1 ! 881: 886 0000BE9C ! 882: 887 0000BE9C 00000080 .globl _os_b_op2 /* offset to byte operand 2 */ ! 883: 888 0000BEA0 _os_b_op2: ! 884: 889 0000BEA0 .long _dmp_byte_op_2-DMP_PG_1 ! 885: 890 0000BEA0 ! 886: 891 0000BEA0 000007fc .globl _os_b_op3 /* offset to byte operand 3 */ ! 887: 892 0000BEA4 _os_b_op3: ! 888: 893 0000BEA4 .long _dmp_byte_op_3-DMP_PG_1 ! 889: 894 0000BEA4 ! 890: 895 0000BEA4 000017fc .globl _os_op1 /* offset to word operand 1 */ ! 891: 896 0000BEA8 _os_op1: ! 892: 897 0000BEA8 .long _dmp_op_1-DMP_PG_1 ! 893: 898 0000BEA8 ! 894: 899 0000BEA8 00001c00 .globl _os_op2 /* offset to word operand 2 */ ! 895: 900 0000BEAC _os_op2: ! 896: 901 0000BEAC .long _dmp_op_2-DMP_PG_1 ! 897: 902 0000BEAC ! 898: 903 0000BEAC 00000c30 .globl _os_op3 /* offset to word operand 3 */ ! 899: 904 0000BEB0 _os_op3: ! 900: 905 0000BEB0 .long _dmp_op_3-DMP_PG_1 ! 901: 906 0000BEB0 ! 902: 907 0000BEB0 00001030 .globl _os_ad_op1 /* offset to operand 1 ptr. */ ! 903: 908 0000BEB4 _os_ad_op1: ! 904: 909 0000BEB4 .long _dmp_op_1_ptr-DMP_PG_1 ! 905: 910 0000BEB4 ! 906: 911 0000BEB4 00002030 .globl _os_ad_op2 /* offset to operand 2 ptr. */ ! 907: 912 0000BEB8 _os_ad_op2: ! 908: 913 0000BEB8 .long _dmp_op_2_ptr-DMP_PG_1 ! 909: 914 0000BEB8 ! 910: 917 0000BEB8 .globl _os_ad_op3 /* offset to operand 3 ptr. */ ! 911: 918 0000BEB8 _os_ad_op3: ! 912: 919 0000BEB8 00036440 .long _dmp_op_3_ptr-DMP_PG_1 ! 913: 920 0000BEBC ! 914: 921 0000BEBC ! 915: 922 0000BEBC /* ! 916: 923 0000BEBC 00036444 * Pointers to the Demand Paging Data Operands ! 917: 924 0000BEC0 */ ! 918: 925 0000BEC0 .globl _adr_b_op1 /* byte operand 1's address */ ! 919: 926 0000BEC0 _adr_b_op1: ! 920: 927 0000BEC0 00036460 .long _dmp_byte_op_1 ! 921: 928 0000BEC4 ! 922: 929 0000BEC4 .globl _adr_bop1_lsw /* addr of byte op 1's LSW */ ! 923: 930 0000BEC4 _adr_bop1_lsw: ! 924: 931 0000BEC4 00036464 .long _dmp_byte_op_1+4 ! 925: 932 0000BEC8 ! 926: 933 0000BEC8 .globl _adr_b_op2 /* byte operand 2's address */ ! 927: 934 0000BEC8 _adr_b_op2: ! 928: 935 0000BEC8 00036480 .long _dmp_byte_op_2 ! 929: 936 0000BECC ! 930: 937 0000BECC .globl _adr_bop2_lsw /* addr of byte op 2's LSW */ ! 931: 938 0000BECC _adr_bop2_lsw: ! 932: 939 0000BECC 00036bfc .long _dmp_byte_op_2+4 ! 933: 940 0000BED0 ! 934: 941 0000BED0 .globl _adr_b_op3 /* byte operand 3's address */ ! 935: 942 0000BED0 _adr_b_op3: ! 936: 943 0000BED0 00036c00 .long _dmp_byte_op_3 ! 937: 944 0000BED4 ! 938: 945 0000BED4 .globl _adr_op1 /* operand 1's address */ ! 939: 946 0000BED4 _adr_op1: ! 940: 947 0000BED4 00037bfc .long _dmp_op_1 ! 941: 948 0000BED8 ! 942: 949 0000BED8 .globl _adr_op1_lsw /* address of LSW of dbl op 1 */ ! 943: 950 0000BED8 _adr_op1_lsw: ! 944: 951 0000BED8 00037c00 .long _dmp_op_1+4 ! 945: 952 0000BEDC ! 946: 953 0000BEDC .globl _adr_op2 /* operand 2's address */ ! 947: 954 0000BEDC _adr_op2: ! 948: 955 0000BEDC 00038000 .long _dmp_op_2 ! 949: 956 0000BEE0 ! 950: 957 0000BEE0 .globl _adr_op2_lsw /* address of LSW of dbl op 2 */ ! 951: 958 0000BEE0 _adr_op2_lsw: ! 952: 959 0000BEE0 00038800 .long _dmp_op_2+4 ! 953: 960 0000BEE4 ! 954: 961 0000BEE4 .globl _adr_op3 /* operand 3's address */ ! 955: 962 0000BEE4 _adr_op3: ! 956: 963 0000BEE4 00038c00 .long _dmp_op_3 ! 957: 964 0000BEE8 ! 958: 965 0000BEE8 .globl _adr_op4 /* operand 4's address */ ! 959: 966 0000BEE8 _adr_op4: ! 960: 967 0000BEE8 00037030 .long _dmp_op_4 ! 961: 968 0000BEEC ! 962: 969 0000BEEC .globl _adr_op5 /* operand 5's address */ ! 963: 970 0000BEEC _adr_op5: ! 964: 971 0000BEEC 00038430 .long _dmp_op_5 ! 965: 972 0000BEF0 ! 966: 973 0000BEF0 .globl _adr_op1_ptr /* op. ptr 1's address */ ! 967: 974 0000BEF0 _adr_op1_ptr: ! 968: 975 0000BEF0 00037430 .long _dmp_op_1_ptr ! 969: 976 0000BEF4 ! 970: 977 0000BEF4 .globl _adr_op3_ptr /* op. ptr 3's address */ ! 971: 978 0000BEF4 _adr_op3_ptr: ! 972: 979 0000BEF4 00000000 .long _dmp_op_3_ptr ! 973: 980 0000BEF8 ! 974: 981 0000BEF8 .globl _adr_op2_ptr /* op. ptr 2's address */ ! 975: 982 0000BEF8 _adr_op2_ptr: ! 976: 983 0000BEF8 00000000 .long _dmp_op_2_ptr ! 977: 984 0000BEFC ! 978: 985 0000BEFC .globl _reg_no /* register being validated */ ! 979: 986 0000BEFC _reg_no: ! 980: 987 0000BEFC 00000000 .long 0 ! 981: 988 0000BF00 ! 982: 989 0000BF00 .globl _regs_ok /* flag -no reg. miscompares*/ ! 983: 990 0000BF00 _regs_ok: ! 984: 991 0000BF00 00000000 .long 0 ! 985: 992 0000BF04 ! 986: 993 0000BF04 .globl _exp_reg /* expected reg. value */ ! 987: 994 0000BF04 _exp_reg: ! 988: 995 0000BF04 00000000 .long 0 ! 989: 996 0000BF08 ! 990: 997 0000BF08 .globl _act_reg /* actual register value */ ! 991: 998 0000BF08 _act_reg: ! 992: 999 0000BF08 00000000 .long 0 ! 993: 1000 0000BF0C ! 994: 1001 0000BF0C .globl _test_index /* test table index */ ! 995: 1002 0000BF0C _test_index: ! 996: 1003 0000BF0C 00000000 .long 0 ! 997: 1004 0000BF10 ! 998: 1005 0000BF10 .globl _inst_index /* instruction table index */ ! 999: 1006 0000BF10 _inst_index: ! 1000: 1007 0000BF10 00000000 .long 0 ! 1001: 1008 0000BF14 ! 1002: 1009 0000BF14 .globl _index /* test data index */ ! 1003: 1010 0000BF14 _index: ! 1004: 1011 0000BF14 00000000 .long 0 ! 1005: 1012 0000BF18 ! 1006: 1013 0000BF18 .globl _index2 /* test data index # 2 */ ! 1007: 1014 0000BF18 _index2: ! 1008: 1015 0000BF18 00000000 .long 0 ! 1009: 1016 0000BF1C ! 1010: 1017 0000BF1C .globl _old_indx /* test data index (-1) */ ! 1011: 1018 0000BF1C _old_indx: ! 1012: 1019 0000BF1C 40800000 .long 0 ! 1013: 1020 0000BF20 ! 1014: 1021 0000BF20 .globl _max_index /* maximum data index */ ! 1015: 1022 0000BF20 _max_index: ! 1016: 1023 0000BF20 40800000 .long 0 ! 1017: 1024 0000BF24 ! 1018: 1025 0000BF24 .globl _loop_val_1a /* op_1 MSW for data swaps */ ! 1019: 1026 0000BF24 _loop_val_1a: ! 1020: 1027 0000BF24 40800000 .long 0x40800000 ! 1021: 1028 0000BF28 ! 1022: 1029 0000BF28 .globl _loop_val_1b /* op_1 MSW for data swaps */ ! 1023: 1030 0000BF28 _loop_val_1b: ! 1024: 1031 0000BF28 40800000 .long 0x40800000 ! 1025: 1032 0000BF2C ! 1026: 1033 0000BF2C .globl _loop_val_1c /*op_1 LSW for data swaps */ ! 1027: 1034 0000BF2C _loop_val_1c: ! 1028: 1035 0000BF2C 40800000 .long 0x40800000 ! 1029: 1036 0000BF30 ! 1030: 1037 0000BF30 .globl _loop_val_1d /* op_1 LSW for data swaps */ ! 1031: 1038 0000BF30 _loop_val_1d: ! 1032: 1039 0000BF30 40800000 .long 0x40800000 ! 1033: 1040 0000BF34 ! 1034: 1041 0000BF34 .globl _loop_val_2a /* op_2 MSW for data swaps */ ! 1035: 1042 0000BF34 _loop_val_2a: ! 1036: 1043 0000BF34 40800000 .long 0x40800000 ! 1037: 1044 0000BF38 ! 1038: 1045 0000BF38 .globl _loop_val_2b /* op_2 MSW for data swaps */ ! 1039: 1046 0000BF38 _loop_val_2b: ! 1040: 1047 0000BF38 40800000 .long 0x40800000 ! 1041: 1048 0000BF3C ! 1042: 1049 0000BF3C .globl _loop_val_2c /* op_2 LSW for data swaps */ ! 1043: 1050 0000BF3C _loop_val_2c: ! 1044: 1051 0000BF3C 00000000 .long 0x40800000 ! 1045: 1052 0000BF40 ! 1046: 1053 0000BF40 .globl _loop_val_2d /* op_2 LSW for data swaps */ ! 1047: 1054 0000BF40 _loop_val_2d: ! 1048: 1055 0000BF40 00000000 .long 0x40800000 ! 1049: 1056 0000BF44 ! 1050: 1057 0000BF44 .globl _error /* an error exists flag */ ! 1051: 1058 0000BF44 _error: ! 1052: 1059 0000BF44 00000000 .long 0 ! 1053: 1060 0000BF48 ! 1054: 1061 0000BF48 .globl _err_code /* code ( type ) of error */ ! 1055: 1062 0000BF48 _err_code: ! 1056: 1063 0000BF48 00000000 .long 0 ! 1057: 1064 0000BF4C ! 1058: 1065 0000BF4C .globl _subtest_message /* pointer to test message */ ! 1059: 1066 0000BF4C _subtest_message: ! 1060: 1067 0000BF4C **** .long 0 ! 1061: 1068 0000BF88 ! 1062: 1069 0000BF88 .globl _error_message /* pointer to error message */ ! 1063: 1070 0000BF88 _error_message: ! 1064: 1071 0000BF88 **** .long 0 ! 1065: 1072 0000BFC4 ! 1066: 1073 0000BFC4 .globl _load_regs /* load registers' buffer */ ! 1067: 1074 0000BFC4 _load_regs: ! 1068: 1075 0000BFC4 **** .space (15*4) ! 1069: 1076 0000C000 ! 1070: 1077 0000C000 .globl _store_regs /* store registers' buffer */ ! 1071: 1078 0000C000 _store_regs: ! 1072: 1079 0000C000 00000000 .space (15*4) ! 1073: 1080 0000C004 ! 1074: 1081 0000C004 .globl _exp_regs /* expected register data */ ! 1075: 1082 0000C004 _exp_regs: ! 1076: 1083 0000C004 .space (15*4) ! 1077: 1084 0000C004 00000000 ! 1078: 1085 0000C008 .globl _post_event_fp /* frame pointer storage */ ! 1079: 1086 0000C008 _post_event_fp: /* (must follow store_reg */ ! 1080: 1087 0000C008 .long 0 ! 1081: 1088 0000C008 00000000 ! 1082: 1089 0000C00C ! 1083: 1090 0000C00C .globl _address_fault_expected /* reserved-address fault? */ ! 1084: 1091 0000C00C _address_fault_expected: ! 1085: 1092 0000C00C 00000000 .long 0 ! 1086: 1093 0000C010 ! 1087: 1094 0000C010 .globl _loop_addr /* for addr test looping */ ! 1088: 1095 0000C010 _loop_addr: ! 1089: 1096 0000C010 00000000 .long 0 ! 1090: 1097 0000C014 ! 1091: 1098 0000C014 .globl _next_addr /* for address testing */ ! 1092: 1099 0000C014 _next_addr: ! 1093: 1100 0000C014 00000000 .long 0 ! 1094: 1101 0000C018 ! 1095: 1102 0000C018 .globl _addr_mode /* current addressing mode */ ! 1096: 1103 0000C018 _addr_mode: ! 1097: 1104 0000C018 00000000 .long 0 ! 1098: 1105 0000C01C ! 1099: 1106 0000C01C .globl _addr_code /* code for addressing mode */ ! 1100: 1107 0000C01C _addr_code: ! 1101: 1108 0000C01C 00000000 .long 0 ! 1102: 1109 0000C020 ! 1103: 1110 0000C020 .globl _addr_code2 /* addr code for 2nd operand */ ! 1104: 1111 0000C020 _addr_code2: ! 1105: 1112 0000C020 00000000 .long 0 ! 1106: 1113 0000C024 ! 1107: 1114 0000C024 .globl _addr_code3 /* addr code for 3rd operand */ ! 1108: 1115 0000C024 _addr_code3: ! 1109: 1116 0000C024 00000000 .long 0 ! 1110: 1117 0000C028 ! 1111: 1118 0000C028 .globl _addr_codeB /* 2nd adr code for indexing */ ! 1112: 1119 0000C028 _addr_codeB: ! 1113: 1120 0000C028 00000000 .long 0 ! 1114: 1121 0000C02C ! 1115: 1122 0000C02C .globl _addr_code_p1 /* addr code for pipelines */ ! 1116: 1123 0000C02C _addr_code_p1: ! 1117: 1124 0000C02C 00000000 .long 0 ! 1118: 1125 0000C030 ! 1119: 1126 0000C030 .globl _addr_code_p2 /* addr code for pipelines */ ! 1120: 1127 0000C030 _addr_code_p2: ! 1121: 1128 0000C030 00000000 .long 0 ! 1122: 1129 0000C034 ! 1123: 1130 0000C034 .globl _inst_size /* # of bytes in instruction */ ! 1124: 1131 0000C034 _inst_size: ! 1125: 1132 0000C034 00000000 .long 0 ! 1126: 1133 0000C038 ! 1127: 1134 0000C038 .globl _shift_count /* inst_buf shift count */ ! 1128: 1135 0000C038 _shift_count: ! 1129: 1136 0000C038 00000000 .long 0 ! 1130: 1137 0000C03C ! 1131: 1138 0000C03C .globl _min_shift /* minimum inst_buf shift */ ! 1132: 1139 0000C03C _min_shift: ! 1133: 1140 0000C03C 00000000 .long 0 ! 1134: 1141 0000C040 ! 1135: 1142 0000C040 .globl _addr_size /* size of addr specifier(s)*/ ! 1136: 1143 0000C040 _addr_size: ! 1137: 1144 0000C040 00000000 .long 0 ! 1138: 1145 0000C044 ! 1139: 1146 0000C044 .globl _addr_1 /* address specifier # 1 */ ! 1140: 1147 0000C044 _addr_1: ! 1141: 1148 0000C044 00000000 .long 0 ! 1142: 1149 0000C048 ! 1143: 1150 0000C048 .globl _addr_2 /* address specifier # 2 */ ! 1144: 1151 0000C048 _addr_2: ! 1145: 1152 0000C048 **** .long 0 ! 1146: 1153 0000C05C ! 1147: 1154 0000C05C .globl _addr_3 /* address specifier # 3 */ ! 1148: 1155 0000C05C _addr_3: ! 1149: 1156 0000C05C .long 0 ! 1150: 1157 0000C05C ! 1151: 1158 0000C05C 00000000 .globl _inst_buf /* instruction code buffer */ ! 1152: 1159 0000C060 _inst_buf: ! 1153: 1160 0000C060 .space 20 /* 20 bytes (5 longwords) */ ! 1154: 1161 0000C060 .globl _end_of_inst_buf ! 1155: 1162 0000C060 _end_of_inst_buf: ! 1156: 1163 0000C060 ! 1157: 1166 0000C060 .globl _code_addr /* start of test code */ ! 1158: 1167 0000C060 _code_addr: ! 1159: 1168 0000C060 .long 0 ! 1160: 1169 0000C060 00000000 ! 1161: 1170 0000C064 ! 1162: 1171 0000C064 ! 1163: 1172 0000C064 ! 1164: 1173 0000C064 00000000 /* ! 1165: 1174 0000C068 * exaustive test data ! 1166: 1175 0000C068 */ ! 1167: 1176 0000C068 ! 1168: 1177 0000C068 00000000 .globl _fudgeing_ok /* +/- 1 answer is OK */ ! 1169: 1178 0000C06C _fudgeing_ok: ! 1170: 1179 0000C06C **** .long 0 ! 1171: 1180 0000C1AC 00000000 ! 1172: 1181 0000C1B0 .globl _not_done /* keep testing flag */ ! 1173: 1182 0000C1B0 _not_done: ! 1174: 1183 0000C1B0 00000000 .long 0 ! 1175: 1184 0000C1B4 ! 1176: 1185 0000C1B4 .globl _use_ITT_data /* use ITT type fractions */ ! 1177: 1186 0000C1B4 00000000 _use_ITT_data: ! 1178: 1187 0000C1B8 **** .long 0 ! 1179: 1188 0000055c * ! 1180: 1189 0000055c * .space (80*4) /* room for 40 stack entries */ ! 1181: 1189 0000055c * .space (80*4) /* room for 40 stack entries */
This archive runs on limited infrastructure. Preserving old code on modern bandwidth. Automated agents are requested to crawl responsibly.