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Up to [Power 6/32 Unix Tahoe 4.2BSD] / cci / d / macro4|
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Power 6/32 Unix version 1.21
1 00000000 2 00000000 /* privileged registers constants (addresses) */ 3 00000000 4 00000000 5 00000000 6 00000000 .set SBR,0 /*system base register */ 7 00000000 .set SLR,1 /*system length reg */ 8 00000000 .set P0BR,2 /*p0 base reg */ 9 00000000 .set P0LR,3 /*p0 length reg */ 10 00000000 .set P1BR,4 /*p1 base reg */ 11 00000000 .set P1LR,5 /*p1 length reg */ 12 00000000 .set P2BR,6 /*p2 base reg */ 13 00000000 .set P2LR,7 /*p2 length reg */ 14 00000000 .set IPL,8 /*int priority level reg */ 15 00000000 .set MME,9 /*memory mgmt enable reg */ 16 00000000 .set TBIA,10 /*trans buf invalidate all */ 17 00000000 /*entries */ 18 00000000 .set TBIS,11 /*trans buf invalidate single */ 19 00000000 /*entry */ 20 00000000 .set DCK,12 /*data cache key */ 21 00000000 .set CCK,13 /*code cache key */ 22 00000000 .set PCBB,14 /*process control block base */ 23 00000000 .set ISP,15 /*interrupt stack pointer */ 24 00000000 .set SIRR,16 /*software int request reg */ 25 00000000 .set SISR,17 /*software int summary reg */ 26 00000000 .set SCBB,18 /*system control block base reg */ 27 00000000 .set KSP,19 /*kernel stack pointer reg */ 28 00000000 .set USP,20 /*user stack pointer */ 29 00000000 .set DCB,21 /*CPU2 DCB */ 30 00000000 .set PACC,23 /*purge (invalidate) all pages */ 31 00000000 /*of process in code cache */ 32 00000000 .set P1DC,24 /*purge one page of data cache */ 33 00000000 .set PADC,25 /*purge all the pages of */ 34 00000000 /*process in data cache */ 35 00000000 .set HISR,26 /* Hardware interrupt summary reg */ 36 00000000 .set DCR,27 /* Diagnostic control register */ 37 00000000 .set PDCS,28 /* Purge 1 data cache slot */ 38 00000000 39 00000000 # 40 00000000 #TAHOE program status longword 41 00000000 # 42 00000000 43 00000000 .set PSL_C,0x00000001 /* carry bit */ 44 00000000 .set PSL_V,0x00000002 /* overflow bit */ 45 00000000 .set PSL_Z,0x00000004 /* zero bit */ 46 00000000 .set Z,0x00000004 47 00000000 .set PSL_N,0x00000008 /* negative bit */ 48 00000000 .set PSL_T,0x00000010 /* trace enable bit */ 49 00000000 .set PSL_I,0x00000020 /* integer overflow enable bit */ 50 00000000 .set PSL_EN_OVFL,0x20 /* integer overflow enable bit */ 51 00000000 .set PSL_EN_UNDFL,0x40 /* floating underflow enable */ 52 00000000 .set PSL_DBL,0x80 /* dbl precision Accumulator bit */ 53 00000000 .set PSL_IPL,0x001f0000 /* interrupt priority level */ 54 00000000 .set PSL_MOD,0x01000000 /* mode = 1 means user */ 55 00000000 .set PSL_IS,0x04000000 /* interrupt stack */ 56 00000000 .set PSL_TP,0x40000000 /* trace pending */ 57 00000000 58 00000000 # 59 00000000 # TAHOE page table entry 60 00000000 #/ 61 00000000 .set PG_V,0x8000000 62 00000000 .set PG_PROT,0x78000000 63 00000000 .set PG_M,0x04000000 64 00000000 .set PG_USED,0x02000000 65 00000000 .set PG_NC,0x01000000 66 00000000 .set PG_PFNUM,0x003fffff 67 00000000 68 00000000 .set PG_NOACC,0 69 00000000 .set PG_KR,0x40000000 70 00000000 .set PG_KW,0x60000000 71 00000000 .set PG_URKR,0x50000000 72 00000000 .set PG_URKW,0x70000000 73 00000000 .set PG_UW,0x78000000 74 00000000 75 00000000 #* PCB offsets & diagnostic extension to pcb */ 76 00000000 #* PCB is at pcb0 */ 77 00000000 78 00000000 79 00000000 .set PCB_SIZE, 24 80 00000000 .set PCB_KSP, 0 81 00000000 .set PCB_USP, 4 82 00000000 .set PCB_R0, 8 83 00000000 .set PCB_R1, 12 84 00000000 .set PCB_R2, 16 85 00000000 .set PCB_R3, 20 86 00000000 .set PCB_R4, 24 87 00000000 .set PCB_R5, 28 88 00000000 .set PCB_R6, 32 89 00000000 .set PCB_R7, 36 90 00000000 .set PCB_R8, 40 91 00000000 .set PCB_R9, 44 92 00000000 .set PCB_R10, 48 93 00000000 .set PCB_R11, 52 94 00000000 .set PCB_R12, 56 95 00000000 .set PCB_R13, 60 96 00000000 .set PCB_PC, 64 97 00000000 .set PCB_PSL, 68 98 00000000 .set PCB_P0BR, 72 99 00000000 .set PCB_P0LR, 76 100 00000000 .set PCB_P1BR, 80 101 00000000 .set PCB_P1LR, 84 102 00000000 .set PCB_P2BR, 88 103 00000000 .set PCB_P2LR, 92 104 00000000 .set PCB_ACCM, 96 105 00000000 .set PCB_ACCL, 100 106 00000000 #* 107 00000000 # Diagnostic pcb extension 108 00000000 #/ 109 00000000 .set PCB_STAT, 104 /*process status,statistics,id,etc*/ 110 00000000 111 00000000 112 00000000 113 00000000 #* fundamental constants */ 114 00000000 115 00000000 #* 116 00000000 # fundamental constants of the implementation-- 117 00000000 # cannot be changed easily. 118 00000000 #/ 119 00000000 120 00000000 .set NBPG,1024 121 00000000 .set PGOFSET,(NBPG-1) /* byte offset into page */ 122 00000000 .set PGSHIFT,10 /* LOG2(NBPG) */ 123 00000000 .set HIGH,0x1f 124 00000000 125 00000000 126 00000000 #* SCB offsets */ 127 00000000 #* SCB is at scb */ 128 00000000 129 00000000 .set PFVEC,1*4 /*power fail */ 130 00000000 .set PRVEC,2*4 /*power restore */ 131 00000000 .set CLOCKVEC,7*4 /*hard clock vector */ 132 00000000 .set CRVEC,0xa*4 /*console receive */ 133 00000000 .set CXVEC,44 /*console transmit */ 134 00000000 .set SIVEC1,0x1e*4 /*software int vec #1 */ 135 00000000 /*for 2,3,..15, sub 4,8,.. 56 */ 136 00000000 /*from SIVEC1 */ 137 00000000 .set BEVEC,0x20*4 /*bus error */ 138 00000000 .set SYSVEC,0x2b*4 /*system call (kcall) */ 139 00000000 .set PINSTVEC,0x2c*4 /*privileged instruction fault */ 140 00000000 .set PRIVSVEC,0x2c*4 /*privileged instruction fault */ 141 00000000 .set ROVEC,0x2d*4 /*reserved operand fault */ 142 00000000 .set RAVEC,0x2e*4 /*reserved addressing fault */ 143 00000000 .set PROTVEC,0x2f*4 /*access control violation */ 144 00000000 .set TRANS,0x30 /*translation fault vector */ 145 00000000 .set TRANSVEC,0x30*4 /*translation fault vector */ 146 00000000 .set KSPVEC,0x31*4 /*kernel stack not valid vector */ 147 00000000 .set TRACEVEC,0x32*4 /*trace vector */ 148 00000000 .set BPTVEC,0x33*4 /*break point fault */ 149 00000000 .set ARITHVEC,0x34*4 /*arithmetic trap */ 150 00000000 .set ALIGNVEC,0x35*4 /*alignment vector */ 151 00000000 .set FPMVEC,0x37*4 /*fpp emulation vector */ 152 00000000 .set IO14VEC,256 /*io vector, ipl #14 */ 153 00000000 .set IO15VEC,320 /*io vector, ipl #15 */ 154 00000000 .set IO16VEC,384 /*io vector, ipl #16 */ 155 00000000 .set IO17VEC,448 /*io vector, ipl #17 */ 156 00000000 157 00000000 #* SPT (system page table) offsets */ 158 00000000 #* SPT is at Sysmap */ 159 00000000 160 00000000 .set SCBPTE,8 /*system control block pte offset*/ 161 00000000 .set BUFPTE,12 /*buffer pte offset */ 162 00000000 .set ISPTE,16 /*interrupt stack page 0 */ 163 00000000 .set IS1PTE,20 /*interrupt stack page 1 */ 164 00000000 .set SPTPTE,20 /*system page table page 1 */ 165 00000000 .set SPT1PTE,20 /*system page table page 2 */ 166 00000000 .set IOMAPPTE,24 /*io map */ 167 00000000 .set PCBPTE,28 /*process control blocks pte */ 168 00000000 .set U0P0PTE,32 /*U0 p0pt pte */ 169 00000000 .set U0P1PTE,36 /*U0 p1pt pte */ 170 00000000 .set U0P2PTE,40 /*U0 p2pt pte */ 171 00000000 .set U1P0PTE,44 172 00000000 .set U1P1PTE,48 173 00000000 .set U1P2PTE,52 174 00000000 .set U2P0PTE,56 175 00000000 .set U2P1PTE,60 176 00000000 .set U2P2PTE,64 177 00000000 .set U3P0PTE,68 178 00000000 .set U3P1PTE,72 179 00000000 .set U3P2PTE,76 180 00000000 .set U4P0PTE,80 181 00000000 .set U4P1PTE,84 182 00000000 .set U4P2PTE,88 183 00000000 .set U5P0PTE,92 184 00000000 .set U5P1PTE,96 185 00000000 .set U5P2PTE,100 186 00000000 .set U6P0PTE,104 187 00000000 .set U6P1PTE,108 188 00000000 .set U6P2PTE,112 189 00000000 .set U7P0PTE,116 /*U7 p0pt pte */ 190 00000000 .set U7P1PTE,120 /*U7 p1pt pte */ 191 00000000 .set U7P2PTE,124 /*U7 p2pt pte */ 192 00000000 .set IOB0PTE,128 /*io buffer 0 pte */ 193 00000000 .set IOB1PTE,132 194 00000000 .set IOB2PTE,136 195 00000000 .set IOB3PTE,140 196 00000000 .set IOB4PTE,144 197 00000000 .set IOB5PTE,148 198 00000000 .set IOB6PTE,152 199 00000000 .set IOB7PTE,156 /*io buffer 7 pte */ 200 00000000 201 00000000 202 00000000 #* trap.h 4.6 81/03/03 */ 203 00000000 204 00000000 #* 205 00000000 #* Trap type values 206 00000000 #/ 207 00000000 208 00000000 .set RESADFLT,0 /* reserved addressing fault */ 209 00000000 .set PRIVINFLT,1 /* privileged instruction fault */ 210 00000000 .set RESOPFLT,2 /* reserved operand fault */ 211 00000000 .set BPTFLT,3 /* bpt instruction fault */ 212 00000000 .set ALIGNFLT,4 /* alignment fault */ 213 00000000 .set SYSCALL,5 /* kcall instruction (syscall trap) */ 214 00000000 .set ARITHTRAP,6 /* arithmetic trap */ 215 00000000 .set PROTFLT,7 /* protection fault */ 216 00000000 .set TRCTRAP,8 /* trace trap */ 217 00000000 .set TRANSFLT,9 /* translation not valid fault */ 218 00000000 .set DONE,255 219 00000000 220 00000000 # 221 00000000 # Event codes 222 00000000 # 223 00000000 .set RTCLOCK_CODE,7 /* real time clock event */ 224 00000000 .set RESOP_CODE,0x2d /* reserved operand fault */ 225 00000000 .set RESAD_CODE,0x2e /* reserved address fault */ 226 00000000 .set ARITH_CODE,0x34 /* arithmetic fault */ 227 00000000 .set FPM_CODE,0x37 /* fpp emulation trap */ 228 00000000 .set INTEGER_OVERFLOW,1 /* code for arith. fault */ 229 00000000 230 00000000 # 231 00000000 # Arithmetic Event types 232 00000000 # 233 00000000 .set INT_OVFL_CODE,1 /* integer overflow */ 234 00000000 .set INT_0_DIV_CODE,2 /* integer divide by 0 */ 235 00000000 .set FLT_0_DIV_CODE,3 /* floating divide by 0 */ 236 00000000 .set FLT_OVFL_CODE,4 /* floating overflow */ 237 00000000 .set FLT_UNDFL_CODE,5 /* floating underflow */ 238 00000000 239 00000000 # 240 00000000 # Floating Point Instruction Op-Codes 241 00000000 # 242 00000000 .set LDF_OP_CODE,0x06 /* sgl load acc. instr */ 243 00000000 .set LDD_OP_CODE,0x07 /* dbl load acc. instr */ 244 00000000 .set LNF_OP_CODE,0x16 /* sgl load-neg acc. instr */ 245 00000000 .set LND_OP_CODE,0x17 /* dbl load-neg acc. instr */ 246 00000000 .set STF_OP_CODE,0x26 /* sgl store acc. instr */ 247 00000000 .set STD_OP_CODE,0x27 /* dbl store acc. instr */ 248 00000000 .set CMPF_OP_CODE,0x36 /* sgl compare instr */ 249 00000000 .set CMPD_OP_CODE,0x37 /* dbl compare instr */ 250 00000000 .set CMPF2_OP_CODE,0x46 /* sgl compare 2 instr */ 251 00000000 .set CMPD2_OP_CODE,0x47 /* dbl compare 2 instr */ 252 00000000 .set TSTF_OP_CODE,0x56 /* sgl test acc. instr */ 253 00000000 .set TSTD_OP_CODE,0x57 /* dbl test acc. instr */ 254 00000000 .set PUSHD_OP_CODE,0x67 /* dbl push acc. instr */ 255 00000000 .set CVLF_OP_CODE,0x76 /* convert int to sgl instr */ 256 00000000 .set CVLD_OP_CODE,0x77 /* convert int to dbl instr */ 257 00000000 .set CVFL_OP_CODE,0x86 /* convert sgl to int instr */ 258 00000000 .set CVDL_OP_CODE,0x87 /* convert dbl to int instr */ 259 00000000 .set LDFD_OP_CODE,0x97 /* load sgl to dbl instr */ 260 00000000 .set CVDF_OP_CODE,0xa6 /* convert dbl to sgl instr */ 261 00000000 .set NEGF_OP_CODE,0xb6 /* negate sgl acc. instr */ 262 00000000 .set NEGD_OP_CODE,0xb7 /* negate dbl acc. instr */ 263 00000000 .set ADDF_OP_CODE,0xc6 /* sgl add instr */ 264 00000000 .set ADDD_OP_CODE,0xc7 /* dbl add instr */ 265 00000000 .set SUBF_OP_CODE,0xd6 /* sgl subtract instr */ 266 00000000 .set SUBD_OP_CODE,0xd7 /* dbl subtract instr */ 267 00000000 .set MULF_OP_CODE,0xe6 /* sgl multiply instr */ 268 00000000 .set MULD_OP_CODE,0xe7 /* dbl multiply instr */ 269 00000000 .set DIVF_OP_CODE,0xf6 /* sgl divide instr */ 270 00000000 .set DIVD_OP_CODE,0xf7 /* dbl divide instr */ 271 00000000 .set SINF_OP_CODE,0x05 /* sgl sine instr */ 272 00000000 .set COSF_OP_CODE,0x15 /* sgl cosine instr */ 273 00000000 .set ATANF_OP_CODE,0x25 /* sgl arc-tangent instr */ 274 00000000 .set LOGF_OP_CODE,0x35 /* sgl natural log instr */ 275 00000000 .set SQRTF_OP_CODE,0x45 /* sgl square root instr */ 276 00000000 .set EXPF_OP_CODE,0x55 /* sgl "e to the x" instr */ 277 00000000 .set MULL2_OP_CODE,0x4c /* integer multiply - 2 ops */ 278 00000000 .set MULL3_OP_CODE,0x5c /* integer multiply - 3 ops */ 279 00000000 280 00000000 281 00000000 # 282 00000000 # Addressing test constants - These must agree with "fpp_defs.h" 283 00000000 # 284 00000000 .set ADR_ABSOLUTE,1 /* absolute address */ 285 00000000 .set ADR_LITERAL,2 /* literal -short immediate byte */ 286 00000000 .set ADR_IM_B,3 /* immediate byte */ 287 00000000 .set ADR_IM_W,4 /* immediate word */ 288 00000000 .set ADR_IM_L,5 /* immediate long-word */ 289 00000000 .set ADR_B_DSP,6 /* byte displ relative */ 290 00000000 .set ADR_W_DSP,7 /* word displ relative */ 291 00000000 .set ADR_L_DSP,8 /* long-word displ relative */ 292 00000000 .set ADR_B_DSP_DEF,9 /* byte displ relative deferred */ 293 00000000 .set ADR_W_DSP_DEF,10 /* word displ relative deferred */ 294 00000000 .set ADR_L_DSP_DEF,11 /* L-word displ relative deferred */ 295 00000000 .set ADR_REG,12 /* direct register */ 296 00000000 .set ADR_REG_DEF,13 /* register deferred */ 297 00000000 .set ADR_FP_DEF,14 /* FP deferred */ 298 00000000 .set ADR_SP_DEF,15 /* SP deferred */ 299 00000000 .set ADR_PUSH,16 /* auto-decrement SP */ 300 00000000 .set ADR_POP,17 /* auto-increment SP */ 301 00000000 .set ADR_POP_DEF,18 /* auto-increment SP deferred */ 302 00000000 .set ADR_REG_B,19 /* register + byte displ */ 303 00000000 .set ADR_REG_W,20 /* register + word displ */ 304 00000000 .set ADR_REG_L,21 /* register + long-word displ */ 305 00000000 .set ADR_REG_B_DEF,22 /* register + byte displ deferred */ 306 00000000 .set ADR_REG_W_DEF,23 /* register + word displ deferred */ 307 00000000 .set ADR_REG_L_DEF,24 /* register + L-word displ deferred */ 308 00000000 .set ADR_I_FP_DEF,25 /* indexed (frame pointer deferred) */ 309 00000000 .set ADR_I_L,26 /* indexed (longword displacement) */ 310 00000000 311 00000000 312 00000000 #************************************************************************* 313 00000000 # 314 00000000 # Stuff for the Demand Paging , Events, & Addressing Tests 315 00000000 # 316 00000000 #************************************************************************/ 317 00000000 .set SGL,1 /* sgl precision data */ 318 00000000 .set DBL,2 /* dbl precision data */ 319 00000000 .set ENABLE_EVENTS,0x60 /* enable ovfl & undfl events */ 320 00000000 .set NONE,0 /* no operand flag */ 321 00000000 .set LOAD,1 /* read-the-operand flag */ 322 00000000 .set STORE,2 /* store-the-operand flag */ 323 00000000 324 00000000 .set NO_EVT_HLT,1 /* halt code: did not Get event */ 325 00000000 .set EVT_MSK_HLT,2 /* halt code: got masked event */ 326 00000000 .set BAD_PSL_HLT,3 /* halt code: wrong PSL value */ 327 00000000 .set PUSH_CNT_HLT,4 /* halt code: wrong # ops on stk */ 328 00000000 .set PUSH_PSL_HLT,5 /* halt code: bad PSL on stack */ 329 00000000 .set PUSH_PC_HLT,6 /* halt code: bad PC on stack */ 330 00000000 .set BAD_REG_HLT,7 /* halt code: bad final register */ 331 00000000 .set BAD_ACC_HLT,8 /* halt code: bad final Acc. */ 332 00000000 333 00000000 # 334 00000000 # set DMP_PG_0 to the 1st empty page 335 00000000 # 336 00000000 .set DMP_PG_0,0x36000 337 00000000 .set DMP_PG_1,DMP_PG_0+0x400 338 00000000 .set DMP_PG_2,DMP_PG_1+0x400 339 00000000 .set DMP_PG_3,DMP_PG_2+0x400 340 00000000 .set DMP_PG_4,DMP_PG_3+0x400 341 00000000 .set DMP_PG_5,DMP_PG_4+0x400 342 00000000 .set DMP_PG_6,DMP_PG_5+0x400 343 00000000 .set DMP_PG_7,DMP_PG_6+0x400 344 00000000 .set DMP_PG_8,DMP_PG_7+0x400 345 00000000 .set DMP_PG_9,DMP_PG_8+0x400 346 00000000 .set DMP_PG_10,DMP_PG_9+0x400 347 00000000 .set DMP_PG_11,DMP_PG_10+0x400 348 00000000 .set DMP_PG_12,DMP_PG_11+0x400 349 00000000 .set DMP_PG_13,DMP_PG_12+0x400 350 00000000 351 00000000 # 352 00000000 # test code space for the address / demand page tests 353 00000000 # 354 00000000 .set START_OF_CODE,DMP_PG_1-20 /* 1st addr of test-code space */ 355 00000000 .set CODE_BUF_SIZE,40 /* # bytes in test-code space */ 356 00000000 .set END_OF_CODE,START_OF_CODE+CODE_BUF_SIZE 357 00000000 358 00000000 # 359 00000000 # data locations used by the event and demand page tests 360 00000000 # 361 00000000 .set _dmp_byte_op_1,DMP_PG_1+0x40 /* 'byte offset' data */ 362 00000000 .set _dmp_byte_op_2,DMP_PG_1+0x60 /* 'byte offset' data */ 363 00000000 .set _dmp_byte_op_3,DMP_PG_1+0x80 /* 'byte offset' data */ 364 00000000 .set _dmp_op_1,DMP_PG_3-4 /* 1st data word */ 365 00000000 .set _dmp_op_1_ptr,DMP_PG_4+0x30 /* ptr to 1st data wd */ 366 00000000 .set _dmp_op_2_ptr,DMP_PG_5+0x30 /* ptr to 2nd data wd */ 367 00000000 .set _dmp_op_2,DMP_PG_7-4 /* 2nd data word */ 368 00000000 .set _dmp_op_3,DMP_PG_8 /* 3rd data word */ 369 00000000 .set _dmp_op_3_ptr,DMP_PG_9+0x30 /* ptr to 3rd data wd */ 370 00000000 .set _dmp_op_4,DMP_PG_10 /* 4th data (for pipes) */ 371 00000000 .set _dmp_op_5,DMP_PG_11 /* 5th data (for pipes) */ 372 00000000 .set _sp_minus,DMP_PG_13-4 /* SP for POPs */ 373 00000000 .set _sp_page,DMP_PG_13 /* SP page boundary */ 374 00000000 .set _sp_plus,DMP_PG_13+4 /* SP for PUSHs */ 375 00000000 376 00000000 377 00000000 378 00000000 /************************************************************************** 383 00000000 * 384 00000000 * FLOATING POINT MACRO TEST GLOBAL VARIABLES 385 00000000 * 386 00000000 **************************************************************************/ 387 00000000 388 00000000 Symbol _sp_plus,DMP_ not found --- 389 00000000 00000000 filler: 390 00000004 .align 2 /* longword align */ 391 00000004 .globl _run_list 392 00000004 _run_list: 393 00000004 .long 0 /* user entered test to execute */ 394 0000BC88 00000000 .align 2 /* longword align */ 395 0000BC8C 396 0000BC8C .globl _test_no 397 0000BC8C _test_no: 398 0000BC8C 00000000 .long 0 /* test # being executed */ 399 0000BC90 400 0000BC90 .globl _subtest 401 0000BC90 _subtest: 402 0000BC90 00000000 .long 0 /* subtest # being executed */ 403 0000BC94 404 0000BC94 .globl _cycle 405 0000BC94 _cycle: 406 0000BC94 00000000 .long 0 /* current test cycle */ 407 0000BC98 408 0000BC98 .globl _run_all 409 0000BC98 _run_all: 410 0000BC98 .long 0 /* flag - if <> 0, run all tests */ 411 0000BC98 6d efffffffe6 412 0000BC9E 20 .align 2 413 0000BC9F .globl _Hardclk 414 0000BC9F 00 _Hardclk: 415 0000BCA0 incl _clk_cnt 416 0000BCA0 00000000 rei 417 0000BCA4 418 0000BCA4 00000000 .align 2 419 0000BCA8 .globl _tstmsk 420 0000BCA8 _tstmsk: .long 0 /* tests to run */ 421 0000BCA8 .globl _ss1 422 0000BCA8 00000000 _ss1: .long 0 /* If 1 then do not print heading messages */ 423 0000BCAC 424 0000BCAC .globl _zero /* a known '0' data pattern */ 425 0000BCAC _zero: 426 0000BCAC 00000000 .long 0 427 0000BCB0 428 0000BCB0 .globl _nonstop /* continuous testing flag */ 429 0000BCB0 _nonstop: 430 0000BCB0 00000000 .long 0 431 0000BCB4 432 0000BCB4 .globl _OPTIONS /* r1 options */ 433 0000BCB4 _OPTIONS: 434 0000BCB4 00000000 .long 0 435 0000BCB8 436 0000BCB8 .globl _halt_flg /* b(0) flag -halt on error */ 437 0000BCB8 _halt_flg: 438 0000BCB8 00000000 .long 0 439 0000BCBC 440 0000BCBC .globl _loop_on_err /* b(1) flag -loop on error */ 441 0000BCBC _loop_on_err: 442 0000BCBC 00000000 .long 0 443 0000BCC0 444 0000BCC0 .globl _prt_error /* b(2) flag -print error messages */ 445 0000BCC0 _prt_error: 446 0000BCC0 00000000 .long 0 447 0000BCC4 448 0000BCC4 .globl _prt_hdrs /* b(3) flag -print header messages */ 449 0000BCC4 _prt_hdrs: 450 0000BCC4 00000000 .long 0 451 0000BCC8 452 0000BCC8 .globl _en_data_cache /* b(4) flag -enable the data cache */ 453 0000BCC8 _en_data_cache: 454 0000BCC8 00000000 .long 0 455 0000BCCC 456 0000BCCC .globl _user_mode /* b(5) flag -run DMP tests in user mode */ 457 0000BCCC _user_mode: 458 0000BCCC 00000000 .long 0 459 0000BCD0 460 0000BCD0 .globl _evt_inst /* R3 flag -instruction op-code to test */ 461 0000BCD0 _evt_inst: 462 0000BCD0 00000000 .long 0 463 0000BCD4 464 0000BCD4 .globl _no_fpp_wcs /* flag -the NO-FPP WCS was loaded */ 465 0000BCD4 _no_fpp_wcs: 466 0000BCD4 00000000 .long 0 467 0000BCD8 468 0000BCD8 .globl _emulated_inst /* flag -instr is emulated w/ no-fpp wcs */ 469 0000BCD8 _emulated_inst: 470 0000BCD8 00000000 .long 0 471 0000BCDC 472 0000BCDC .globl _force_loop /* flag -force loop after error if set */ 473 0000BCDC _force_loop: 474 0000BCDC 00000000 .long 0 475 0000BCE0 476 0000BCE0 .globl _clock_event /* flag - a clock event occurred */ 477 0000BCE0 _clock_event: 478 0000BCE0 00000000 .long 0 479 0000BCE4 480 0000BCE4 .globl _test_event /* flag - type of event under test */ 481 0000BCE4 _test_event: 482 0000BCE4 00000000 .long 0 483 0000BCE8 484 0000BCE8 .globl _exp_event /* flag - expect fpp event & type expected */ 485 0000BCE8 _exp_event: 486 0000BCE8 00000000 .long 0 487 0000BCEC 488 0000BCEC .globl _exp_code /* flag - type of arithmetic fault expected */ 489 0000BCEC _exp_code: 490 0000BCEC 00000000 .long 0 491 0000BCF0 492 0000BCF0 .globl _evt_disabled /* flag - event is disabled in the PSW */ 493 0000BCF0 _evt_disabled: 494 0000BCF0 0000 .long 0 495 0000BCF2 0000 496 0000BCF4 .globl _disable_mask /* mask to disable events in the PSW */ 497 0000BCF4 _disable_mask: 498 0000BCF4 .word 0 499 0000BCF4 00000000 .align 2 500 0000BCF8 501 0000BCF8 .globl _nop_cnt /* # of NOPs between test instructions */ 502 0000BCF8 _nop_cnt: 503 0000BCF8 00000000 .long 0 504 0000BCFC 505 0000BCFC .globl _pipe_test /* flag - pipelineing test in progress */ 506 0000BCFC _pipe_test: 507 0000BCFC 00000000 .long 0 508 0000BD00 509 0000BD00 .globl _pipe_inst1 /* 1st instruction in pipelined test */ 510 0000BD00 _pipe_inst1: 511 0000BD00 00000000 .long 0 512 0000BD04 513 0000BD04 .globl _pipe_inst2 /* last instruction in pipelined test */ 514 0000BD04 _pipe_inst2: 515 0000BD04 00000000 .long 0 516 0000BD08 517 0000BD08 .globl _event_msg /* pointer to event message */ 518 0000BD08 _event_msg: 519 0000BD08 00000000 .long 0 520 0000BD0C 521 0000BD0C .globl _event_return /* return address after fpp event */ 522 0000BD0C _event_return: 523 0000BD0C 00000000 .long 0 524 0000BD10 525 0000BD10 .globl _unexp_event_ret /* return address after unexpected event */ 526 0000BD10 _unexp_event_ret: 527 0000BD10 00000000 .long 0 528 0000BD14 529 0000BD14 .globl _event_type /* event type (arith, resop, etc.) */ 530 0000BD14 _event_type: 531 0000BD14 00000000 .long 0 532 0000BD18 533 0000BD18 .globl _event_code /* arith fault type (ovfl, undfl,...) */ 534 0000BD18 _event_code: 535 0000BD18 00000000 .long 0 536 0000BD1C 537 0000BD1C .globl _fpm_trap_occurred /* flag -got an FPM trap */ 538 0000BD1C _fpm_trap_occurred: 539 0000BD1C 00000000 .long 0 540 0000BD20 541 0000BD20 .globl _push_cnt /* # longwords pushed on stack by an event */ 542 0000BD20 _push_cnt: 543 0000BD20 00000000 .long 0 544 0000BD24 545 0000BD24 .globl _exp_push_cnt /* # longwords expected to be pushed */ 546 0000BD24 _exp_push_cnt: 547 0000BD24 00000000 .long 0 548 0000BD28 549 0000BD28 .globl _i_cache_hit /* instruction cache hit flag */ 550 0000BD28 _i_cache_hit: 551 0000BD28 00000000 .long 0 552 0000BD2C 553 0000BD2C .globl _monitor_fp /* the monitor's frame pointer */ 554 0000BD2C _monitor_fp: 555 0000BD2C 00000000 .long 0 556 0000BD30 557 0000BD30 .globl _monitor_sp /* the monitor's stack pointer */ 558 0000BD30 _monitor_sp: 559 0000BD30 00000000 .long 0 560 0000BD34 561 0000BD34 .globl _run_code_psl /* "run_code"'s entry PSL */ 562 0000BD34 _run_code_psl: 563 0000BD34 00000000 .long 0 564 0000BD38 565 0000BD38 .globl _event_pc /* PC pushed on the stack by an event */ 566 0000BD38 _event_pc: 567 0000BD38 00000000 .long 0 568 0000BD3C 569 0000BD3C .globl _event_psl /* PSL pushed on the stack by an event */ 570 0000BD3C _event_psl: 571 0000BD3C 00000000 .long 0 572 0000BD40 00000000 573 0000BD44 .globl _post_evt_acc /* Accumulator value after an event */ 574 0000BD44 _post_evt_acc: 575 0000BD44 .long 0 576 0000BD44 00000000 .long 0 577 0000BD48 578 0000BD48 .globl _post_event_psl /* PSL after an FPM event */ 579 0000BD48 _post_event_psl: 580 0000BD48 00000000 .long 0 581 0000BD4C 582 0000BD4C .globl _pre_event_fp /* frame pointer before an expected event */ 583 0000BD4C _pre_event_fp: 584 0000BD4C 00000000 .long 0 585 0000BD50 586 0000BD50 .globl _pre_event_sp /* stack pointer before an expected event */ 587 0000BD50 _pre_event_sp: 588 0000BD50 00000000 .long 0 589 0000BD54 590 0000BD54 .globl _post_event_sp /* stack pointer after an fpp event */ 591 0000BD54 _post_event_sp: 592 0000BD54 .long 0 593 0000BD54 00000000 594 0000BD58 /* post_event_fp is with STORE_REG */ 595 0000BD58 596 0000BD58 00000000 .globl _count /* cycle count */ 597 0000BD5C _count: .long 0 598 0000BD5C 00000000 599 0000BD60 .globl _tmp_mcbr 600 0000BD60 _tmp_mcbr: .long 0 601 0000BD60 .globl _tmp_mear 602 0000BD60 _tmp_mear: .long 0 603 0000BD60 604 0000BD60 00000000 605 0000BD64 00000000 606 0000BD68 .globl _dbl_value_1 /* 1st dbl test value */ 607 0000BD68 _dbl_value_1: 608 0000BD68 .long 0 609 0000BD68 00000000 .long 0 610 0000BD6C 00000000 611 0000BD70 .globl _dbl_value_2 /* 2nd dbl test value */ 612 0000BD70 _dbl_value_2: 613 0000BD70 .long 0 614 0000BD70 00000000 .long 0 615 0000BD74 00000000 616 0000BD78 .globl _dbl_value_3 /* 3rd dbl test value */ 617 0000BD78 _dbl_value_3: 618 0000BD78 .long 0 619 0000BD78 00000000 .long 0 620 0000BD7C 00000000 621 0000BD80 .globl _dbl_expected /* expected dbl data */ 622 0000BD80 _dbl_expected: 623 0000BD80 .long 0 624 0000BD80 00000000 .long 0 625 0000BD84 00000000 626 0000BD88 .globl _dbl_ld_acc /* load dbl acc. from here */ 627 0000BD88 _dbl_ld_acc: 628 0000BD88 .long 0 629 0000BD88 00000000 .long 0 630 0000BD8C 00000000 631 0000BD90 .globl _dbl_st_acc /* stored dbl accumulator */ 632 0000BD90 _dbl_st_acc: 633 0000BD90 .long 0 634 0000BD90 00000000 .long 0 635 0000BD94 00000000 636 0000BD98 .globl _dbl_dummy1 /* dummy quad word */ 637 0000BD98 _dbl_dummy1: 638 0000BD98 .long 0 639 0000BD98 00000000 .long 0 640 0000BD9C 00000000 641 0000BDA0 .globl _dbl_dummy2 /* ditto */ 642 0000BDA0 _dbl_dummy2: 643 0000BDA0 .long 0 644 0000BDA0 00000000 .long 0 645 0000BDA4 646 0000BDA4 .globl _sgl_value_1 /* 1st sgl data value */ 647 0000BDA4 _sgl_value_1: 648 0000BDA4 00000000 .long 0 649 0000BDA8 650 0000BDA8 .globl _sgl_value_2 /* 2nd sgl data value */ 651 0000BDA8 _sgl_value_2: 652 0000BDA8 00000000 .long 0 653 0000BDAC 654 0000BDAC .globl _sgl_value_3 /* 3rd sgl data value */ 655 0000BDAC _sgl_value_3: 656 0000BDAC 00000000 .long 0 657 0000BDB0 658 0000BDB0 .globl _sgl_value_4 /* 4th sgl data value */ 659 0000BDB0 _sgl_value_4: 660 0000BDB0 00000000 .long 0 661 0000BDB4 662 0000BDB4 .globl _sgl_value_5 /* 5th sgl data value */ 663 0000BDB4 _sgl_value_5: 664 0000BDB4 00000000 .long 0 665 0000BDB8 666 0000BDB8 .globl _sgl_value_6 /* 6th sgl data value */ 667 0000BDB8 _sgl_value_6: 668 0000BDB8 00000000 .long 0 669 0000BDBC 670 0000BDBC .globl _sgl_value_7 /* 7th sgl data value */ 671 0000BDBC _sgl_value_7: 672 0000BDBC 00000000 .long 0 673 0000BDC0 674 0000BDC0 .globl _sgl_value_8 /* 8th sgl data value */ 675 0000BDC0 _sgl_value_8: 676 0000BDC0 00000000 .long 0 677 0000BDC4 678 0000BDC4 .globl _sgl_value_9 /* 9th sgl data value */ 679 0000BDC4 _sgl_value_9: 680 0000BDC4 00000000 .long 0 681 0000BDC8 682 0000BDC8 .globl _sgl_value_10 /* 10th sgl data value */ 683 0000BDC8 _sgl_value_10: 684 0000BDC8 00000000 .long 0 685 0000BDCC 686 0000BDCC .globl _sgl_expected /* expected sgl data */ 687 0000BDCC _sgl_expected: 688 0000BDCC 00000000 .long 0 689 0000BDD0 690 0000BDD0 .globl _sgl_ld_acc /* load sgl acc. from here */ 691 0000BDD0 _sgl_ld_acc: 692 0000BDD0 00000000 .long 0 693 0000BDD4 694 0000BDD4 .globl _sgl_st_acc /* stored sgl acc. */ 695 0000BDD4 _sgl_st_acc: 696 0000BDD4 00000000 .long 0 697 0000BDD8 698 0000BDD8 .globl _sgl_dummy1 /* a dummy variable */ 699 0000BDD8 _sgl_dummy1: 700 0000BDD8 00000000 .long 0 701 0000BDDC 702 0000BDDC .globl _sgl_dummy2 /* a dummy variable, too */ 703 0000BDDC _sgl_dummy2: 704 0000BDDC 00000000 .long 0 705 0000BDE0 706 0000BDE0 .globl _psl_val /* PSL value */ 707 0000BDE0 _psl_val: 708 0000BDE0 00000000 .long 0 709 0000BDE4 710 0000BDE4 .globl _exp_psl /* expected PSL value */ 711 0000BDE4 _exp_psl: 712 0000BDE4 00000000 .long 0 713 0000BDE8 714 0000BDE8 .globl _init_psl /* initial PSL value */ 715 0000BDE8 _init_psl: 716 0000BDE8 000000ff .long 0 717 0000BDEC fffffff1 718 0000BDF0 00000000 .globl _status_array /* array of +, -, 0 data */ 719 0000BDF4 _status_array: 720 0000BDF4 .long 255 /* + */ 721 0000BDF4 .long -15 /* - */ 722 0000BDF4 00000000 .long 0 /* 0 */ 723 0000BDF8 724 0000BDF8 .globl _status_index /* index to status array */ 725 0000BDF8 _status_index: 726 0000BDF8 00000000 .long 0 727 0000BDFC 728 0000BDFC .globl _test_flags /* condition flags seen */ 729 0000BDFC _test_flags: 730 0000BDFC 00000000 .long 0 731 0000BE00 732 0000BE00 .globl _fpm_ms_op /* MS op on stack -FPM trap */ 733 0000BE00 _fpm_ms_op: 734 0000BE00 00000000 .long 0 735 0000BE04 736 0000BE04 .globl _fpm_ls_op /* LS op on stack -FPM trap */ 737 0000BE04 _fpm_ls_op: 738 0000BE04 00000000 .long 0 739 0000BE08 740 0000BE08 .globl _fpm_op_code /* stack's op-code -FPM trap */ 741 0000BE08 _fpm_op_code: 742 0000BE08 00000000 .long 0 743 0000BE0C 744 0000BE0C .globl _fpm_pc /* stack's PC -FPM trap */ 745 0000BE0C _fpm_pc: 746 0000BE0C 00000000 .long 0 747 0000BE10 748 0000BE10 .globl _fpm_psl /* stack's PSL -FPM trap */ 749 0000BE10 _fpm_psl: 750 0000BE10 00000000 .long 0 751 0000BE14 752 0000BE14 .globl _rtc_occurred /* flag -clock event seen */ 753 0000BE14 _rtc_occurred: 754 0000BE14 00000000 .long 0 755 0000BE18 756 0000BE18 .globl _clock_retrys /* # times to wait for clock */ 757 0000BE18 _clock_retrys: 758 0000BE18 00000000 .long 0 759 0000BE1C 760 0000BE1C .globl _pop_val_1 /* 1st popped stack data */ 761 0000BE1C _pop_val_1: 762 0000BE1C 00000000 .long 0 763 0000BE20 764 0000BE20 .globl _pop_val_2 /* 2nd popped stack data */ 765 0000BE20 _pop_val_2: 766 0000BE20 00000000 .long 0 767 0000BE24 768 0000BE24 .globl _pop_val_3 /* 3rd popped stack data */ 769 0000BE24 _pop_val_3: 770 0000BE24 00000000 .long 0 771 0000BE28 772 0000BE28 .globl _pop_val_4 /* 4th popped stack data */ 773 0000BE28 _pop_val_4: 774 0000BE28 00000000 .long 0 775 0000BE2C 776 0000BE2C .globl _pop_val_5 /* 5th popped stack data */ 777 0000BE2C _pop_val_5: 778 0000BE2C 00000000 .long 0 779 0000BE30 780 0000BE30 .globl _pop_val_6 /* 6th popped stack data */ 781 0000BE30 _pop_val_6: 782 0000BE30 00000000 .long 0 783 0000BE34 784 0000BE34 .globl _exp_pc /* expected PC */ 785 0000BE34 _exp_pc: 786 0000BE34 00000000 .long 0 787 0000BE38 788 0000BE38 .globl _act_pc /* actual PC */ 789 0000BE38 _act_pc: 790 0000BE38 00000000 .long 0 791 0000BE3C 792 0000BE3C .globl _op_code /* op-code of the inst. */ 793 0000BE3C _op_code: 794 0000BE3C 00000000 .long 0 795 0000BE40 796 0000BE40 .globl _op_name /* instruction name */ 797 0000BE40 _op_name: 798 0000BE40 00000000 .long 0 799 0000BE44 800 0000BE44 .globl _precision /* sgl / dbl precision inst */ 801 0000BE44 _precision: 802 0000BE44 00000000 .long 0 803 0000BE48 804 0000BE48 .globl _acc_ld_size /* sgl or dbl acc. loaded */ 805 0000BE48 _acc_ld_size: 806 0000BE48 00000000 .long 0 807 0000BE4C 808 0000BE4C .globl _acc_st_size /* sgl or dbl acc. stored */ 809 0000BE4C _acc_st_size: 810 0000BE4C 00000000 .long 0 811 0000BE50 812 0000BE50 .globl _no_ops /* # of operands needed */ 813 0000BE50 _no_ops: 814 0000BE50 00000000 .long 0 815 0000BE54 816 0000BE54 .globl _op_type /* load / store operand */ 817 0000BE54 _op_type: 818 0000BE54 00000000 .long 0 819 0000BE58 820 0000BE58 .globl _load_type_inst /* flag -inst loads the Acc */ 821 0000BE58 _load_type_inst: 822 0000BE58 00000000 .long 0 823 0000BE5C 824 0000BE5C .globl _sgl_op /* inst has sgl operand(s) */ 825 0000BE5C _sgl_op: 826 0000BE5C 00000000 .long 0 827 0000BE60 828 0000BE60 .globl _s_to_d /* inst converts sgl to dbl */ 829 0000BE60 _s_to_d: 830 0000BE60 00000000 .long 0 831 0000BE64 832 0000BE64 .globl _d_to_s /* inst converts dbl to sgl */ 833 0000BE64 _d_to_s: 834 0000BE64 00000000 .long 0 835 0000BE68 836 0000BE68 .globl _valid_test /* flag -some tests were run */ 837 0000BE68 _valid_test: 838 0000BE68 00000000 .long 0 839 0000BE6C 840 0000BE6C .globl _insts_tested /* # of instructions tested */ 841 0000BE6C _insts_tested: 842 0000BE6C 00000000 .long 0 843 0000BE70 844 0000BE70 .globl _force_sp /* flag to set the SP value */ 845 0000BE70 _force_sp: 846 0000BE70 00000000 .long 0 847 0000BE74 848 0000BE74 .globl _data_ptr /* ptr to dmp test data tbl */ 849 0000BE74 _data_ptr: 850 0000BE74 00000000 .long 0 851 0000BE78 852 0000BE78 .globl _test_ptr /* ptr to result test func. */ 853 0000BE78 _test_ptr: 854 0000BE78 00000000 .long 0 855 0000BE7C 856 0000BE7C .globl _no_page_faults /* # addr page faults found */ 857 0000BE7C _no_page_faults: 858 0000BE7C 00000000 .long 0 859 0000BE80 860 0000BE80 .globl _exp_page_faults /* # addr page faults exp'd */ 861 0000BE80 _exp_page_faults: 862 0000BE80 00000000 .long 0 863 0000BE84 864 0000BE84 .globl _trans_acc_error /* flag -bad Acc after pg flt */ 865 0000BE84 _trans_acc_error: 866 0000BE84 00000000 .long 0 867 0000BE88 00000000 868 0000BE8C .globl _trans_acc /* Acc. after a page fault */ 869 0000BE8C _trans_acc: 870 0000BE8C .long 0 871 0000BE8C 00000000 .long 0 872 0000BE90 00000000 873 0000BE94 .globl _exp_trans_acc /* Acc. expected after fault */ 874 0000BE94 _exp_trans_acc: 877 0000BE94 .long 0 878 0000BE94 .long 0 879 0000BE94 00000040 880 0000BE98 /* 881 0000BE98 * OFFSETS FROM THE CODE BUFFER TO THE DMP DATA OPERANDS 882 0000BE98 */ 883 0000BE98 00000060 .globl _os_b_op1 /* offset to byte operand 1 */ 884 0000BE9C _os_b_op1: 885 0000BE9C .long _dmp_byte_op_1-DMP_PG_1 886 0000BE9C 887 0000BE9C 00000080 .globl _os_b_op2 /* offset to byte operand 2 */ 888 0000BEA0 _os_b_op2: 889 0000BEA0 .long _dmp_byte_op_2-DMP_PG_1 890 0000BEA0 891 0000BEA0 000007fc .globl _os_b_op3 /* offset to byte operand 3 */ 892 0000BEA4 _os_b_op3: 893 0000BEA4 .long _dmp_byte_op_3-DMP_PG_1 894 0000BEA4 895 0000BEA4 000017fc .globl _os_op1 /* offset to word operand 1 */ 896 0000BEA8 _os_op1: 897 0000BEA8 .long _dmp_op_1-DMP_PG_1 898 0000BEA8 899 0000BEA8 00001c00 .globl _os_op2 /* offset to word operand 2 */ 900 0000BEAC _os_op2: 901 0000BEAC .long _dmp_op_2-DMP_PG_1 902 0000BEAC 903 0000BEAC 00000c30 .globl _os_op3 /* offset to word operand 3 */ 904 0000BEB0 _os_op3: 905 0000BEB0 .long _dmp_op_3-DMP_PG_1 906 0000BEB0 907 0000BEB0 00001030 .globl _os_ad_op1 /* offset to operand 1 ptr. */ 908 0000BEB4 _os_ad_op1: 909 0000BEB4 .long _dmp_op_1_ptr-DMP_PG_1 910 0000BEB4 911 0000BEB4 00002030 .globl _os_ad_op2 /* offset to operand 2 ptr. */ 912 0000BEB8 _os_ad_op2: 913 0000BEB8 .long _dmp_op_2_ptr-DMP_PG_1 914 0000BEB8 917 0000BEB8 .globl _os_ad_op3 /* offset to operand 3 ptr. */ 918 0000BEB8 _os_ad_op3: 919 0000BEB8 00036440 .long _dmp_op_3_ptr-DMP_PG_1 920 0000BEBC 921 0000BEBC 922 0000BEBC /* 923 0000BEBC 00036444 * Pointers to the Demand Paging Data Operands 924 0000BEC0 */ 925 0000BEC0 .globl _adr_b_op1 /* byte operand 1's address */ 926 0000BEC0 _adr_b_op1: 927 0000BEC0 00036460 .long _dmp_byte_op_1 928 0000BEC4 929 0000BEC4 .globl _adr_bop1_lsw /* addr of byte op 1's LSW */ 930 0000BEC4 _adr_bop1_lsw: 931 0000BEC4 00036464 .long _dmp_byte_op_1+4 932 0000BEC8 933 0000BEC8 .globl _adr_b_op2 /* byte operand 2's address */ 934 0000BEC8 _adr_b_op2: 935 0000BEC8 00036480 .long _dmp_byte_op_2 936 0000BECC 937 0000BECC .globl _adr_bop2_lsw /* addr of byte op 2's LSW */ 938 0000BECC _adr_bop2_lsw: 939 0000BECC 00036bfc .long _dmp_byte_op_2+4 940 0000BED0 941 0000BED0 .globl _adr_b_op3 /* byte operand 3's address */ 942 0000BED0 _adr_b_op3: 943 0000BED0 00036c00 .long _dmp_byte_op_3 944 0000BED4 945 0000BED4 .globl _adr_op1 /* operand 1's address */ 946 0000BED4 _adr_op1: 947 0000BED4 00037bfc .long _dmp_op_1 948 0000BED8 949 0000BED8 .globl _adr_op1_lsw /* address of LSW of dbl op 1 */ 950 0000BED8 _adr_op1_lsw: 951 0000BED8 00037c00 .long _dmp_op_1+4 952 0000BEDC 953 0000BEDC .globl _adr_op2 /* operand 2's address */ 954 0000BEDC _adr_op2: 955 0000BEDC 00038000 .long _dmp_op_2 956 0000BEE0 957 0000BEE0 .globl _adr_op2_lsw /* address of LSW of dbl op 2 */ 958 0000BEE0 _adr_op2_lsw: 959 0000BEE0 00038800 .long _dmp_op_2+4 960 0000BEE4 961 0000BEE4 .globl _adr_op3 /* operand 3's address */ 962 0000BEE4 _adr_op3: 963 0000BEE4 00038c00 .long _dmp_op_3 964 0000BEE8 965 0000BEE8 .globl _adr_op4 /* operand 4's address */ 966 0000BEE8 _adr_op4: 967 0000BEE8 00037030 .long _dmp_op_4 968 0000BEEC 969 0000BEEC .globl _adr_op5 /* operand 5's address */ 970 0000BEEC _adr_op5: 971 0000BEEC 00038430 .long _dmp_op_5 972 0000BEF0 973 0000BEF0 .globl _adr_op1_ptr /* op. ptr 1's address */ 974 0000BEF0 _adr_op1_ptr: 975 0000BEF0 00037430 .long _dmp_op_1_ptr 976 0000BEF4 977 0000BEF4 .globl _adr_op3_ptr /* op. ptr 3's address */ 978 0000BEF4 _adr_op3_ptr: 979 0000BEF4 00000000 .long _dmp_op_3_ptr 980 0000BEF8 981 0000BEF8 .globl _adr_op2_ptr /* op. ptr 2's address */ 982 0000BEF8 _adr_op2_ptr: 983 0000BEF8 00000000 .long _dmp_op_2_ptr 984 0000BEFC 985 0000BEFC .globl _reg_no /* register being validated */ 986 0000BEFC _reg_no: 987 0000BEFC 00000000 .long 0 988 0000BF00 989 0000BF00 .globl _regs_ok /* flag -no reg. miscompares*/ 990 0000BF00 _regs_ok: 991 0000BF00 00000000 .long 0 992 0000BF04 993 0000BF04 .globl _exp_reg /* expected reg. value */ 994 0000BF04 _exp_reg: 995 0000BF04 00000000 .long 0 996 0000BF08 997 0000BF08 .globl _act_reg /* actual register value */ 998 0000BF08 _act_reg: 999 0000BF08 00000000 .long 0 1000 0000BF0C 1001 0000BF0C .globl _test_index /* test table index */ 1002 0000BF0C _test_index: 1003 0000BF0C 00000000 .long 0 1004 0000BF10 1005 0000BF10 .globl _inst_index /* instruction table index */ 1006 0000BF10 _inst_index: 1007 0000BF10 00000000 .long 0 1008 0000BF14 1009 0000BF14 .globl _index /* test data index */ 1010 0000BF14 _index: 1011 0000BF14 00000000 .long 0 1012 0000BF18 1013 0000BF18 .globl _index2 /* test data index # 2 */ 1014 0000BF18 _index2: 1015 0000BF18 00000000 .long 0 1016 0000BF1C 1017 0000BF1C .globl _old_indx /* test data index (-1) */ 1018 0000BF1C _old_indx: 1019 0000BF1C 40800000 .long 0 1020 0000BF20 1021 0000BF20 .globl _max_index /* maximum data index */ 1022 0000BF20 _max_index: 1023 0000BF20 40800000 .long 0 1024 0000BF24 1025 0000BF24 .globl _loop_val_1a /* op_1 MSW for data swaps */ 1026 0000BF24 _loop_val_1a: 1027 0000BF24 40800000 .long 0x40800000 1028 0000BF28 1029 0000BF28 .globl _loop_val_1b /* op_1 MSW for data swaps */ 1030 0000BF28 _loop_val_1b: 1031 0000BF28 40800000 .long 0x40800000 1032 0000BF2C 1033 0000BF2C .globl _loop_val_1c /*op_1 LSW for data swaps */ 1034 0000BF2C _loop_val_1c: 1035 0000BF2C 40800000 .long 0x40800000 1036 0000BF30 1037 0000BF30 .globl _loop_val_1d /* op_1 LSW for data swaps */ 1038 0000BF30 _loop_val_1d: 1039 0000BF30 40800000 .long 0x40800000 1040 0000BF34 1041 0000BF34 .globl _loop_val_2a /* op_2 MSW for data swaps */ 1042 0000BF34 _loop_val_2a: 1043 0000BF34 40800000 .long 0x40800000 1044 0000BF38 1045 0000BF38 .globl _loop_val_2b /* op_2 MSW for data swaps */ 1046 0000BF38 _loop_val_2b: 1047 0000BF38 40800000 .long 0x40800000 1048 0000BF3C 1049 0000BF3C .globl _loop_val_2c /* op_2 LSW for data swaps */ 1050 0000BF3C _loop_val_2c: 1051 0000BF3C 00000000 .long 0x40800000 1052 0000BF40 1053 0000BF40 .globl _loop_val_2d /* op_2 LSW for data swaps */ 1054 0000BF40 _loop_val_2d: 1055 0000BF40 00000000 .long 0x40800000 1056 0000BF44 1057 0000BF44 .globl _error /* an error exists flag */ 1058 0000BF44 _error: 1059 0000BF44 00000000 .long 0 1060 0000BF48 1061 0000BF48 .globl _err_code /* code ( type ) of error */ 1062 0000BF48 _err_code: 1063 0000BF48 00000000 .long 0 1064 0000BF4C 1065 0000BF4C .globl _subtest_message /* pointer to test message */ 1066 0000BF4C _subtest_message: 1067 0000BF4C **** .long 0 1068 0000BF88 1069 0000BF88 .globl _error_message /* pointer to error message */ 1070 0000BF88 _error_message: 1071 0000BF88 **** .long 0 1072 0000BFC4 1073 0000BFC4 .globl _load_regs /* load registers' buffer */ 1074 0000BFC4 _load_regs: 1075 0000BFC4 **** .space (15*4) 1076 0000C000 1077 0000C000 .globl _store_regs /* store registers' buffer */ 1078 0000C000 _store_regs: 1079 0000C000 00000000 .space (15*4) 1080 0000C004 1081 0000C004 .globl _exp_regs /* expected register data */ 1082 0000C004 _exp_regs: 1083 0000C004 .space (15*4) 1084 0000C004 00000000 1085 0000C008 .globl _post_event_fp /* frame pointer storage */ 1086 0000C008 _post_event_fp: /* (must follow store_reg */ 1087 0000C008 .long 0 1088 0000C008 00000000 1089 0000C00C 1090 0000C00C .globl _address_fault_expected /* reserved-address fault? */ 1091 0000C00C _address_fault_expected: 1092 0000C00C 00000000 .long 0 1093 0000C010 1094 0000C010 .globl _loop_addr /* for addr test looping */ 1095 0000C010 _loop_addr: 1096 0000C010 00000000 .long 0 1097 0000C014 1098 0000C014 .globl _next_addr /* for address testing */ 1099 0000C014 _next_addr: 1100 0000C014 00000000 .long 0 1101 0000C018 1102 0000C018 .globl _addr_mode /* current addressing mode */ 1103 0000C018 _addr_mode: 1104 0000C018 00000000 .long 0 1105 0000C01C 1106 0000C01C .globl _addr_code /* code for addressing mode */ 1107 0000C01C _addr_code: 1108 0000C01C 00000000 .long 0 1109 0000C020 1110 0000C020 .globl _addr_code2 /* addr code for 2nd operand */ 1111 0000C020 _addr_code2: 1112 0000C020 00000000 .long 0 1113 0000C024 1114 0000C024 .globl _addr_code3 /* addr code for 3rd operand */ 1115 0000C024 _addr_code3: 1116 0000C024 00000000 .long 0 1117 0000C028 1118 0000C028 .globl _addr_codeB /* 2nd adr code for indexing */ 1119 0000C028 _addr_codeB: 1120 0000C028 00000000 .long 0 1121 0000C02C 1122 0000C02C .globl _addr_code_p1 /* addr code for pipelines */ 1123 0000C02C _addr_code_p1: 1124 0000C02C 00000000 .long 0 1125 0000C030 1126 0000C030 .globl _addr_code_p2 /* addr code for pipelines */ 1127 0000C030 _addr_code_p2: 1128 0000C030 00000000 .long 0 1129 0000C034 1130 0000C034 .globl _inst_size /* # of bytes in instruction */ 1131 0000C034 _inst_size: 1132 0000C034 00000000 .long 0 1133 0000C038 1134 0000C038 .globl _shift_count /* inst_buf shift count */ 1135 0000C038 _shift_count: 1136 0000C038 00000000 .long 0 1137 0000C03C 1138 0000C03C .globl _min_shift /* minimum inst_buf shift */ 1139 0000C03C _min_shift: 1140 0000C03C 00000000 .long 0 1141 0000C040 1142 0000C040 .globl _addr_size /* size of addr specifier(s)*/ 1143 0000C040 _addr_size: 1144 0000C040 00000000 .long 0 1145 0000C044 1146 0000C044 .globl _addr_1 /* address specifier # 1 */ 1147 0000C044 _addr_1: 1148 0000C044 00000000 .long 0 1149 0000C048 1150 0000C048 .globl _addr_2 /* address specifier # 2 */ 1151 0000C048 _addr_2: 1152 0000C048 **** .long 0 1153 0000C05C 1154 0000C05C .globl _addr_3 /* address specifier # 3 */ 1155 0000C05C _addr_3: 1156 0000C05C .long 0 1157 0000C05C 1158 0000C05C 00000000 .globl _inst_buf /* instruction code buffer */ 1159 0000C060 _inst_buf: 1160 0000C060 .space 20 /* 20 bytes (5 longwords) */ 1161 0000C060 .globl _end_of_inst_buf 1162 0000C060 _end_of_inst_buf: 1163 0000C060 1166 0000C060 .globl _code_addr /* start of test code */ 1167 0000C060 _code_addr: 1168 0000C060 .long 0 1169 0000C060 00000000 1170 0000C064 1171 0000C064 1172 0000C064 1173 0000C064 00000000 /* 1174 0000C068 * exaustive test data 1175 0000C068 */ 1176 0000C068 1177 0000C068 00000000 .globl _fudgeing_ok /* +/- 1 answer is OK */ 1178 0000C06C _fudgeing_ok: 1179 0000C06C **** .long 0 1180 0000C1AC 00000000 1181 0000C1B0 .globl _not_done /* keep testing flag */ 1182 0000C1B0 _not_done: 1183 0000C1B0 00000000 .long 0 1184 0000C1B4 1185 0000C1B4 .globl _use_ITT_data /* use ITT type fractions */ 1186 0000C1B4 00000000 _use_ITT_data: 1187 0000C1B8 **** .long 0 1188 0000055c * 1189 0000055c * .space (80*4) /* room for 40 stack entries */ 1189 0000055c * .space (80*4) /* room for 40 stack entries */
This archive runs on limited infrastructure. Preserving old code on modern bandwidth. Automated agents are requested to crawl responsibly.