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1.1 root 1:
2: #include "fpp_defs.h"
3:
4:
5: /*****************************************************************************
6: *
7: * LDD_STD - DOUBLE PRECISION FLOATING POINT LOAD_STORE TEST
8: *
9: *****************************************************************************/
10: ldd()
11: {
12: asm(".globl _ldd_t");
13: asm("_ldd_t:"); /* entry address */
14: if( ( cycle == 1 ) && ( prt_hdrs ) ) /* print headers on 1st pass */
15: writes("\n LDD_STD");
16: ldd_1(); /* load through a register */
17: ldd_2(); /* load through the cache */
18: ldd_3(); /* register stability ldd */
19: ldd_4(); /* register stability std */
20: ldd_5(); /* PSL stability test ldd */
21: ldd_6(); /* PSL stability test std */
22: asm("jmp *return"); /* return to the test monitor */
23: }
24:
25:
26:
27: /************************************************************************
28: *
29: * SUBTEST 1 - load through a register
30: *
31: ************************************************************************/
32: ldd_1()
33: {
34: force_loop = FALSE;
35: subtest = 1;
36: for( index = 0; index < max_ldd_1_index; index++ ) {
37: dbl_ld_acc = ldd_1_data[index].ld; /* get the operand */
38: if( dbl_ld_acc.m & 0x7f800000 )
39: dbl_expected = dbl_ld_acc; /* expected = loaded */
40: else {
41: dbl_expected.m = 0; /* expect a '0' */
42: dbl_expected.l = 0;
43: }
44: sgl_value_1 = dbl_ld_acc.m;
45: sgl_value_2 = dbl_ld_acc.l;
46: /*
47: * If LOOP ON ERROR is set, this is the loop for this subtest.
48: * The force loop flag is set after the first error.
49: */
50: asm("_ldd_1_lp1:");
51: asm("movl _sgl_value_1,r4"); /* move the operand to r4/r5 */
52: asm("movl _sgl_value_2,r5");
53: asm("ldd r4"); /* load the value */
54: asm("nop");
55: asm("std r8"); /* store the result in R8 */
56: if( force_loop )
57: asm("brb _ldd_1_lp1");; /* loop on the error */
58: /*
59: * end error loop - test the results
60: */
61: asm("movl r8,_dbl_st_acc"); /* save the stored data */
62: asm("movl r9,_dbl_st_acc+4");
63: if( ( dbl_st_acc.m != dbl_expected.m ) || /* COMPARE the */
64: ( dbl_st_acc.l != dbl_expected.l ) ) { /* values */
65: errcnt++; /* bump the error count */
66: if( prt_error ) {
67: writes(" \n"); /* start a new print line */
68: writes("cycle: ");
69: writed( cycle );
70: writes(" LDD_STD test ");
71: writed( test_no );
72: writes(", subtest 1 (Reg. Data) - BAD FINAL ACC\n");
73: print_ldd_data();
74: writes(", index = ");
75: writed( index );
76: writec('\n');
77: writes(" Acc expected = ");
78: write32h( dbl_expected.m );
79: writec(' ');
80: write32h(dbl_expected.l );
81: writec('\n');
82: }
83: if( halt_flg )
84: ldd_er_halt( BAD_ACC_HLT ); /* halt on the error */
85: if( loop_on_err ) {
86: force_loop = TRUE; /* set the force loop flag */
87: asm("brw _ldd_1_lp1");; /* and loop on the error */
88: } /* end of loop on error */
89: } /* end of compare error */
90: } /* end of WHILE loop */
91: } /* end of subtest 1 */
92:
93:
94:
95: /************************************************************************
96: *
97: * SUBTEST 2 - load through cache
98: *
99: ************************************************************************/
100: ldd_2()
101: {
102: force_loop = FALSE;
103: subtest = 2;
104: for( index = 0; index < max_ldd_1_index; index++ ) {
105: dbl_ld_acc = ldd_1_data[index].ld; /* get the operand */
106: if( dbl_ld_acc.m & 0x7f800000 )
107: dbl_expected = dbl_ld_acc; /* expected = loaded */
108: else {
109: dbl_expected.m = 0; /* expect a '0' */
110: dbl_expected.l = 0;
111: }
112: /*
113: * If LOOP ON ERROR is set, this is the loop for this subtest.
114: * The force loop flag is set after the first error.
115: */
116: asm("_ldd_2_lp1:");
117: asm("ldd _dbl_ld_acc"); /* load the value */
118: asm("nop");
119: asm("std _dbl_st_acc"); /* store the result */
120: if( force_loop )
121: asm("brb _ldd_2_lp1");; /* loop on the error */
122: /*
123: * end error loop - test the results
124: */
125: if( ( dbl_st_acc.m != dbl_expected.m ) || /* COMPARE the */
126: ( dbl_st_acc.l != dbl_expected.l ) ) { /* values */
127: errcnt++; /* bump the error count */
128: if( prt_error ) {
129: writes(" \n"); /* start a new print line */
130: writes("cycle: ");
131: writed( cycle );
132: writes(" LDD_STD test ");
133: writed( test_no );
134: writes(", subtest 2 (Cache Data) - BAD FINAL ACC\n");
135: print_ldd_data();
136: writes(", index = ");
137: writed( index );
138: writec('\n');
139: writes(" Acc expected = ");
140: write32h( dbl_expected.m );
141: writec(' ');
142: write32h( dbl_expected.l );
143: writec('\n');
144: }
145: if( halt_flg )
146: ldd_er_halt( BAD_ACC_HLT ); /* halt on the error */
147: if( loop_on_err ) {
148: force_loop = TRUE; /* set the force loop flag */
149: asm("brw _ldd_2_lp1");; /* and loop on the error */
150: } /* end of loop on error */
151: } /* end of compare error */
152: } /* end of WHILE loop */
153: } /* end of subtest 2 */
154:
155:
156:
157: /************************************************************************
158: *
159: * SUBTEST 3 - Check for register corruption (ldd)
160: *
161: ************************************************************************/
162: ldd_3()
163: {
164: force_loop = FALSE; /* clear force_loop flg */
165: subtest = 3;
166: fill_reg_buf( load_regs ); /* get patterns for regs */
167: index = 0;
168: dbl_ld_acc = ldd_1_data[0].ld; /* get value to load */
169: if( dbl_ld_acc.m & 0x7f800000 )
170: dbl_expected = dbl_ld_acc; /* expected = loaded */
171: else {
172: dbl_expected.m = 0; /* expect a '0' */
173: dbl_expected.l = 0;
174: }
175: /*
176: * If LOOP ON ERROR is set, this is the loop for this subtest.
177: * The force loop flag is set after the first error.
178: */
179: asm("_ldd_3_lp1:");
180: asm("loadr $0x1fff,_load_regs"); /* load regs 0 - 12 */
181: asm("nop");
182: asm("ldd _dbl_ld_acc"); /* load the accumulator */
183: asm("nop");
184: asm("storer $0x1fff,_store_regs"); /* store regs 0 - 12 */
185: asm("nop");
186: asm("std _dbl_st_acc"); /* save the accumulator */
187: if( force_loop )
188: asm("brb _ldd_3_lp1");; /* loop on the error */
189: /*
190: * Now compare the stored register values to those that were loaded
191: */
192: index2 = 0;
193: while( (load_regs[index2] == store_regs[index2]) && (index2 < 13) )
194: index2++; /* check reg values */
195: if( index2 < 13 ) { /* error if index2 < 13 */
196: errcnt++; /* bump the error count */
197: if( prt_error ) {
198: writes(" \n"); /* start a new print line */
199: writes("cycle: ");
200: writed( cycle );
201: writes(" LDD_STD test ");
202: writed( test_no );
203: writes(", subtest 3 - A REGISTER WAS MODIFIED\n");
204: print_ldd_data(); /* print the operands */
205: writes("\nregister "); /* print the information */
206: writed( index2 ); /* about the corrupted */
207: writes(" = "); /* register */
208: write32h( store_regs[index2] );
209: writes(", should be = ");
210: write32h( load_regs[index2] );
211: writes("\n");
212: }
213: if( halt_flg )
214: ldd_er_halt( BAD_REG_HLT ); /* halt on the error */
215: if( loop_on_err ) {
216: force_loop = TRUE; /* set the force loop flag */
217: asm("brw _ldd_3_lp1");; /* and loop on the error */
218: } /* end of loop on error */
219: } /* end of register corruption error */
220: } /* end of subtest 3 */
221:
222:
223:
224: /************************************************************************
225: *
226: * SUBTEST 4 - Check for register corruption (std)
227: *
228: ************************************************************************/
229: ldd_4()
230: {
231: force_loop = FALSE; /* clear force_loop flg */
232: subtest = 4;
233: fill_reg_buf( load_regs ); /* get patterns for regs */
234: index = 0;
235: dbl_ld_acc = ldd_1_data[0].ld; /* get value to store */
236: /*
237: * If LOOP ON ERROR is set, this is the loop for this subtest.
238: * The force loop flag is set after the first error.
239: */
240: asm("_ldd_4_lp1:");
241: asm("ldd _dbl_ld_acc"); /* load the accumulator */
242: asm("nop");
243: asm("loadr $0x1fff,_load_regs"); /* load regs 0 - 12 */
244: asm("nop");
245: asm("std _dbl_st_acc"); /* save the accumulator */
246: asm("nop");
247: asm("storer $0x1fff,_store_regs"); /* store regs 0 - 12 */
248: if( force_loop )
249: asm("brb _ldd_4_lp1");; /* loop on the error */
250: /*
251: * Now compare the stored register values to those that were loaded
252: */
253: index2 = 0;
254: while( (load_regs[index2] == store_regs[index2]) && (index2 < 13) )
255: index2++; /* check reg values */
256: if( index2 < 13 ) { /* error if index2 < 13 */
257: errcnt++; /* bump the error count */
258: if( prt_error ) {
259: writes(" \n"); /* start a new print line */
260: writes("cycle: ");
261: writed( cycle );
262: writes(" LDD_STD test ");
263: writed( test_no );
264: writes(", subtest 4 - A REGISTER WAS MODIFIED\n");
265: print_ldd_data(); /* print the operands */
266: writes("\nregister "); /* print the information */
267: writed( index2 ); /* about the corrupted */
268: writes(" = "); /* register */
269: write32h( store_regs[index2] );
270: writes(", should be = ");
271: write32h( load_regs[index2] );
272: writes("\n");
273: }
274: if( halt_flg )
275: ldd_er_halt( BAD_REG_HLT ); /* halt on the error */
276: if( loop_on_err ) {
277: force_loop = TRUE; /* set the force loop flag */
278: asm("brw _ldd_4_lp1");; /* and loop on the error */
279: } /* end of loop on error */
280: } /* end of register corruption error */
281: } /* end of subtest 4 */
282:
283:
284:
285: /************************************************************************
286: *
287: * SUBTEST 5 - Check for PSL corruption (ldd)
288: *
289: ************************************************************************/
290: ldd_5()
291: {
292: force_loop = FALSE; /* clear force_loop flg */
293: subtest = 5;
294: status_index = 0;
295: fill_reg_buf( load_regs ); /* get patterns for regs */
296: for( index = 0; index < 3; index++ ) {
297: dbl_ld_acc = ldd_1_data[index].ld; /* get value to load */
298: sgl_dummy1 = status_array[status_index]; /* status = +, -, 0 */
299: /*
300: * If LOOP ON ERROR is set, this is the loop for this subtest.
301: * The force loop flag is set after the first error.
302: */
303: asm("_ldd_5_lp1:");
304: asm("tstl _sgl_dummy1"); /* set the PSL status */
305: asm("movpsl _init_psl"); /* save the initial PSL */
306: asm("nop");
307: asm("ldd _dbl_ld_acc"); /* load the accumulator */
308: asm("nop");
309: asm("movpsl _psl_val"); /* save the final PSL */
310: asm("nop");
311: asm("std _dbl_st_acc"); /* save the accumulator */
312: if( force_loop )
313: asm("brb _ldd_5_lp1");; /* loop on the error */
314: /*
315: * Now compare the final PSL to the initial PSL -they should be the same
316: */
317: exp_psl = init_psl;
318: if( psl_val != exp_psl ) {
319: errcnt++; /* bump the error count */
320: if( prt_error ) {
321: writes(" \n"); /* start a new print line */
322: writes("cycle: ");
323: writed( cycle );
324: writes(" LDD_STD test ");
325: writed( test_no );
326: writes(", subtest 5 - INCORRECT FINAL PSL - LDD\n");
327: print_ldd_data(); /* print the operands */
328: writes("\ninitial PSL = ");
329: write32h( init_psl );
330: writes(", final PSL = ");
331: write32h( psl_val );
332: writes(", expected PSL = ");
333: write32h( exp_psl );
334: writes("\n");
335: }
336: if( halt_flg )
337: ldd_er_halt( BAD_PSL_HLT ); /* halt on the error */
338: if( loop_on_err ) {
339: force_loop = TRUE; /* set the force loop flag */
340: asm("brw _ldd_5_lp1");; /* and loop on the error */
341: } /* end of loop on error */
342: } /* end of PSL corruption error */
343: } /* end of WHILE loop */
344: } /* end of subtest 5 */
345:
346:
347:
348: /************************************************************************
349: *
350: * SUBTEST 6 - STD status test
351: *
352: ************************************************************************/
353: ldd_6()
354: {
355: force_loop = FALSE;
356: index = 0; /* clear the data index */
357: status_index = 0; /* clear the status index */
358: do {
359: dbl_ld_acc = ldd_1_data[index].ld; /* get the dbl operand */
360: sgl_dummy1 = status_array[status_index]; /* array = +, -, 0 */
361: /*
362: * If LOOP ON ERROR is set, this is the loop for this subtest.
363: * The force loop flag is set after the first error.
364: */
365: asm("_ldd_6_lp1:");
366: asm("ldd _dbl_ld_acc"); /* load the operand */
367: asm("tstl _sgl_dummy1"); /* generate initial status */
368: asm("movpsl _init_psl"); /* save the initial status */
369: asm("std _dbl_st_acc"); /* save the accumulator */
370: asm("movpsl _psl_val"); /* save the final status */
371: if( force_loop ) /* loop? */
372: asm("jmp _ldd_6_lp1");; /* run the loop again */
373: exp_psl = init_psl; /* get the initial PSL */
374: exp_psl &= 0xfffffff3; /* clear ZERO, NEGATIVE */
375: sgl_dummy2 = dbl_ld_acc.m; /* get MSW of the operand */
376: /* if( !no_fpp_wcs ) /* why? */
377: sgl_dummy2 &= 0xff800000; /* clear the fraction part */
378: if( !sgl_dummy2 )
379: exp_psl |= PSL_Z; /* expect the ZERO bit set */
380: if( sgl_dummy2 < 0 )
381: exp_psl |= PSL_N; /* expect the NEG bit set */
382: if( psl_val != exp_psl ) { /* COMPARE the values */
383: errcnt++; /* bump the error count */
384: if( prt_error ) {
385: writes(" \n"); /* start a new print line */
386: writes("cycle: ");
387: writed( cycle );
388: writes(" LDD_STD test ");
389: writed( test_no );
390: writes(", subtest 6 - INCORRECT FINAL PSL - STD\n");
391: print_ldd_data(); /* print the operands */
392: writes("\ninitial PSL = ");
393: write32h( init_psl );
394: writes(", final PSL = ");
395: write32h( psl_val );
396: writes(", expected PSL = ");
397: write32h( exp_psl );
398: writes("\n");
399: }
400: if( halt_flg )
401: ldd_er_halt( BAD_PSL_HLT ); /* halt on the error */
402: if( loop_on_err ) {
403: force_loop = TRUE; /* set the force loop flag */
404: asm("brw _ldd_6_lp1");; /* and loop */
405: }; /* end of loop-on-error */
406: } /* end of compare error */
407: if( ++status_index >= 3 )
408: status_index = 0; /* reset the status index */
409: } while( index++ < max_ldd_1_index );
410: } /* end of subtest 6 */
411:
412:
413:
414: /**************************************************************************
415: *
416: * PRINT THE DATA AND STORE RESULTS
417: *
418: * Acc loaded = xxxxxxxx xxxxxxxx, Acc stored = xxxxxxxx xxxxxxxx, index = xx
419: **************************************************************************/
420: print_ldd_data()
421: {
422: writes(" Acc loaded = ");
423: write32h( dbl_ld_acc.m );
424: writec(' ');
425: write32h( dbl_ld_acc.l );
426: writes(", Acc stored = ");
427: write32h( dbl_st_acc.m );
428: writec(' ');
429: write32h( dbl_st_acc.l );
430: }
431:
432:
433:
434: /**************************************************************************
435: *
436: * HALT ON ERROR ROUTINE
437: *
438: **************************************************************************/
439: ldd_er_halt( halt_code )
440: int halt_code;
441: {
442: sgl_value_1 = dbl_ld_acc.m;
443: sgl_value_2 = dbl_ld_acc.l;
444: sgl_value_3 = dbl_st_acc.m;
445: sgl_value_4 = dbl_st_acc.l;
446: sgl_dummy1 = halt_code; /* get the error type */
447: asm("movl _test_no,r0"); /* r0 = test number */
448: asm("movl _subtest,r1"); /* r1 = subtest number */
449: asm("movl _sgl_dummy1,r2"); /* r2 = error code */
450: asm("movl _cycle,r3"); /* r3 = cycle count */
451: asm("movl _sgl_value_1,r4"); /* r4 = MS operand */
452: asm("movl _sgl_value_2,r5"); /* r5 = LS operand */
453: asm("movl _sgl_value_3,r6"); /* r6 = MS actual value */
454: asm("movl _sgl_value_4,r7"); /* r7 = LS actual value */
455: if( halt_code == BAD_ACC_HLT ) {
456: sgl_value_1 = dbl_expected.m;
457: sgl_value_2 = dbl_expected.l;
458: asm("movl _sgl_value_1,r8"); /* r8 = MS expected */
459: asm("movl _sgl_value_2,r9"); /* r9 = LS expected */
460: asm("movl _index,r10"); /* r10 = data index */
461: } else
462: if( halt_code == BAD_REG_HLT ) {
463: sgl_dummy1 = load_regs[index2];
464: sgl_dummy2 = store_regs[index2];
465: asm("movl _index2,r8"); /* r8 = bad register # */
466: asm("movl _sgl_dummy2,r9"); /* r9 = actual value */
467: asm("movl _sgl_dummy1,r10"); /* r10 = expected value */
468: } else
469: if( halt_code == BAD_PSL_HLT ) {
470: asm("movl _init_psl,r8"); /* r8 = initial PSL */
471: asm("movl _psl_val,r9"); /* r9 = final PSL */
472: asm("movl _exp_psl,r10"); /* r10 = expected PSL */
473: };
474: asm("halt"); /* HALT ... */
475: }
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