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Up to [Power 6/32 Unix Tahoe 4.2BSD] / cci / d / macro4|
Return to ldd_std.c CVS log | Up to [Power 6/32 Unix Tahoe 4.2BSD] / cci / d / macro4 |
Power 6/32 Unix version 1.21
#include "fpp_defs.h"
/*****************************************************************************
*
* LDD_STD - DOUBLE PRECISION FLOATING POINT LOAD_STORE TEST
*
*****************************************************************************/
ldd()
{
asm(".globl _ldd_t");
asm("_ldd_t:"); /* entry address */
if( ( cycle == 1 ) && ( prt_hdrs ) ) /* print headers on 1st pass */
writes("\n LDD_STD");
ldd_1(); /* load through a register */
ldd_2(); /* load through the cache */
ldd_3(); /* register stability ldd */
ldd_4(); /* register stability std */
ldd_5(); /* PSL stability test ldd */
ldd_6(); /* PSL stability test std */
asm("jmp *return"); /* return to the test monitor */
}
/************************************************************************
*
* SUBTEST 1 - load through a register
*
************************************************************************/
ldd_1()
{
force_loop = FALSE;
subtest = 1;
for( index = 0; index < max_ldd_1_index; index++ ) {
dbl_ld_acc = ldd_1_data[index].ld; /* get the operand */
if( dbl_ld_acc.m & 0x7f800000 )
dbl_expected = dbl_ld_acc; /* expected = loaded */
else {
dbl_expected.m = 0; /* expect a '0' */
dbl_expected.l = 0;
}
sgl_value_1 = dbl_ld_acc.m;
sgl_value_2 = dbl_ld_acc.l;
/*
* If LOOP ON ERROR is set, this is the loop for this subtest.
* The force loop flag is set after the first error.
*/
asm("_ldd_1_lp1:");
asm("movl _sgl_value_1,r4"); /* move the operand to r4/r5 */
asm("movl _sgl_value_2,r5");
asm("ldd r4"); /* load the value */
asm("nop");
asm("std r8"); /* store the result in R8 */
if( force_loop )
asm("brb _ldd_1_lp1");; /* loop on the error */
/*
* end error loop - test the results
*/
asm("movl r8,_dbl_st_acc"); /* save the stored data */
asm("movl r9,_dbl_st_acc+4");
if( ( dbl_st_acc.m != dbl_expected.m ) || /* COMPARE the */
( dbl_st_acc.l != dbl_expected.l ) ) { /* values */
errcnt++; /* bump the error count */
if( prt_error ) {
writes(" \n"); /* start a new print line */
writes("cycle: ");
writed( cycle );
writes(" LDD_STD test ");
writed( test_no );
writes(", subtest 1 (Reg. Data) - BAD FINAL ACC\n");
print_ldd_data();
writes(", index = ");
writed( index );
writec('\n');
writes(" Acc expected = ");
write32h( dbl_expected.m );
writec(' ');
write32h(dbl_expected.l );
writec('\n');
}
if( halt_flg )
ldd_er_halt( BAD_ACC_HLT ); /* halt on the error */
if( loop_on_err ) {
force_loop = TRUE; /* set the force loop flag */
asm("brw _ldd_1_lp1");; /* and loop on the error */
} /* end of loop on error */
} /* end of compare error */
} /* end of WHILE loop */
} /* end of subtest 1 */
/************************************************************************
*
* SUBTEST 2 - load through cache
*
************************************************************************/
ldd_2()
{
force_loop = FALSE;
subtest = 2;
for( index = 0; index < max_ldd_1_index; index++ ) {
dbl_ld_acc = ldd_1_data[index].ld; /* get the operand */
if( dbl_ld_acc.m & 0x7f800000 )
dbl_expected = dbl_ld_acc; /* expected = loaded */
else {
dbl_expected.m = 0; /* expect a '0' */
dbl_expected.l = 0;
}
/*
* If LOOP ON ERROR is set, this is the loop for this subtest.
* The force loop flag is set after the first error.
*/
asm("_ldd_2_lp1:");
asm("ldd _dbl_ld_acc"); /* load the value */
asm("nop");
asm("std _dbl_st_acc"); /* store the result */
if( force_loop )
asm("brb _ldd_2_lp1");; /* loop on the error */
/*
* end error loop - test the results
*/
if( ( dbl_st_acc.m != dbl_expected.m ) || /* COMPARE the */
( dbl_st_acc.l != dbl_expected.l ) ) { /* values */
errcnt++; /* bump the error count */
if( prt_error ) {
writes(" \n"); /* start a new print line */
writes("cycle: ");
writed( cycle );
writes(" LDD_STD test ");
writed( test_no );
writes(", subtest 2 (Cache Data) - BAD FINAL ACC\n");
print_ldd_data();
writes(", index = ");
writed( index );
writec('\n');
writes(" Acc expected = ");
write32h( dbl_expected.m );
writec(' ');
write32h( dbl_expected.l );
writec('\n');
}
if( halt_flg )
ldd_er_halt( BAD_ACC_HLT ); /* halt on the error */
if( loop_on_err ) {
force_loop = TRUE; /* set the force loop flag */
asm("brw _ldd_2_lp1");; /* and loop on the error */
} /* end of loop on error */
} /* end of compare error */
} /* end of WHILE loop */
} /* end of subtest 2 */
/************************************************************************
*
* SUBTEST 3 - Check for register corruption (ldd)
*
************************************************************************/
ldd_3()
{
force_loop = FALSE; /* clear force_loop flg */
subtest = 3;
fill_reg_buf( load_regs ); /* get patterns for regs */
index = 0;
dbl_ld_acc = ldd_1_data[0].ld; /* get value to load */
if( dbl_ld_acc.m & 0x7f800000 )
dbl_expected = dbl_ld_acc; /* expected = loaded */
else {
dbl_expected.m = 0; /* expect a '0' */
dbl_expected.l = 0;
}
/*
* If LOOP ON ERROR is set, this is the loop for this subtest.
* The force loop flag is set after the first error.
*/
asm("_ldd_3_lp1:");
asm("loadr $0x1fff,_load_regs"); /* load regs 0 - 12 */
asm("nop");
asm("ldd _dbl_ld_acc"); /* load the accumulator */
asm("nop");
asm("storer $0x1fff,_store_regs"); /* store regs 0 - 12 */
asm("nop");
asm("std _dbl_st_acc"); /* save the accumulator */
if( force_loop )
asm("brb _ldd_3_lp1");; /* loop on the error */
/*
* Now compare the stored register values to those that were loaded
*/
index2 = 0;
while( (load_regs[index2] == store_regs[index2]) && (index2 < 13) )
index2++; /* check reg values */
if( index2 < 13 ) { /* error if index2 < 13 */
errcnt++; /* bump the error count */
if( prt_error ) {
writes(" \n"); /* start a new print line */
writes("cycle: ");
writed( cycle );
writes(" LDD_STD test ");
writed( test_no );
writes(", subtest 3 - A REGISTER WAS MODIFIED\n");
print_ldd_data(); /* print the operands */
writes("\nregister "); /* print the information */
writed( index2 ); /* about the corrupted */
writes(" = "); /* register */
write32h( store_regs[index2] );
writes(", should be = ");
write32h( load_regs[index2] );
writes("\n");
}
if( halt_flg )
ldd_er_halt( BAD_REG_HLT ); /* halt on the error */
if( loop_on_err ) {
force_loop = TRUE; /* set the force loop flag */
asm("brw _ldd_3_lp1");; /* and loop on the error */
} /* end of loop on error */
} /* end of register corruption error */
} /* end of subtest 3 */
/************************************************************************
*
* SUBTEST 4 - Check for register corruption (std)
*
************************************************************************/
ldd_4()
{
force_loop = FALSE; /* clear force_loop flg */
subtest = 4;
fill_reg_buf( load_regs ); /* get patterns for regs */
index = 0;
dbl_ld_acc = ldd_1_data[0].ld; /* get value to store */
/*
* If LOOP ON ERROR is set, this is the loop for this subtest.
* The force loop flag is set after the first error.
*/
asm("_ldd_4_lp1:");
asm("ldd _dbl_ld_acc"); /* load the accumulator */
asm("nop");
asm("loadr $0x1fff,_load_regs"); /* load regs 0 - 12 */
asm("nop");
asm("std _dbl_st_acc"); /* save the accumulator */
asm("nop");
asm("storer $0x1fff,_store_regs"); /* store regs 0 - 12 */
if( force_loop )
asm("brb _ldd_4_lp1");; /* loop on the error */
/*
* Now compare the stored register values to those that were loaded
*/
index2 = 0;
while( (load_regs[index2] == store_regs[index2]) && (index2 < 13) )
index2++; /* check reg values */
if( index2 < 13 ) { /* error if index2 < 13 */
errcnt++; /* bump the error count */
if( prt_error ) {
writes(" \n"); /* start a new print line */
writes("cycle: ");
writed( cycle );
writes(" LDD_STD test ");
writed( test_no );
writes(", subtest 4 - A REGISTER WAS MODIFIED\n");
print_ldd_data(); /* print the operands */
writes("\nregister "); /* print the information */
writed( index2 ); /* about the corrupted */
writes(" = "); /* register */
write32h( store_regs[index2] );
writes(", should be = ");
write32h( load_regs[index2] );
writes("\n");
}
if( halt_flg )
ldd_er_halt( BAD_REG_HLT ); /* halt on the error */
if( loop_on_err ) {
force_loop = TRUE; /* set the force loop flag */
asm("brw _ldd_4_lp1");; /* and loop on the error */
} /* end of loop on error */
} /* end of register corruption error */
} /* end of subtest 4 */
/************************************************************************
*
* SUBTEST 5 - Check for PSL corruption (ldd)
*
************************************************************************/
ldd_5()
{
force_loop = FALSE; /* clear force_loop flg */
subtest = 5;
status_index = 0;
fill_reg_buf( load_regs ); /* get patterns for regs */
for( index = 0; index < 3; index++ ) {
dbl_ld_acc = ldd_1_data[index].ld; /* get value to load */
sgl_dummy1 = status_array[status_index]; /* status = +, -, 0 */
/*
* If LOOP ON ERROR is set, this is the loop for this subtest.
* The force loop flag is set after the first error.
*/
asm("_ldd_5_lp1:");
asm("tstl _sgl_dummy1"); /* set the PSL status */
asm("movpsl _init_psl"); /* save the initial PSL */
asm("nop");
asm("ldd _dbl_ld_acc"); /* load the accumulator */
asm("nop");
asm("movpsl _psl_val"); /* save the final PSL */
asm("nop");
asm("std _dbl_st_acc"); /* save the accumulator */
if( force_loop )
asm("brb _ldd_5_lp1");; /* loop on the error */
/*
* Now compare the final PSL to the initial PSL -they should be the same
*/
exp_psl = init_psl;
if( psl_val != exp_psl ) {
errcnt++; /* bump the error count */
if( prt_error ) {
writes(" \n"); /* start a new print line */
writes("cycle: ");
writed( cycle );
writes(" LDD_STD test ");
writed( test_no );
writes(", subtest 5 - INCORRECT FINAL PSL - LDD\n");
print_ldd_data(); /* print the operands */
writes("\ninitial PSL = ");
write32h( init_psl );
writes(", final PSL = ");
write32h( psl_val );
writes(", expected PSL = ");
write32h( exp_psl );
writes("\n");
}
if( halt_flg )
ldd_er_halt( BAD_PSL_HLT ); /* halt on the error */
if( loop_on_err ) {
force_loop = TRUE; /* set the force loop flag */
asm("brw _ldd_5_lp1");; /* and loop on the error */
} /* end of loop on error */
} /* end of PSL corruption error */
} /* end of WHILE loop */
} /* end of subtest 5 */
/************************************************************************
*
* SUBTEST 6 - STD status test
*
************************************************************************/
ldd_6()
{
force_loop = FALSE;
index = 0; /* clear the data index */
status_index = 0; /* clear the status index */
do {
dbl_ld_acc = ldd_1_data[index].ld; /* get the dbl operand */
sgl_dummy1 = status_array[status_index]; /* array = +, -, 0 */
/*
* If LOOP ON ERROR is set, this is the loop for this subtest.
* The force loop flag is set after the first error.
*/
asm("_ldd_6_lp1:");
asm("ldd _dbl_ld_acc"); /* load the operand */
asm("tstl _sgl_dummy1"); /* generate initial status */
asm("movpsl _init_psl"); /* save the initial status */
asm("std _dbl_st_acc"); /* save the accumulator */
asm("movpsl _psl_val"); /* save the final status */
if( force_loop ) /* loop? */
asm("jmp _ldd_6_lp1");; /* run the loop again */
exp_psl = init_psl; /* get the initial PSL */
exp_psl &= 0xfffffff3; /* clear ZERO, NEGATIVE */
sgl_dummy2 = dbl_ld_acc.m; /* get MSW of the operand */
/* if( !no_fpp_wcs ) /* why? */
sgl_dummy2 &= 0xff800000; /* clear the fraction part */
if( !sgl_dummy2 )
exp_psl |= PSL_Z; /* expect the ZERO bit set */
if( sgl_dummy2 < 0 )
exp_psl |= PSL_N; /* expect the NEG bit set */
if( psl_val != exp_psl ) { /* COMPARE the values */
errcnt++; /* bump the error count */
if( prt_error ) {
writes(" \n"); /* start a new print line */
writes("cycle: ");
writed( cycle );
writes(" LDD_STD test ");
writed( test_no );
writes(", subtest 6 - INCORRECT FINAL PSL - STD\n");
print_ldd_data(); /* print the operands */
writes("\ninitial PSL = ");
write32h( init_psl );
writes(", final PSL = ");
write32h( psl_val );
writes(", expected PSL = ");
write32h( exp_psl );
writes("\n");
}
if( halt_flg )
ldd_er_halt( BAD_PSL_HLT ); /* halt on the error */
if( loop_on_err ) {
force_loop = TRUE; /* set the force loop flag */
asm("brw _ldd_6_lp1");; /* and loop */
}; /* end of loop-on-error */
} /* end of compare error */
if( ++status_index >= 3 )
status_index = 0; /* reset the status index */
} while( index++ < max_ldd_1_index );
} /* end of subtest 6 */
/**************************************************************************
*
* PRINT THE DATA AND STORE RESULTS
*
* Acc loaded = xxxxxxxx xxxxxxxx, Acc stored = xxxxxxxx xxxxxxxx, index = xx
**************************************************************************/
print_ldd_data()
{
writes(" Acc loaded = ");
write32h( dbl_ld_acc.m );
writec(' ');
write32h( dbl_ld_acc.l );
writes(", Acc stored = ");
write32h( dbl_st_acc.m );
writec(' ');
write32h( dbl_st_acc.l );
}
/**************************************************************************
*
* HALT ON ERROR ROUTINE
*
**************************************************************************/
ldd_er_halt( halt_code )
int halt_code;
{
sgl_value_1 = dbl_ld_acc.m;
sgl_value_2 = dbl_ld_acc.l;
sgl_value_3 = dbl_st_acc.m;
sgl_value_4 = dbl_st_acc.l;
sgl_dummy1 = halt_code; /* get the error type */
asm("movl _test_no,r0"); /* r0 = test number */
asm("movl _subtest,r1"); /* r1 = subtest number */
asm("movl _sgl_dummy1,r2"); /* r2 = error code */
asm("movl _cycle,r3"); /* r3 = cycle count */
asm("movl _sgl_value_1,r4"); /* r4 = MS operand */
asm("movl _sgl_value_2,r5"); /* r5 = LS operand */
asm("movl _sgl_value_3,r6"); /* r6 = MS actual value */
asm("movl _sgl_value_4,r7"); /* r7 = LS actual value */
if( halt_code == BAD_ACC_HLT ) {
sgl_value_1 = dbl_expected.m;
sgl_value_2 = dbl_expected.l;
asm("movl _sgl_value_1,r8"); /* r8 = MS expected */
asm("movl _sgl_value_2,r9"); /* r9 = LS expected */
asm("movl _index,r10"); /* r10 = data index */
} else
if( halt_code == BAD_REG_HLT ) {
sgl_dummy1 = load_regs[index2];
sgl_dummy2 = store_regs[index2];
asm("movl _index2,r8"); /* r8 = bad register # */
asm("movl _sgl_dummy2,r9"); /* r9 = actual value */
asm("movl _sgl_dummy1,r10"); /* r10 = expected value */
} else
if( halt_code == BAD_PSL_HLT ) {
asm("movl _init_psl,r8"); /* r8 = initial PSL */
asm("movl _psl_val,r9"); /* r9 = final PSL */
asm("movl _exp_psl,r10"); /* r10 = expected PSL */
};
asm("halt"); /* HALT ... */
}
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