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Up to [Power 6/32 Unix Tahoe 4.2BSD] / cci / d / macro4|
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Power 6/32 Unix version 1.21
1 00000000 LL0:
2 00000000 .data
3 00000c20 * .text
4 00000000 .align 1
5 00000000 .globl _ldd
6 00000000 _ldd:
7 00015C40 0000 .word L215
8 00015C42 #
9 00015C42 # #include "fpp_defs.h"
10 00015C42 #
11 00015C42 #
12 00015C42 # /*****************************************************************************
13 00015C42 # *
14 00015C42 # * LDD_STD - DOUBLE PRECISION FLOATING POINT LOAD_STORE TEST
15 00015C42 # *
16 00015C42 # *****************************************************************************/
17 00015C42 # ldd()
18 00015C42 # {
19 00015C42 11 4f jbr L217
20 00015C44 L218:
21 00015C44 # asm(".globl _ldd_t");
22 00015C44 .globl _ldd_t
23 00015C44 # asm("_ldd_t:"); /* entry address */
24 00015C44 _ldd_t:
25 00015C44 # if( ( cycle == 1 ) && ( prt_hdrs ) ) /* print headers on 1st pass */
26 00015C44 1d effffffff6 01 cmpl _cycle,$1
27 00015C4B 21 15 jneq L219
28 00015C4D 5d efffffffed tstl _prt_hdrs
29 00015C53 31 0d jeql L219
30 00015C55 # writes("\n LDD_STD");
31 00015C55 .data 1
32 00000c20 * L221:
33 00000c20 * 0A204C44445F53544400 .ascii "\12 LDD_STD\0"
34 00000c2a * .text
35 00015C55 dd 8f00000c20 pushl $L221
36 00015C5B fe 08 efffffffde callf $8,_writes
37 00015C62 # ldd_1(); /* load through a register */
38 00015C62 L219:
39 00015C62 fe 04 ef0000002d callf $4,_ldd_1
40 00015C69 # ldd_2(); /* load through the cache */
41 00015C69 fe 04 ef000001ee callf $4,_ldd_2
42 00015C70 # ldd_3(); /* register stability ldd */
43 00015C70 fe 04 ef00000385 callf $4,_ldd_3
44 00015C77 # ldd_4(); /* register stability std */
45 00015C77 fe 04 ef0000054e callf $4,_ldd_4
46 00015C7E # ldd_5(); /* PSL stability test ldd */
47 00015C7E fe 04 ef000006e5 callf $4,_ldd_5
48 00015C85 # ldd_6(); /* PSL stability test std */
49 00015C85 fe 04 ef0000087e callf $4,_ldd_6
50 00015C8C # asm("jmp *return"); /* return to the test monitor */
51 00015C8C 71 ffffffffae jmp *return
52 00015C92 # }
53 00015C92 40 ret#2
54 00015C93 .set L215,0x0
55 00015C93 L217:
56 00015C93 11 af jbr L218
57 00015C95 .data
58 00000c20 * .text
59 00015C95 00 .align 1
60 00015C96 .globl _ldd_1
61 00015C96 _ldd_1:
62 00015C96 0000 .word L228
63 00015C98 #
64 00015C98 #
65 00015C98 #
66 00015C98 # /************************************************************************
67 00015C98 # *
68 00015C98 # * SUBTEST 1 - load through a register
69 00015C98 # *
70 00015C98 # ************************************************************************/
71 00015C98 # ldd_1()
72 00015C98 # {
73 00015C98 13 01bf jbr L230
74 00015C9B L231:
75 00015C9B # force_loop = FALSE;
76 00015C9B 4d efffffff9f clrl _force_loop
77 00015CA1 # subtest = 1;
78 00015CA1 0d 01 efffffff98 movl $1,_subtest
79 00015CA8 # for( index = 0; index < max_ldd_1_index; index++ ) {
80 00015CA8 4d efffffff92 clrl _index
81 00015CAE L234:
82 00015CAE 1d efffffff8c efffffff87 cmpl _index,_max_ldd_1_index
83 00015CB9 91 03 13 019b jgeq L233
84 00015CBE # dbl_ld_acc = ldd_1_data[index].ld; /* get the operand */
85 00015CBE 48 04 efffffff7b 50 shll $4,_index,r0
86 00015CC6 0c 8f00000000 50 addl2 $_ldd_1_data,r0
87 00015CCD 0d a004 efffffff6f movl 4(r0),_dbl_ld_acc+4
88 00015CD5 0d 60 efffffff64 movl (r0),_dbl_ld_acc
89 00015CDC # if( dbl_ld_acc.m & 0x7f800000 )
90 00015CDC 3d 8f7f800000 efffffff59 bitl $2139095040,_dbl_ld_acc
91 00015CE7 31 18 jeql L235
92 00015CE9 # dbl_expected = dbl_ld_acc; /* expected = loaded */
93 00015CE9 0d efffffff55 efffffff50 movl _dbl_ld_acc+4,_dbl_expected+4
94 00015CF4 0d efffffff46 efffffff41 movl _dbl_ld_acc,_dbl_expected
95 00015CFF # else {
96 00015CFF 11 0c jbr L236
97 00015D01 L235:
98 00015D01 # dbl_expected.m = 0; /* expect a '0' */
99 00015D01 4d efffffff39 clrl _dbl_expected
100 00015D07 # dbl_expected.l = 0;
101 00015D07 4d efffffff37 clrl _dbl_expected+4
102 00015D0D # }
103 00015D0D L236:
104 00015D0D # sgl_value_1 = dbl_ld_acc.m;
105 00015D0D 0d efffffff2d efffffff28 movl _dbl_ld_acc,_sgl_value_1
106 00015D18 # sgl_value_2 = dbl_ld_acc.l;
107 00015D18 0d efffffff26 efffffff1d movl _dbl_ld_acc+4,_sgl_value_2
108 00015D23 # /*
109 00015D23 # * If LOOP ON ERROR is set, this is the loop for this subtest.
110 00015D23 # * The force loop flag is set after the first error.
111 00015D23 # */
112 00015D23 # asm("_ldd_1_lp1:");
113 00015D23 _ldd_1_lp1:
114 00015D23 # asm("movl _sgl_value_1,r4"); /* move the operand to r4/r5 */
115 00015D23 0d efffffff17 54 movl _sgl_value_1,r4
116 00015D2A # asm("movl _sgl_value_2,r5");
117 00015D2A 0d efffffff10 55 movl _sgl_value_2,r5
118 00015D31 # asm("ldd r4"); /* load the value */
119 00015D31 07 54 ldd r4
120 00015D33 # asm("nop");
121 00015D33 10 nop
122 00015D34 # asm("std r8"); /* store the result in R8 */
123 00015D34 27 58 std r8
124 00015D36 # if( force_loop )
125 00015D36 5d efffffff04 tstl _force_loop
126 00015D3C 31 02 jeql L237
127 00015D3E # asm("brb _ldd_1_lp1");; /* loop on the error */
128 00015D3E 11 e3 brb _ldd_1_lp1
129 00015D40 L237:
130 00015D40 # /*
131 00015D40 # * end error loop - test the results
132 00015D40 # */
133 00015D40 # asm("movl r8,_dbl_st_acc"); /* save the stored data */
134 00015D40 0d 58 effffffef9 movl r8,_dbl_st_acc
135 00015D47 # asm("movl r9,_dbl_st_acc+4");
136 00015D47 0d 59 effffffef6 movl r9,_dbl_st_acc+4
137 00015D4E # if( ( dbl_st_acc.m != dbl_expected.m ) || /* COMPARE the */
138 00015D4E # ( dbl_st_acc.l != dbl_expected.l ) ) { /* values */
139 00015D4E 1d effffffeec effffffee7 cmpl _dbl_st_acc,_dbl_expected
140 00015D59 21 10 jneq L9999
141 00015D5B 1d effffffee3 effffffede cmpl _dbl_st_acc+4,_dbl_expected+4
142 00015D66 21 03 13 00e5 jeql L238
143 00015D6B L9999:
144 00015D6B # errcnt++; /* bump the error count */
145 00015D6B 6d effffffecf incl _errcnt
146 00015D71 # if( prt_error ) {
147 00015D71 5d effffffec9 tstl _prt_error
148 00015D77 21 03 13 00b1 jeql L239
149 00015D7C # writes(" \n"); /* start a new print line */
150 00015D7C .data 1
151 00000c2a * L240:
152 00000c2a * 200A00 .ascii " \12\0"
153 00000c2d * .text
154 00015D7C dd 8f00000c2a pushl $L240
155 00015D82 fe 08 effffffeb7 callf $8,_writes
156 00015D89 # writes("cycle: ");
157 00015D89 .data 1
158 00000c2d * L241:
159 00000c2d * 6379636C653A2000 .ascii "cycle: \0"
160 00000c35 * .text
161 00015D89 dd 8f00000c2d pushl $L241
162 00015D8F fe 08 effffffeaa callf $8,_writes
163 00015D96 # writed( cycle );
164 00015D96 dd effffffea4 pushl _cycle
165 00015D9C fe 08 effffffe9d callf $8,_writed
166 00015DA3 # writes(" LDD_STD test ");
167 00015DA3 .data 1
168 00000c35 * L243:
169 00000c35 * 20204C44445F5354442074657 .ascii " LDD_STD test \0"
3742000
170 00000c45 * .text
171 00015DA3 dd 8f00000c35 pushl $L243
172 00015DA9 fe 08 effffffe90 callf $8,_writes
173 00015DB0 # writed( test_no );
174 00015DB0 dd effffffe8a pushl _test_no
175 00015DB6 fe 08 effffffe83 callf $8,_writed
176 00015DBD # writes(", subtest 1 (Reg. Data) - BAD FINAL ACC\n");
177 00015DBD .data 1
178 00000c45 * L244:
179 00000c45 * 2C20737562746573742031202 .ascii ", subtest 1 (Reg. Data) - BAD FINAL ACC\12\0"
85265672E204461746129202D
204241442046494E414C20414
3430A00
180 00000c6e * .text
181 00015DBD dd 8f00000c45 pushl $L244
182 00015DC3 fe 08 effffffe76 callf $8,_writes
183 00015DCA # print_ldd_data();
184 00015DCA fe 04 ef0000091d callf $4,_print_ldd_data
185 00015DD1 # writes(", index = ");
186 00015DD1 .data 1
187 00000c6e * L246:
188 00000c6e * 2C20696E646578203D2000 .ascii ", index = \0"
189 00000c79 * .text
190 00015DD1 dd 8f00000c6e pushl $L246
191 00015DD7 fe 08 effffffe62 callf $8,_writes
192 00015DDE # writed( index );
193 00015DDE dd effffffe5c pushl _index
194 00015DE4 fe 08 effffffe55 callf $8,_writed
195 00015DEB # writec('\n');
196 00015DEB dd 0a pushl $10
197 00015DED fe 08 effffffe4c callf $8,_writec
198 00015DF4 # writes(" Acc expected = ");
199 00015DF4 .data 1
200 00000c79 * L248:
201 00000c79 * 2020202020202020202020202 .ascii " Acc expected = \0"
0202020202020202020202020
2020202020202041636320657
8706563746564203D2000
202 00000ca9 * .text
203 00015DF4 dd 8f00000c79 pushl $L248
204 00015DFA fe 08 effffffe3f callf $8,_writes
205 00015E01 # write32h( dbl_expected.m );
206 00015E01 dd effffffe39 pushl _dbl_expected
207 00015E07 fe 08 effffffe32 callf $8,_write32h
208 00015E0E # writec(' ');
209 00015E0E dd 20 pushl $32
210 00015E10 fe 08 effffffe29 callf $8,_writec
211 00015E17 # write32h(dbl_expected.l );
212 00015E17 dd effffffe27 pushl _dbl_expected+4
213 00015E1D fe 08 effffffe1c callf $8,_write32h
214 00015E24 # writec('\n');
215 00015E24 dd 0a pushl $10
216 00015E26 fe 08 effffffe13 callf $8,_writec
217 00015E2D # }
218 00015E2D # if( halt_flg )
219 00015E2D L239:
220 00015E2D 5d effffffe0d tstl _halt_flg
221 00015E33 31 09 jeql L250
222 00015E35 # ldd_er_halt( BAD_ACC_HLT ); /* halt on the error */
223 00015E35 dd 01 pushl $1
224 00015E37 fe 08 ef00000918 callf $8,_ldd_er_halt
225 00015E3E # if( loop_on_err ) {
226 00015E3E L250:
227 00015E3E 5d effffffdfc tstl _loop_on_err
228 00015E44 31 0a jeql L252
229 00015E46 # force_loop = TRUE; /* set the force loop flag */
230 00015E46 0d 01 effffffdf3 movl $1,_force_loop
231 00015E4D # asm("brw _ldd_1_lp1");; /* and loop on the error */
232 00015E4D 13 fed3 brw _ldd_1_lp1
233 00015E50 # } /* end of loop on error */
234 00015E50 # } /* end of compare error */
235 00015E50 L252:
236 00015E50 # } /* end of WHILE loop */
237 00015E50 L238:
238 00015E50 L232:
239 00015E50 6d effffffdea incl _index
240 00015E56 13 fe55 jbr L234
241 00015E59 L233:
242 00015E59 # } /* end of subtest 1 */
243 00015E59 40 ret#2
244 00015E5A .set L228,0x0
245 00015E5A L230:
246 00015E5A 13 fe3e jbr L231
247 00015E5D .data
248 00000c20 * .text
249 00015E5D 00 .align 1
250 00015E5E .globl _ldd_2
251 00015E5E _ldd_2:
252 00015E5E 0000 .word L253
253 00015E60 #
254 00015E60 #
255 00015E60 #
256 00015E60 # /************************************************************************
257 00015E60 # *
258 00015E60 # * SUBTEST 2 - load through cache
259 00015E60 # *
260 00015E60 # ************************************************************************/
261 00015E60 # ldd_2()
262 00015E60 # {
263 00015E60 13 0195 jbr L255
264 00015E63 L256:
265 00015E63 # force_loop = FALSE;
266 00015E63 4d effffffdd7 clrl _force_loop
267 00015E69 # subtest = 2;
268 00015E69 0d 02 effffffdd0 movl $2,_subtest
269 00015E70 # for( index = 0; index < max_ldd_1_index; index++ ) {
270 00015E70 4d effffffdca clrl _index
271 00015E76 L259:
272 00015E76 1d effffffdc4 effffffdbf cmpl _index,_max_ldd_1_index
273 00015E81 91 03 13 0171 jgeq L258
274 00015E86 # dbl_ld_acc = ldd_1_data[index].ld; /* get the operand */
275 00015E86 48 04 effffffdb3 50 shll $4,_index,r0
276 00015E8E 0c 8f00000000 50 addl2 $_ldd_1_data,r0
277 00015E95 0d a004 effffffda7 movl 4(r0),_dbl_ld_acc+4
278 00015E9D 0d 60 effffffd9c movl (r0),_dbl_ld_acc
279 00015EA4 # if( dbl_ld_acc.m & 0x7f800000 )
280 00015EA4 3d 8f7f800000 effffffd91 bitl $2139095040,_dbl_ld_acc
281 00015EAF 31 18 jeql L260
282 00015EB1 # dbl_expected = dbl_ld_acc; /* expected = loaded */
283 00015EB1 0d effffffd8d effffffd88 movl _dbl_ld_acc+4,_dbl_expected+4
284 00015EBC 0d effffffd7e effffffd79 movl _dbl_ld_acc,_dbl_expected
285 00015EC7 # else {
286 00015EC7 11 0c jbr L261
287 00015EC9 L260:
288 00015EC9 # dbl_expected.m = 0; /* expect a '0' */
289 00015EC9 4d effffffd71 clrl _dbl_expected
290 00015ECF # dbl_expected.l = 0;
291 00015ECF 4d effffffd6f clrl _dbl_expected+4
292 00015ED5 # }
293 00015ED5 L261:
294 00015ED5 # /*
295 00015ED5 # * If LOOP ON ERROR is set, this is the loop for this subtest.
296 00015ED5 # * The force loop flag is set after the first error.
297 00015ED5 # */
298 00015ED5 # asm("_ldd_2_lp1:");
299 00015ED5 _ldd_2_lp1:
300 00015ED5 # asm("ldd _dbl_ld_acc"); /* load the value */
301 00015ED5 07 effffffd65 ldd _dbl_ld_acc
302 00015EDB # asm("nop");
303 00015EDB 10 nop
304 00015EDC # asm("std _dbl_st_acc"); /* store the result */
305 00015EDC 27 effffffd5e std _dbl_st_acc
306 00015EE2 # if( force_loop )
307 00015EE2 5d effffffd58 tstl _force_loop
308 00015EE8 31 02 jeql L262
309 00015EEA # asm("brb _ldd_2_lp1");; /* loop on the error */
310 00015EEA 11 e9 brb _ldd_2_lp1
311 00015EEC L262:
312 00015EEC # /*
313 00015EEC # * end error loop - test the results
314 00015EEC # */
315 00015EEC # if( ( dbl_st_acc.m != dbl_expected.m ) || /* COMPARE the */
316 00015EEC # ( dbl_st_acc.l != dbl_expected.l ) ) { /* values */
317 00015EEC 1d effffffd4e effffffd49 cmpl _dbl_st_acc,_dbl_expected
318 00015EF7 21 10 jneq L9998
319 00015EF9 1d effffffd45 effffffd40 cmpl _dbl_st_acc+4,_dbl_expected+4
320 00015F04 21 03 13 00e5 jeql L263
321 00015F09 L9998:
322 00015F09 # errcnt++; /* bump the error count */
323 00015F09 6d effffffd31 incl _errcnt
324 00015F0F # if( prt_error ) {
325 00015F0F 5d effffffd2b tstl _prt_error
326 00015F15 21 03 13 00b1 jeql L264
327 00015F1A # writes(" \n"); /* start a new print line */
328 00015F1A .data 1
329 00000ca9 * L265:
330 00000ca9 * 200A00 .ascii " \12\0"
331 00000cac * .text
332 00015F1A dd 8f00000ca9 pushl $L265
333 00015F20 fe 08 effffffd19 callf $8,_writes
334 00015F27 # writes("cycle: ");
335 00015F27 .data 1
336 00000cac * L266:
337 00000cac * 6379636C653A2000 .ascii "cycle: \0"
338 00000cb4 * .text
339 00015F27 dd 8f00000cac pushl $L266
340 00015F2D fe 08 effffffd0c callf $8,_writes
341 00015F34 # writed( cycle );
342 00015F34 dd effffffd06 pushl _cycle
343 00015F3A fe 08 effffffcff callf $8,_writed
344 00015F41 # writes(" LDD_STD test ");
345 00015F41 .data 1
346 00000cb4 * L267:
347 00000cb4 * 20204C44445F5354442074657 .ascii " LDD_STD test \0"
3742000
348 00000cc4 * .text
349 00015F41 dd 8f00000cb4 pushl $L267
350 00015F47 fe 08 effffffcf2 callf $8,_writes
351 00015F4E # writed( test_no );
352 00015F4E dd effffffcec pushl _test_no
353 00015F54 fe 08 effffffce5 callf $8,_writed
354 00015F5B # writes(", subtest 2 (Cache Data) - BAD FINAL ACC\n");
355 00015F5B .data 1
356 00000cc4 * L268:
357 00000cc4 * 2C20737562746573742032202 .ascii ", subtest 2 (Cache Data) - BAD FINAL ACC\12\0"
8436163686520446174612920
2D204241442046494E414C204
143430A00
358 00000cee * .text
359 00015F5B dd 8f00000cc4 pushl $L268
360 00015F61 fe 08 effffffcd8 callf $8,_writes
361 00015F68 # print_ldd_data();
362 00015F68 fe 04 ef0000077f callf $4,_print_ldd_data
363 00015F6F # writes(", index = ");
364 00015F6F .data 1
365 00000cee * L269:
366 00000cee * 2C20696E646578203D2000 .ascii ", index = \0"
367 00000cf9 * .text
368 00015F6F dd 8f00000cee pushl $L269
369 00015F75 fe 08 effffffcc4 callf $8,_writes
370 00015F7C # writed( index );
371 00015F7C dd effffffcbe pushl _index
372 00015F82 fe 08 effffffcb7 callf $8,_writed
373 00015F89 # writec('\n');
374 00015F89 dd 0a pushl $10
375 00015F8B fe 08 effffffcae callf $8,_writec
376 00015F92 # writes(" Acc expected = ");
377 00015F92 .data 1
378 00000cf9 * L270:
379 00000cf9 * 2020202020202020202020202 .ascii " Acc expected = \0"
0202020202020202020202020
2020202020202041636320657
8706563746564203D2000
380 00000d29 * .text
381 00015F92 dd 8f00000cf9 pushl $L270
382 00015F98 fe 08 effffffca1 callf $8,_writes
383 00015F9F # write32h( dbl_expected.m );
384 00015F9F dd effffffc9b pushl _dbl_expected
385 00015FA5 fe 08 effffffc94 callf $8,_write32h
386 00015FAC # writec(' ');
387 00015FAC dd 20 pushl $32
388 00015FAE fe 08 effffffc8b callf $8,_writec
389 00015FB5 # write32h( dbl_expected.l );
390 00015FB5 dd effffffc89 pushl _dbl_expected+4
391 00015FBB fe 08 effffffc7e callf $8,_write32h
392 00015FC2 # writec('\n');
393 00015FC2 dd 0a pushl $10
394 00015FC4 fe 08 effffffc75 callf $8,_writec
395 00015FCB # }
396 00015FCB # if( halt_flg )
397 00015FCB L264:
398 00015FCB 5d effffffc6f tstl _halt_flg
399 00015FD1 31 09 jeql L271
400 00015FD3 # ldd_er_halt( BAD_ACC_HLT ); /* halt on the error */
401 00015FD3 dd 01 pushl $1
402 00015FD5 fe 08 ef0000077a callf $8,_ldd_er_halt
403 00015FDC # if( loop_on_err ) {
404 00015FDC L271:
405 00015FDC 5d effffffc5e tstl _loop_on_err
406 00015FE2 31 0a jeql L272
407 00015FE4 # force_loop = TRUE; /* set the force loop flag */
408 00015FE4 0d 01 effffffc55 movl $1,_force_loop
409 00015FEB # asm("brw _ldd_2_lp1");; /* and loop on the error */
410 00015FEB 13 fee7 brw _ldd_2_lp1
411 00015FEE # } /* end of loop on error */
412 00015FEE # } /* end of compare error */
413 00015FEE L272:
414 00015FEE # } /* end of WHILE loop */
415 00015FEE L263:
416 00015FEE L257:
417 00015FEE 6d effffffc4c incl _index
418 00015FF4 13 fe7f jbr L259
419 00015FF7 L258:
420 00015FF7 # } /* end of subtest 2 */
421 00015FF7 40 ret#2
422 00015FF8 .set L253,0x0
423 00015FF8 L255:
424 00015FF8 13 fe68 jbr L256
425 00015FFB .data
426 00000c20 * .text
427 00015FFB 00 .align 1
428 00015FFC .globl _ldd_3
429 00015FFC _ldd_3:
430 00015FFC 0000 .word L273
431 00015FFE #
432 00015FFE #
433 00015FFE #
434 00015FFE # /************************************************************************
435 00015FFE # *
436 00015FFE # * SUBTEST 3 - Check for register corruption (ldd)
437 00015FFE # *
438 00015FFE # ************************************************************************/
439 00015FFE # ldd_3()
440 00015FFE # {
441 00015FFE 13 01c7 jbr L275
442 00016001 L276:
443 00016001 # force_loop = FALSE; /* clear force_loop flg */
444 00016001 4d effffffc39 clrl _force_loop
445 00016007 # subtest = 3;
446 00016007 0d 03 effffffc32 movl $3,_subtest
447 0001600E # fill_reg_buf( load_regs ); /* get patterns for regs */
448 0001600E dd 8f00000000 pushl $_load_regs
449 00016014 fe 08 effffffc25 callf $8,_fill_reg_buf
450 0001601B # index = 0;
451 0001601B 4d effffffc1f clrl _index
452 00016021 # dbl_ld_acc = ldd_1_data[0].ld; /* get value to load */
453 00016021 0d effffffc1d effffffc18 movl _ldd_1_data+4,_dbl_ld_acc+4
454 0001602C 0d effffffc0e effffffc09 movl _ldd_1_data,_dbl_ld_acc
455 00016037 # if( dbl_ld_acc.m & 0x7f800000 )
456 00016037 3d 8f7f800000 effffffbfe bitl $2139095040,_dbl_ld_acc
457 00016042 31 18 jeql L278
458 00016044 # dbl_expected = dbl_ld_acc; /* expected = loaded */
459 00016044 0d effffffbfa effffffbf5 movl _dbl_ld_acc+4,_dbl_expected+4
460 0001604F 0d effffffbeb effffffbe6 movl _dbl_ld_acc,_dbl_expected
461 0001605A # else {
462 0001605A 11 0c jbr L279
463 0001605C L278:
464 0001605C # dbl_expected.m = 0; /* expect a '0' */
465 0001605C 4d effffffbde clrl _dbl_expected
466 00016062 # dbl_expected.l = 0;
467 00016062 4d effffffbdc clrl _dbl_expected+4
468 00016068 # }
469 00016068 L279:
470 00016068 # /*
471 00016068 # * If LOOP ON ERROR is set, this is the loop for this subtest.
472 00016068 # * The force loop flag is set after the first error.
473 00016068 # */
474 00016068 # asm("_ldd_3_lp1:");
475 00016068 _ldd_3_lp1:
476 00016068 # asm("loadr $0x1fff,_load_regs"); /* load regs 0 - 12 */
477 00016068 ab 891fff effffffbcf loadr $0x1fff,_load_regs
478 00016071 # asm("nop");
479 00016071 10 nop
480 00016072 # asm("ldd _dbl_ld_acc"); /* load the accumulator */
481 00016072 07 effffffbc8 ldd _dbl_ld_acc
482 00016078 # asm("nop");
483 00016078 10 nop
484 00016079 # asm("storer $0x1fff,_store_regs"); /* store regs 0 - 12 */
485 00016079 bb 891fff effffffbbe storer $0x1fff,_store_regs
486 00016082 # asm("nop");
487 00016082 10 nop
488 00016083 # asm("std _dbl_st_acc"); /* save the accumulator */
489 00016083 27 effffffbb7 std _dbl_st_acc
490 00016089 # if( force_loop )
491 00016089 5d effffffbb1 tstl _force_loop
492 0001608F 31 02 jeql L280
493 00016091 # asm("brb _ldd_3_lp1");; /* loop on the error */
494 00016091 11 d5 brb _ldd_3_lp1
495 00016093 L280:
496 00016093 # /*
497 00016093 # * Now compare the stored register values to those that were loaded
498 00016093 # */
499 00016093 # index2 = 0;
500 00016093 4d effffffba7 clrl _index2
501 00016099 # while( (load_regs[index2] == store_regs[index2]) && (index2 < 13) )
502 00016099 L281:
503 00016099 0d effffffba1 50 movl _index2,r0
504 000160A0 0d effffffb9a 51 movl _index2,r1
505 000160A7 1d 40effffffb92 cmpl _load_regs[r0],_store_regs[r1]
41effffffb8c
506 000160B4 21 11 jneq L282
507 000160B6 1d effffffb84 0d cmpl _index2,$13
508 000160BD 81 08 jgeq L282
509 000160BF # index2++; /* check reg values */
510 000160BF 6d effffffb7b incl _index2
511 000160C5 11 d2 jbr L281
512 000160C7 L282:
513 000160C7 # if( index2 < 13 ) { /* error if index2 < 13 */
514 000160C7 1d effffffb73 0d cmpl _index2,$13
515 000160CE 91 03 13 00f4 jgeq L283
516 000160D3 # errcnt++; /* bump the error count */
517 000160D3 6d effffffb67 incl _errcnt
518 000160D9 # if( prt_error ) {
519 000160D9 5d effffffb61 tstl _prt_error
520 000160DF 21 03 13 00c0 jeql L284
521 000160E4 # writes(" \n"); /* start a new print line */
522 000160E4 .data 1
523 00000d29 * L285:
524 00000d29 * 200A00 .ascii " \12\0"
525 00000d2c * .text
526 000160E4 dd 8f00000d29 pushl $L285
527 000160EA fe 08 effffffb4f callf $8,_writes
528 000160F1 # writes("cycle: ");
529 000160F1 .data 1
530 00000d2c * L286:
531 00000d2c * 6379636C653A2000 .ascii "cycle: \0"
532 00000d34 * .text
533 000160F1 dd 8f00000d2c pushl $L286
534 000160F7 fe 08 effffffb42 callf $8,_writes
535 000160FE # writed( cycle );
536 000160FE dd effffffb3c pushl _cycle
537 00016104 fe 08 effffffb35 callf $8,_writed
538 0001610B # writes(" LDD_STD test ");
539 0001610B .data 1
540 00000d34 * L287:
541 00000d34 * 20204C44445F5354442074657 .ascii " LDD_STD test \0"
3742000
542 00000d44 * .text
543 0001610B dd 8f00000d34 pushl $L287
544 00016111 fe 08 effffffb28 callf $8,_writes
545 00016118 # writed( test_no );
546 00016118 dd effffffb22 pushl _test_no
547 0001611E fe 08 effffffb1b callf $8,_writed
548 00016125 # writes(", subtest 3 - A REGISTER WAS MODIFIED\n");
549 00016125 .data 1
550 00000d44 * L288:
551 00000d44 * 2C20737562746573742033202 .ascii ", subtest 3 - A REGISTER WAS MODIFIED\12\0"
D204120524547495354455220
574153204D4F4449464945440
A00
552 00000d6b * .text
553 00016125 dd 8f00000d44 pushl $L288
554 0001612B fe 08 effffffb0e callf $8,_writes
555 00016132 # print_ldd_data(); /* print the operands */
556 00016132 fe 04 ef000005b5 callf $4,_print_ldd_data
557 00016139 # writes("\nregister "); /* print the information */
558 00016139 .data 1
559 00000d6b * L289:
560 00000d6b * 0A72656769737465722000 .ascii "\12register \0"
561 00000d76 * .text
562 00016139 dd 8f00000d6b pushl $L289
563 0001613F fe 08 effffffafa callf $8,_writes
564 00016146 # writed( index2 ); /* about the corrupted */
565 00016146 dd effffffaf4 pushl _index2
566 0001614C fe 08 effffffaed callf $8,_writed
567 00016153 # writes(" = "); /* register */
568 00016153 .data 1
569 00000d76 * L290:
570 00000d76 * 203D2000 .ascii " = \0"
571 00000d7a * .text
572 00016153 dd 8f00000d76 pushl $L290
573 00016159 fe 08 effffffae0 callf $8,_writes
574 00016160 # write32h( store_regs[index2] );
575 00016160 0d effffffada 50 movl _index2,r0
576 00016167 dd 40effffffad2 pushl _store_regs[r0]
577 0001616E fe 08 effffffacb callf $8,_write32h
578 00016175 # writes(", should be = ");
579 00016175 .data 1
580 00000d7a * L291:
581 00000d7a * 2C202073686F756C642062652 .ascii ", should be = \0"
03D2000
582 00000d8a * .text
583 00016175 dd 8f00000d7a pushl $L291
584 0001617B fe 08 effffffabe callf $8,_writes
585 00016182 # write32h( load_regs[index2] );
586 00016182 0d effffffab8 50 movl _index2,r0
587 00016189 dd 40effffffab0 pushl _load_regs[r0]
588 00016190 fe 08 effffffaa9 callf $8,_write32h
589 00016197 # writes("\n");
590 00016197 .data 1
591 00000d8a * L292:
592 00000d8a * 0A00 .ascii "\12\0"
593 00000d8c * .text
594 00016197 dd 8f00000d8a pushl $L292
595 0001619D fe 08 effffffa9c callf $8,_writes
596 000161A4 # }
597 000161A4 # if( halt_flg )
598 000161A4 L284:
599 000161A4 5d effffffa96 tstl _halt_flg
600 000161AA 31 09 jeql L293
601 000161AC # ldd_er_halt( BAD_REG_HLT ); /* halt on the error */
602 000161AC dd 02 pushl $2
603 000161AE fe 08 ef000005a1 callf $8,_ldd_er_halt
604 000161B5 # if( loop_on_err ) {
605 000161B5 L293:
606 000161B5 5d effffffa85 tstl _loop_on_err
607 000161BB 31 0a jeql L294
608 000161BD # force_loop = TRUE; /* set the force loop flag */
609 000161BD 0d 01 effffffa7c movl $1,_force_loop
610 000161C4 # asm("brw _ldd_3_lp1");; /* and loop on the error */
611 000161C4 13 fea1 brw _ldd_3_lp1
612 000161C7 # } /* end of loop on error */
613 000161C7 # } /* end of register corruption error */
614 000161C7 L294:
615 000161C7 # } /* end of subtest 3 */
616 000161C7 L283:
617 000161C7 40 ret#2
618 000161C8 .set L273,0x0
619 000161C8 L275:
620 000161C8 13 fe36 jbr L276
621 000161CB .data
622 00000c20 * .text
623 000161CB 00 .align 1
624 000161CC .globl _ldd_4
625 000161CC _ldd_4:
626 000161CC 0000 .word L295
627 000161CE #
628 000161CE #
629 000161CE #
630 000161CE # /************************************************************************
631 000161CE # *
632 000161CE # * SUBTEST 4 - Check for register corruption (std)
633 000161CE # *
634 000161CE # ************************************************************************/
635 000161CE # ldd_4()
636 000161CE # {
637 000161CE 13 0196 jbr L297
638 000161D1 L298:
639 000161D1 # force_loop = FALSE; /* clear force_loop flg */
640 000161D1 4d effffffa69 clrl _force_loop
641 000161D7 # subtest = 4;
642 000161D7 0d 04 effffffa62 movl $4,_subtest
643 000161DE # fill_reg_buf( load_regs ); /* get patterns for regs */
644 000161DE dd 8f00000000 pushl $_load_regs
645 000161E4 fe 08 effffffa55 callf $8,_fill_reg_buf
646 000161EB # index = 0;
647 000161EB 4d effffffa4f clrl _index
648 000161F1 # dbl_ld_acc = ldd_1_data[0].ld; /* get value to store */
649 000161F1 0d effffffa4d effffffa48 movl _ldd_1_data+4,_dbl_ld_acc+4
650 000161FC 0d effffffa3e effffffa39 movl _ldd_1_data,_dbl_ld_acc
651 00016207 # /*
652 00016207 # * If LOOP ON ERROR is set, this is the loop for this subtest.
653 00016207 # * The force loop flag is set after the first error.
654 00016207 # */
655 00016207 # asm("_ldd_4_lp1:");
656 00016207 _ldd_4_lp1:
657 00016207 # asm("ldd _dbl_ld_acc"); /* load the accumulator */
658 00016207 07 effffffa33 ldd _dbl_ld_acc
659 0001620D # asm("nop");
660 0001620D 10 nop
661 0001620E # asm("loadr $0x1fff,_load_regs"); /* load regs 0 - 12 */
662 0001620E ab 891fff effffffa29 loadr $0x1fff,_load_regs
663 00016217 # asm("nop");
664 00016217 10 nop
665 00016218 # asm("std _dbl_st_acc"); /* save the accumulator */
666 00016218 27 effffffa22 std _dbl_st_acc
667 0001621E # asm("nop");
668 0001621E 10 nop
669 0001621F # asm("storer $0x1fff,_store_regs"); /* store regs 0 - 12 */
670 0001621F bb 891fff effffffa18 storer $0x1fff,_store_regs
671 00016228 # if( force_loop )
672 00016228 5d effffffa12 tstl _force_loop
673 0001622E 31 02 jeql L299
674 00016230 # asm("brb _ldd_4_lp1");; /* loop on the error */
675 00016230 11 d5 brb _ldd_4_lp1
676 00016232 L299:
677 00016232 # /*
678 00016232 # * Now compare the stored register values to those that were loaded
679 00016232 # */
680 00016232 # index2 = 0;
681 00016232 4d effffffa08 clrl _index2
682 00016238 # while( (load_regs[index2] == store_regs[index2]) && (index2 < 13) )
683 00016238 L300:
684 00016238 0d effffffa02 50 movl _index2,r0
685 0001623F 0d effffff9fb 51 movl _index2,r1
686 00016246 1d 40effffff9f3 cmpl _load_regs[r0],_store_regs[r1]
41effffff9ed
687 00016253 21 11 jneq L301
688 00016255 1d effffff9e5 0d cmpl _index2,$13
689 0001625C 81 08 jgeq L301
690 0001625E # index2++; /* check reg values */
691 0001625E 6d effffff9dc incl _index2
692 00016264 11 d2 jbr L300
693 00016266 L301:
694 00016266 # if( index2 < 13 ) { /* error if index2 < 13 */
695 00016266 1d effffff9d4 0d cmpl _index2,$13
696 0001626D 91 03 13 00f4 jgeq L302
697 00016272 # errcnt++; /* bump the error count */
698 00016272 6d effffff9c8 incl _errcnt
699 00016278 # if( prt_error ) {
700 00016278 5d effffff9c2 tstl _prt_error
701 0001627E 21 03 13 00c0 jeql L303
702 00016283 # writes(" \n"); /* start a new print line */
703 00016283 .data 1
704 00000d8c * L304:
705 00000d8c * 200A00 .ascii " \12\0"
706 00000d8f * .text
707 00016283 dd 8f00000d8c pushl $L304
708 00016289 fe 08 effffff9b0 callf $8,_writes
709 00016290 # writes("cycle: ");
710 00016290 .data 1
711 00000d8f * L305:
712 00000d8f * 6379636C653A2000 .ascii "cycle: \0"
713 00000d97 * .text
714 00016290 dd 8f00000d8f pushl $L305
715 00016296 fe 08 effffff9a3 callf $8,_writes
716 0001629D # writed( cycle );
717 0001629D dd effffff99d pushl _cycle
718 000162A3 fe 08 effffff996 callf $8,_writed
719 000162AA # writes(" LDD_STD test ");
720 000162AA .data 1
721 00000d97 * L306:
722 00000d97 * 204C44445F535444207465737 .ascii " LDD_STD test \0"
42000
723 00000da6 * .text
724 000162AA dd 8f00000d97 pushl $L306
725 000162B0 fe 08 effffff989 callf $8,_writes
726 000162B7 # writed( test_no );
727 000162B7 dd effffff983 pushl _test_no
728 000162BD fe 08 effffff97c callf $8,_writed
729 000162C4 # writes(", subtest 4 - A REGISTER WAS MODIFIED\n");
730 000162C4 .data 1
731 00000da6 * L307:
732 00000da6 * 2C20737562746573742034202 .ascii ", subtest 4 - A REGISTER WAS MODIFIED\12\0"
D204120524547495354455220
574153204D4F4449464945440
A00
733 00000dcd * .text
734 000162C4 dd 8f00000da6 pushl $L307
735 000162CA fe 08 effffff96f callf $8,_writes
736 000162D1 # print_ldd_data(); /* print the operands */
737 000162D1 fe 04 ef00000416 callf $4,_print_ldd_data
738 000162D8 # writes("\nregister "); /* print the information */
739 000162D8 .data 1
740 00000dcd * L308:
741 00000dcd * 0A72656769737465722000 .ascii "\12register \0"
742 00000dd8 * .text
743 000162D8 dd 8f00000dcd pushl $L308
744 000162DE fe 08 effffff95b callf $8,_writes
745 000162E5 # writed( index2 ); /* about the corrupted */
746 000162E5 dd effffff955 pushl _index2
747 000162EB fe 08 effffff94e callf $8,_writed
748 000162F2 # writes(" = "); /* register */
749 000162F2 .data 1
750 00000dd8 * L309:
751 00000dd8 * 203D2000 .ascii " = \0"
752 00000ddc * .text
753 000162F2 dd 8f00000dd8 pushl $L309
754 000162F8 fe 08 effffff941 callf $8,_writes
755 000162FF # write32h( store_regs[index2] );
756 000162FF 0d effffff93b 50 movl _index2,r0
757 00016306 dd 40effffff933 pushl _store_regs[r0]
758 0001630D fe 08 effffff92c callf $8,_write32h
759 00016314 # writes(", should be = ");
760 00016314 .data 1
761 00000ddc * L310:
762 00000ddc * 2C202073686F756C642062652 .ascii ", should be = \0"
03D2000
763 00000dec * .text
764 00016314 dd 8f00000ddc pushl $L310
765 0001631A fe 08 effffff91f callf $8,_writes
766 00016321 # write32h( load_regs[index2] );
767 00016321 0d effffff919 50 movl _index2,r0
768 00016328 dd 40effffff911 pushl _load_regs[r0]
769 0001632F fe 08 effffff90a callf $8,_write32h
770 00016336 # writes("\n");
771 00016336 .data 1
772 00000dec * L311:
773 00000dec * 0A00 .ascii "\12\0"
774 00000dee * .text
775 00016336 dd 8f00000dec pushl $L311
776 0001633C fe 08 effffff8fd callf $8,_writes
777 00016343 # }
778 00016343 # if( halt_flg )
779 00016343 L303:
780 00016343 5d effffff8f7 tstl _halt_flg
781 00016349 31 09 jeql L312
782 0001634B # ldd_er_halt( BAD_REG_HLT ); /* halt on the error */
783 0001634B dd 02 pushl $2
784 0001634D fe 08 ef00000402 callf $8,_ldd_er_halt
785 00016354 # if( loop_on_err ) {
786 00016354 L312:
787 00016354 5d effffff8e6 tstl _loop_on_err
788 0001635A 31 0a jeql L313
789 0001635C # force_loop = TRUE; /* set the force loop flag */
790 0001635C 0d 01 effffff8dd movl $1,_force_loop
791 00016363 # asm("brw _ldd_4_lp1");; /* and loop on the error */
792 00016363 13 fea1 brw _ldd_4_lp1
793 00016366 # } /* end of loop on error */
794 00016366 # } /* end of register corruption error */
795 00016366 L313:
796 00016366 # } /* end of subtest 4 */
797 00016366 L302:
798 00016366 40 ret#2
799 00016367 .set L295,0x0
800 00016367 L297:
801 00016367 13 fe67 jbr L298
802 0001636A .data
803 00000c20 * .text
804 0001636A .align 1
805 0001636A .globl _ldd_5
806 0001636A _ldd_5:
807 0001636A 0000 .word L314
808 0001636C #
809 0001636C #
810 0001636C #
811 0001636C # /************************************************************************
812 0001636C # *
813 0001636C # * SUBTEST 5 - Check for PSL corruption (ldd)
814 0001636C # *
815 0001636C # ************************************************************************/
816 0001636C # ldd_5()
817 0001636C # {
818 0001636C 13 0197 jbr L316
819 0001636F L317:
820 0001636F # force_loop = FALSE; /* clear force_loop flg */
821 0001636F 4d effffff8cb clrl _force_loop
822 00016375 # subtest = 5;
823 00016375 0d 05 effffff8c4 movl $5,_subtest
824 0001637C # status_index = 0;
825 0001637C 4d effffff8be clrl _status_index
826 00016382 # fill_reg_buf( load_regs ); /* get patterns for regs */
827 00016382 dd 8f00000000 pushl $_load_regs
828 00016388 fe 08 effffff8b1 callf $8,_fill_reg_buf
829 0001638F # for( index = 0; index < 3; index++ ) {
830 0001638F 4d effffff8ab clrl _index
831 00016395 L320:
832 00016395 1d effffff8a5 03 cmpl _index,$3
833 0001639C 91 03 13 0164 jgeq L319
834 000163A1 # dbl_ld_acc = ldd_1_data[index].ld; /* get value to load */
835 000163A1 48 04 effffff898 50 shll $4,_index,r0
836 000163A9 0c 8f00000000 50 addl2 $_ldd_1_data,r0
837 000163B0 0d a004 effffff88c movl 4(r0),_dbl_ld_acc+4
838 000163B8 0d 60 effffff881 movl (r0),_dbl_ld_acc
839 000163BF # sgl_dummy1 = status_array[status_index]; /* status = +, -, 0 */
840 000163BF 0d effffff87b 50 movl _status_index,r0
841 000163C6 0d 40effffff873 movl _status_array[r0],_sgl_dummy1
effffff86e
842 000163D2 # /*
843 000163D2 # * If LOOP ON ERROR is set, this is the loop for this subtest.
844 000163D2 # * The force loop flag is set after the first error.
845 000163D2 # */
846 000163D2 # asm("_ldd_5_lp1:");
847 000163D2 _ldd_5_lp1:
848 000163D2 # asm("tstl _sgl_dummy1"); /* set the PSL status */
849 000163D2 5d effffff868 tstl _sgl_dummy1
850 000163D8 # asm("movpsl _init_psl"); /* save the initial PSL */
851 000163D8 cd effffff862 movpsl _init_psl
852 000163DE # asm("nop");
853 000163DE 10 nop
854 000163DF # asm("ldd _dbl_ld_acc"); /* load the accumulator */
855 000163DF 07 effffff85b ldd _dbl_ld_acc
856 000163E5 # asm("nop");
857 000163E5 10 nop
858 000163E6 # asm("movpsl _psl_val"); /* save the final PSL */
859 000163E6 cd effffff854 movpsl _psl_val
860 000163EC # asm("nop");
861 000163EC 10 nop
862 000163ED # asm("std _dbl_st_acc"); /* save the accumulator */
863 000163ED 27 effffff84d std _dbl_st_acc
864 000163F3 # if( force_loop )
865 000163F3 5d effffff847 tstl _force_loop
866 000163F9 31 02 jeql L321
867 000163FB # asm("brb _ldd_5_lp1");; /* loop on the error */
868 000163FB 11 d5 brb _ldd_5_lp1
869 000163FD L321:
870 000163FD # /*
871 000163FD # * Now compare the final PSL to the initial PSL -they should be the same
872 000163FD # */
873 000163FD # exp_psl = init_psl;
874 000163FD 0d effffff83d effffff838 movl _init_psl,_exp_psl
875 00016408 # if( psl_val != exp_psl ) {
876 00016408 1d effffff832 effffff82d cmpl _psl_val,_exp_psl
877 00016413 21 03 13 00e4 jeql L322
878 00016418 # errcnt++; /* bump the error count */
879 00016418 6d effffff822 incl _errcnt
880 0001641E # if( prt_error ) {
881 0001641E 5d effffff81c tstl _prt_error
882 00016424 21 03 13 00b0 jeql L323
883 00016429 # writes(" \n"); /* start a new print line */
884 00016429 .data 1
885 00000dee * L324:
886 00000dee * 200A00 .ascii " \12\0"
887 00000df1 * .text
888 00016429 dd 8f00000dee pushl $L324
889 0001642F fe 08 effffff80a callf $8,_writes
890 00016436 # writes("cycle: ");
891 00016436 .data 1
892 00000df1 * L325:
893 00000df1 * 6379636C653A2000 .ascii "cycle: \0"
894 00000df9 * .text
895 00016436 dd 8f00000df1 pushl $L325
896 0001643C fe 08 effffff7fd callf $8,_writes
897 00016443 # writed( cycle );
898 00016443 dd effffff7f7 pushl _cycle
899 00016449 fe 08 effffff7f0 callf $8,_writed
900 00016450 # writes(" LDD_STD test ");
901 00016450 .data 1
902 00000df9 * L326:
903 00000df9 * 20204C44445F5354442074657 .ascii " LDD_STD test \0"
3742000
904 00000e09 * .text
905 00016450 dd 8f00000df9 pushl $L326
906 00016456 fe 08 effffff7e3 callf $8,_writes
907 0001645D # writed( test_no );
908 0001645D dd effffff7dd pushl _test_no
909 00016463 fe 08 effffff7d6 callf $8,_writed
910 0001646A # writes(", subtest 5 - INCORRECT FINAL PSL - LDD\n");
911 0001646A .data 1
912 00000e09 * L327:
913 00000e09 * 2C20737562746573742035202 .ascii ", subtest 5 - INCORRECT FINAL PSL - LDD\12\0"
02D20494E434F525245435420
46494E414C2050534C202D204
C44440A00
914 00000e33 * .text
915 0001646A dd 8f00000e09 pushl $L327
916 00016470 fe 08 effffff7c9 callf $8,_writes
917 00016477 # print_ldd_data(); /* print the operands */
918 00016477 fe 04 ef00000270 callf $4,_print_ldd_data
919 0001647E # writes("\ninitial PSL = ");
920 0001647E .data 1
921 00000e33 * L328:
922 00000e33 * 0A696E697469616C2050534C2 .ascii "\12initial PSL = \0"
03D2000
923 00000e43 * .text
924 0001647E dd 8f00000e33 pushl $L328
925 00016484 fe 08 effffff7b5 callf $8,_writes
926 0001648B # write32h( init_psl );
927 0001648B dd effffff7af pushl _init_psl
928 00016491 fe 08 effffff7a8 callf $8,_write32h
929 00016498 # writes(", final PSL = ");
930 00016498 .data 1
931 00000e43 * L329:
932 00000e43 * 2C202066696E616C2050534C2 .ascii ", final PSL = \0"
03D2000
933 00000e53 * .text
934 00016498 dd 8f00000e43 pushl $L329
935 0001649E fe 08 effffff79b callf $8,_writes
936 000164A5 # write32h( psl_val );
937 000164A5 dd effffff795 pushl _psl_val
938 000164AB fe 08 effffff78e callf $8,_write32h
939 000164B2 # writes(", expected PSL = ");
940 000164B2 .data 1
941 00000e53 * L330:
942 00000e53 * 2C20206578706563746564205 .ascii ", expected PSL = \0"
0534C203D2000
943 00000e66 * .text
944 000164B2 dd 8f00000e53 pushl $L330
945 000164B8 fe 08 effffff781 callf $8,_writes
946 000164BF # write32h( exp_psl );
947 000164BF dd effffff77b pushl _exp_psl
948 000164C5 fe 08 effffff774 callf $8,_write32h
949 000164CC # writes("\n");
950 000164CC .data 1
951 00000e66 * L331:
952 00000e66 * 0A00 .ascii "\12\0"
953 00000e68 * .text
954 000164CC dd 8f00000e66 pushl $L331
955 000164D2 fe 08 effffff767 callf $8,_writes
956 000164D9 # }
957 000164D9 # if( halt_flg )
958 000164D9 L323:
959 000164D9 5d effffff761 tstl _halt_flg
960 000164DF 31 09 jeql L332
961 000164E1 # ldd_er_halt( BAD_PSL_HLT ); /* halt on the error */
962 000164E1 dd 03 pushl $3
963 000164E3 fe 08 ef0000026c callf $8,_ldd_er_halt
964 000164EA # if( loop_on_err ) {
965 000164EA L332:
966 000164EA 5d effffff750 tstl _loop_on_err
967 000164F0 31 0a jeql L333
968 000164F2 # force_loop = TRUE; /* set the force loop flag */
969 000164F2 0d 01 effffff747 movl $1,_force_loop
970 000164F9 # asm("brw _ldd_5_lp1");; /* and loop on the error */
971 000164F9 13 fed6 brw _ldd_5_lp1
972 000164FC # } /* end of loop on error */
973 000164FC # } /* end of PSL corruption error */
974 000164FC L333:
975 000164FC # } /* end of WHILE loop */
976 000164FC L322:
977 000164FC L318:
978 000164FC 6d effffff73e incl _index
979 00016502 13 fe90 jbr L320
980 00016505 L319:
981 00016505 # } /* end of subtest 5 */
982 00016505 40 ret#2
983 00016506 .set L314,0x0
984 00016506 L316:
985 00016506 13 fe66 jbr L317
986 00016509 .data
987 00000c20 * .text
988 00016509 00 .align 1
989 0001650A .globl _ldd_6
990 0001650A _ldd_6:
991 0001650A 0000 .word L334
992 0001650C #
993 0001650C #
994 0001650C #
995 0001650C # /************************************************************************
996 0001650C # *
997 0001650C # * SUBTEST 6 - STD status test
998 0001650C # *
999 0001650C # ************************************************************************/
1000 0001650C # ldd_6()
1001 0001650C # {
1002 0001650C 13 01dc jbr L336
1003 0001650F L337:
1004 0001650F # force_loop = FALSE;
1005 0001650F 4d effffff72b clrl _force_loop
1006 00016515 # index = 0; /* clear the data index */
1007 00016515 4d effffff725 clrl _index
1008 0001651B # status_index = 0; /* clear the status index */
1009 0001651B 4d effffff71f clrl _status_index
1010 00016521 # do {
1011 00016521 L340:
1012 00016521 # dbl_ld_acc = ldd_1_data[index].ld; /* get the dbl operand */
1013 00016521 48 04 effffff718 50 shll $4,_index,r0
1014 00016529 0c 8f00000000 50 addl2 $_ldd_1_data,r0
1015 00016530 0d a004 effffff70c movl 4(r0),_dbl_ld_acc+4
1016 00016538 0d 60 effffff701 movl (r0),_dbl_ld_acc
1017 0001653F # sgl_dummy1 = status_array[status_index]; /* array = +, -, 0 */
1018 0001653F 0d effffff6fb 50 movl _status_index,r0
1019 00016546 0d 40effffff6f3 movl _status_array[r0],_sgl_dummy1
effffff6ee
1020 00016552 # /*
1021 00016552 # * If LOOP ON ERROR is set, this is the loop for this subtest.
1022 00016552 # * The force loop flag is set after the first error.
1023 00016552 # */
1024 00016552 # asm("_ldd_6_lp1:");
1025 00016552 _ldd_6_lp1:
1026 00016552 # asm("ldd _dbl_ld_acc"); /* load the operand */
1027 00016552 07 effffff6e8 ldd _dbl_ld_acc
1028 00016558 # asm("tstl _sgl_dummy1"); /* generate initial status */
1029 00016558 5d effffff6e2 tstl _sgl_dummy1
1030 0001655E # asm("movpsl _init_psl"); /* save the initial status */
1031 0001655E cd effffff6dc movpsl _init_psl
1032 00016564 # asm("std _dbl_st_acc"); /* save the accumulator */
1033 00016564 27 effffff6d6 std _dbl_st_acc
1034 0001656A # asm("movpsl _psl_val"); /* save the final status */
1035 0001656A cd effffff6d0 movpsl _psl_val
1036 00016570 # if( force_loop ) /* loop? */
1037 00016570 5d effffff6ca tstl _force_loop
1038 00016576 31 06 jeql L341
1039 00016578 # asm("jmp _ldd_6_lp1");; /* run the loop again */
1040 00016578 71 efffffffd4 jmp _ldd_6_lp1
1041 0001657E L341:
1042 0001657E # exp_psl = init_psl; /* get the initial PSL */
1043 0001657E 0d effffff6bc effffff6b7 movl _init_psl,_exp_psl
1044 00016589 # exp_psl &= 0xfffffff3; /* clear ZERO, NEGATIVE */
1045 00016589 ac 88f3 effffff6af andl2 $-13,_exp_psl
1046 00016591 # sgl_dummy2 = dbl_ld_acc.m; /* get MSW of the operand */
1047 00016591 0d effffff6a9 effffff6a4 movl _dbl_ld_acc,_sgl_dummy2
1048 0001659C # /* if( !no_fpp_wcs ) /* why? */
1049 0001659C # sgl_dummy2 &= 0xff800000; /* clear the fraction part */
1050 0001659C ac 8fff800000 effffff699 andl2 $-8388608,_sgl_dummy2
1051 000165A7 # if( !sgl_dummy2 )
1052 000165A7 5d effffff693 tstl _sgl_dummy2
1053 000165AD 21 07 jneq L342
1054 000165AF # exp_psl |= PSL_Z; /* expect the ZERO bit set */
1055 000165AF 8c 04 effffff68a orl2 $4,_exp_psl
1056 000165B6 # if( sgl_dummy2 < 0 )
1057 000165B6 L342:
1058 000165B6 5d effffff684 tstl _sgl_dummy2
1059 000165BC 81 07 jgeq L343
1060 000165BE # exp_psl |= PSL_N; /* expect the NEG bit set */
1061 000165BE 8c 08 effffff67b orl2 $8,_exp_psl
1062 000165C5 # if( psl_val != exp_psl ) { /* COMPARE the values */
1063 000165C5 L343:
1064 000165C5 1d effffff675 effffff670 cmpl _psl_val,_exp_psl
1065 000165D0 21 03 13 00e4 jeql L344
1066 000165D5 # errcnt++; /* bump the error count */
1067 000165D5 6d effffff665 incl _errcnt
1068 000165DB # if( prt_error ) {
1069 000165DB 5d effffff65f tstl _prt_error
1070 000165E1 21 03 13 00b0 jeql L345
1071 000165E6 # writes(" \n"); /* start a new print line */
1072 000165E6 .data 1
1073 00000e68 * L346:
1074 00000e68 * 200A00 .ascii " \12\0"
1075 00000e6b * .text
1076 000165E6 dd 8f00000e68 pushl $L346
1077 000165EC fe 08 effffff64d callf $8,_writes
1078 000165F3 # writes("cycle: ");
1079 000165F3 .data 1
1080 00000e6b * L347:
1081 00000e6b * 6379636C653A2000 .ascii "cycle: \0"
1082 00000e73 * .text
1083 000165F3 dd 8f00000e6b pushl $L347
1084 000165F9 fe 08 effffff640 callf $8,_writes
1085 00016600 # writed( cycle );
1086 00016600 dd effffff63a pushl _cycle
1087 00016606 fe 08 effffff633 callf $8,_writed
1088 0001660D # writes(" LDD_STD test ");
1089 0001660D .data 1
1090 00000e73 * L348:
1091 00000e73 * 20204C44445F5354442074657 .ascii " LDD_STD test \0"
3742000
1092 00000e83 * .text
1093 0001660D dd 8f00000e73 pushl $L348
1094 00016613 fe 08 effffff626 callf $8,_writes
1095 0001661A # writed( test_no );
1096 0001661A dd effffff620 pushl _test_no
1097 00016620 fe 08 effffff619 callf $8,_writed
1098 00016627 # writes(", subtest 6 - INCORRECT FINAL PSL - STD\n");
1099 00016627 .data 1
1100 00000e83 * L349:
1101 00000e83 * 2C20737562746573742036202 .ascii ", subtest 6 - INCORRECT FINAL PSL - STD\12\0"
02D20494E434F525245435420
46494E414C2050534C202D205
354440A00
1102 00000ead * .text
1103 00016627 dd 8f00000e83 pushl $L349
1104 0001662D fe 08 effffff60c callf $8,_writes
1105 00016634 # print_ldd_data(); /* print the operands */
1106 00016634 fe 04 ef000000b3 callf $4,_print_ldd_data
1107 0001663B # writes("\ninitial PSL = ");
1108 0001663B .data 1
1109 00000ead * L350:
1110 00000ead * 0A696E697469616C2050534C2 .ascii "\12initial PSL = \0"
03D2000
1111 00000ebd * .text
1112 0001663B dd 8f00000ead pushl $L350
1113 00016641 fe 08 effffff5f8 callf $8,_writes
1114 00016648 # write32h( init_psl );
1115 00016648 dd effffff5f2 pushl _init_psl
1116 0001664E fe 08 effffff5eb callf $8,_write32h
1117 00016655 # writes(", final PSL = ");
1118 00016655 .data 1
1119 00000ebd * L351:
1120 00000ebd * 2C202066696E616C2050534C2 .ascii ", final PSL = \0"
03D2000
1121 00000ecd * .text
1122 00016655 dd 8f00000ebd pushl $L351
1123 0001665B fe 08 effffff5de callf $8,_writes
1124 00016662 # write32h( psl_val );
1125 00016662 dd effffff5d8 pushl _psl_val
1126 00016668 fe 08 effffff5d1 callf $8,_write32h
1127 0001666F # writes(", expected PSL = ");
1128 0001666F .data 1
1129 00000ecd * L352:
1130 00000ecd * 2C20206578706563746564205 .ascii ", expected PSL = \0"
0534C203D2000
1131 00000ee0 * .text
1132 0001666F dd 8f00000ecd pushl $L352
1133 00016675 fe 08 effffff5c4 callf $8,_writes
1134 0001667C # write32h( exp_psl );
1135 0001667C dd effffff5be pushl _exp_psl
1136 00016682 fe 08 effffff5b7 callf $8,_write32h
1137 00016689 # writes("\n");
1138 00016689 .data 1
1139 00000ee0 * L353:
1140 00000ee0 * 0A00 .ascii "\12\0"
1141 00000ee2 * .text
1142 00016689 dd 8f00000ee0 pushl $L353
1143 0001668F fe 08 effffff5aa callf $8,_writes
1144 00016696 # }
1145 00016696 # if( halt_flg )
1146 00016696 L345:
1147 00016696 5d effffff5a4 tstl _halt_flg
1148 0001669C 31 09 jeql L354
1149 0001669E # ldd_er_halt( BAD_PSL_HLT ); /* halt on the error */
1150 0001669E dd 03 pushl $3
1151 000166A0 fe 08 ef000000af callf $8,_ldd_er_halt
1152 000166A7 # if( loop_on_err ) {
1153 000166A7 L354:
1154 000166A7 5d effffff593 tstl _loop_on_err
1155 000166AD 31 0a jeql L355
1156 000166AF # force_loop = TRUE; /* set the force loop flag */
1157 000166AF 0d 01 effffff58a movl $1,_force_loop
1158 000166B6 # asm("brw _ldd_6_lp1");; /* and loop */
1159 000166B6 13 fe99 brw _ldd_6_lp1
1160 000166B9 # }; /* end of loop-on-error */
1161 000166B9 L355:
1162 000166B9 # } /* end of compare error */
1163 000166B9 # if( ++status_index >= 3 )
1164 000166B9 L344:
1165 000166B9 6d effffff581 incl _status_index
1166 000166BF 0d effffff57b 50 movl _status_index,r0
1167 000166C6 1d 50 03 cmpl r0,$3
1168 000166C9 91 06 jlss L356
1169 000166CB # status_index = 0; /* reset the status index */
1170 000166CB 4d effffff56f clrl _status_index
1171 000166D1 # } while( index++ < max_ldd_1_index );
1172 000166D1 L356:
1173 000166D1 L339:
1174 000166D1 0d effffff569 50 movl _index,r0
1175 000166D8 6d effffff562 incl _index
1176 000166DE 1d 50 effffff55b cmpl r0,_max_ldd_1_index
1177 000166E5 81 03 13 fe37 jlss L340
1178 000166EA L338:
1179 000166EA # } /* end of subtest 6 */
1180 000166EA 40 ret#2
1181 000166EB .set L334,0x0
1182 000166EB L336:
1183 000166EB 13 fe21 jbr L337
1184 000166EE .data
1185 00000c20 * .text
1186 000166EE .align 1
1187 000166EE .globl _print_ldd_data
1188 000166EE _print_ldd_data:
1189 000166EE 0000 .word L357
1190 000166F0 #
1191 000166F0 #
1192 000166F0 #
1193 000166F0 # /**************************************************************************
1194 000166F0 # *
1195 000166F0 # * PRINT THE DATA AND STORE RESULTS
1196 000166F0 # *
1197 000166F0 # * Acc loaded = xxxxxxxx xxxxxxxx, Acc stored = xxxxxxxx xxxxxxxx, index = xx
1198 000166F0 # **************************************************************************/
1199 000166F0 # print_ldd_data()
1200 000166F0 # {
1201 000166F0 11 61 jbr L359
1202 000166F2 L360:
1203 000166F2 # writes(" Acc loaded = ");
1204 000166F2 .data 1
1205 00000ee2 * L361:
1206 00000ee2 * 20416363206C6F61646564203 .ascii " Acc loaded = \0"
D2000
1207 00000ef1 * .text
1208 000166F2 dd 8f00000ee2 pushl $L361
1209 000166F8 fe 08 effffff541 callf $8,_writes
1210 000166FF # write32h( dbl_ld_acc.m );
1211 000166FF dd effffff53b pushl _dbl_ld_acc
1212 00016705 fe 08 effffff534 callf $8,_write32h
1213 0001670C # writec(' ');
1214 0001670C dd 20 pushl $32
1215 0001670E fe 08 effffff52b callf $8,_writec
1216 00016715 # write32h( dbl_ld_acc.l );
1217 00016715 dd effffff529 pushl _dbl_ld_acc+4
1218 0001671B fe 08 effffff51e callf $8,_write32h
1219 00016722 # writes(", Acc stored = ");
1220 00016722 .data 1
1221 00000ef1 * L362:
1222 00000ef1 * 2C20204163632073746F72656 .ascii ", Acc stored = \0"
4203D2000
1223 00000f02 * .text
1224 00016722 dd 8f00000ef1 pushl $L362
1225 00016728 fe 08 effffff511 callf $8,_writes
1226 0001672F # write32h( dbl_st_acc.m );
1227 0001672F dd effffff50b pushl _dbl_st_acc
1228 00016735 fe 08 effffff504 callf $8,_write32h
1229 0001673C # writec(' ');
1230 0001673C dd 20 pushl $32
1231 0001673E fe 08 effffff4fb callf $8,_writec
1232 00016745 # write32h( dbl_st_acc.l );
1233 00016745 dd effffff4f9 pushl _dbl_st_acc+4
1234 0001674B fe 08 effffff4ee callf $8,_write32h
1235 00016752 # }
1236 00016752 40 ret#2
1237 00016753 .set L357,0x0
1238 00016753 L359:
1239 00016753 11 9d jbr L360
1240 00016755 .data
1241 00000c20 * .text
1242 00016755 00 .align 1
1243 00016756 .globl _ldd_er_halt
1244 00016756 _ldd_er_halt:
1245 00016756 0000 .word L363
1246 00016758 #
1247 00016758 #
1248 00016758 #
1249 00016758 # /**************************************************************************
1250 00016758 # *
1251 00016758 # * HALT ON ERROR ROUTINE
1252 00016758 # *
1253 00016758 # **************************************************************************/
1254 00016758 # ldd_er_halt( halt_code )
1255 00016758 # int halt_code;
1256 00016758 # {
1257 00016758 13 00ff jbr L365
1258 0001675B L366:
1259 0001675B # sgl_value_1 = dbl_ld_acc.m;
1260 0001675B 0d effffff4df effffff4da movl _dbl_ld_acc,_sgl_value_1
1261 00016766 # sgl_value_2 = dbl_ld_acc.l;
1262 00016766 0d effffff4d8 effffff4cf movl _dbl_ld_acc+4,_sgl_value_2
1263 00016771 # sgl_value_3 = dbl_st_acc.m;
1264 00016771 0d effffff4c9 effffff4c4 movl _dbl_st_acc,_sgl_value_3
1265 0001677C # sgl_value_4 = dbl_st_acc.l;
1266 0001677C 0d effffff4c2 effffff4b9 movl _dbl_st_acc+4,_sgl_value_4
1267 00016787 # sgl_dummy1 = halt_code; /* get the error type */
1268 00016787 0d ad04 effffff4b1 movl 4(fp),_sgl_dummy1
1269 0001678F # asm("movl _test_no,r0"); /* r0 = test number */
1270 0001678F 0d effffff4ab 50 movl _test_no,r0
1271 00016796 # asm("movl _subtest,r1"); /* r1 = subtest number */
1272 00016796 0d effffff4a4 51 movl _subtest,r1
1273 0001679D # asm("movl _sgl_dummy1,r2"); /* r2 = error code */
1274 0001679D 0d effffff49d 52 movl _sgl_dummy1,r2
1275 000167A4 # asm("movl _cycle,r3"); /* r3 = cycle count */
1276 000167A4 0d effffff496 53 movl _cycle,r3
1277 000167AB # asm("movl _sgl_value_1,r4"); /* r4 = MS operand */
1278 000167AB 0d effffff48f 54 movl _sgl_value_1,r4
1279 000167B2 # asm("movl _sgl_value_2,r5"); /* r5 = LS operand */
1280 000167B2 0d effffff488 55 movl _sgl_value_2,r5
1281 000167B9 # asm("movl _sgl_value_3,r6"); /* r6 = MS actual value */
1282 000167B9 0d effffff481 56 movl _sgl_value_3,r6
1283 000167C0 # asm("movl _sgl_value_4,r7"); /* r7 = LS actual value */
1284 000167C0 0d effffff47a 57 movl _sgl_value_4,r7
1285 000167C7 # if( halt_code == BAD_ACC_HLT ) {
1286 000167C7 1d ad04 01 cmpl 4(fp),$1
1287 000167CB 21 2d jneq L367
1288 000167CD # sgl_value_1 = dbl_expected.m;
1289 000167CD 0d effffff46d effffff468 movl _dbl_expected,_sgl_value_1
1290 000167D8 # sgl_value_2 = dbl_expected.l;
1291 000167D8 0d effffff466 effffff45d movl _dbl_expected+4,_sgl_value_2
1292 000167E3 # asm("movl _sgl_value_1,r8"); /* r8 = MS expected */
1293 000167E3 0d effffff457 58 movl _sgl_value_1,r8
1294 000167EA # asm("movl _sgl_value_2,r9"); /* r9 = LS expected */
1295 000167EA 0d effffff450 59 movl _sgl_value_2,r9
1296 000167F1 # asm("movl _index,r10"); /* r10 = data index */
1297 000167F1 0d effffff449 5a movl _index,r10
1298 000167F8 # } else
1299 000167F8 11 5e jbr L368
1300 000167FA L367:
1301 000167FA # if( halt_code == BAD_REG_HLT ) {
1302 000167FA 1d ad04 02 cmpl 4(fp),$2
1303 000167FE 21 3d jneq L369
1304 00016800 # sgl_dummy1 = load_regs[index2];
1305 00016800 0d effffff43a 50 movl _index2,r0
1306 00016807 0d 40effffff432 movl _load_regs[r0],_sgl_dummy1
effffff42d
1307 00016813 # sgl_dummy2 = store_regs[index2];
1308 00016813 0d effffff427 50 movl _index2,r0
1309 0001681A 0d 40effffff41f movl _store_regs[r0],_sgl_dummy2
effffff41a
1310 00016826 # asm("movl _index2,r8"); /* r8 = bad register # */
1311 00016826 0d effffff414 58 movl _index2,r8
1312 0001682D # asm("movl _sgl_dummy2,r9"); /* r9 = actual value */
1313 0001682D 0d effffff40d 59 movl _sgl_dummy2,r9
1314 00016834 # asm("movl _sgl_dummy1,r10"); /* r10 = expected value */
1315 00016834 0d effffff406 5a movl _sgl_dummy1,r10
1316 0001683B # } else
1317 0001683B 11 1b jbr L370
1318 0001683D L369:
1319 0001683D # if( halt_code == BAD_PSL_HLT ) {
1320 0001683D 1d ad04 03 cmpl 4(fp),$3
1321 00016841 21 15 jneq L371
1322 00016843 # asm("movl _init_psl,r8"); /* r8 = initial PSL */
1323 00016843 0d effffff3f7 58 movl _init_psl,r8
1324 0001684A # asm("movl _psl_val,r9"); /* r9 = final PSL */
1325 0001684A 0d effffff3f0 59 movl _psl_val,r9
1326 00016851 # asm("movl _exp_psl,r10"); /* r10 = expected PSL */
1327 00016851 0d effffff3e9 5a movl _exp_psl,r10
1328 00016858 # };
1329 00016858 L371:
1330 00016858 L370:
1331 00016858 L368:
1332 00016858 # asm("halt"); /* HALT ... */
1333 00016858 00 halt
1334 00016859 # }
1335 00016859 40 ret#2
1336 0001685A .set L363,0x0
1337 0001685A L365:
1338 0001685A 13 fefe jbr L366
1339 0001685D .data
1339 0002C49D .data
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