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1.1 root 1:
2: #include "fpp_defs.h"
3:
4:
5: /*****************************************************************************
6: *
7: * LND - DOUBLE PRECISION FLOATING POINT LOAD_NEGATE TEST
8: *
9: *****************************************************************************/
10: lnd()
11: {
12: asm(".globl _lnd_t");
13: asm("_lnd_t:"); /* entry address */
14: if( ( cycle == 1 ) && ( prt_hdrs ) ) /* print headers on 1st pass */
15: writes(" LND");
16: lnd_1(); /* load through a register */
17: lnd_2(); /* load through the cache */
18: lnd_3(); /* register stability */
19: lnd_4(); /* PSL stability test */
20: asm("jmp *return"); /* return to the test monitor */
21: }
22:
23:
24:
25: /************************************************************************
26: *
27: * SUBTEST 1 - load_negate through a register
28: *
29: ************************************************************************/
30: lnd_1()
31: {
32: force_loop = FALSE;
33: subtest = 1;
34: for( index = 0; index < max_lnd_1_index; index++ ) {
35: sgl_value_1 = lnd_1_data[index].ld.m; /* get operands MSW */
36: sgl_value_2 = lnd_1_data[index].ld.l; /* get operands LSW */
37: dbl_expected = lnd_1_data[index].exp; /* get expected result */
38: dbl_ld_acc.m = sgl_value_1;
39: dbl_ld_acc.l = sgl_value_2;
40: /*
41: * If LOOP ON ERROR is set, this is the loop for this subtest.
42: * The force loop flag is set after the first error.
43: */
44: asm("_lnd_1_lp1:");
45: asm("movl _sgl_value_1,r4"); /* put the value to negate */
46: asm("movl _sgl_value_2,r5"); /* in r6 and r7 */
47: asm("lnd r4"); /* load and negate value */
48: asm("std r6"); /* store the result in r6 */
49: if( force_loop ) /* and r7 */
50: asm("brb _lnd_1_lp1");; /* loop on the error */
51: /*
52: * end error loop - test the results
53: */
54: asm("movl r6,_sgl_value_3"); /* move R6 data to cache */
55: asm("movl r7,_sgl_value_4"); /* move R7 data to cache */
56: dbl_st_acc.m = sgl_value_3;
57: dbl_st_acc.l = sgl_value_4;
58: if( ( sgl_value_3 != dbl_expected.m ) ||/* COMPARE the values */
59: ( sgl_value_4 != dbl_expected.l ) ){
60: errcnt++; /* bump the error count */
61: if( prt_error ) {
62: writes(" \n"); /* start a new print line */
63: writes("cycle: ");
64: writed( cycle );
65: writes(" LND test ");
66: writed( test_no );
67: writes(", subtest 1 (Reg. Data) - BAD FINAL ACC\n");
68: print_lnd_data();
69: writes(", index = ");
70: writed( index );
71: writec('\n');
72: writes(" Acc expected = ");
73: write32h( dbl_expected.m );
74: writec(' ');
75: writes( dbl_expected.l );
76: writec('\n');
77: }
78: if( halt_flg )
79: lnd_er_halt( BAD_ACC_HLT ); /* halt on the error */
80: if( loop_on_err ) {
81: force_loop = TRUE; /* set the force loop flag */
82: asm("brw _lnd_1_lp1");; /* and loop on the error */
83: } /* end of loop on error */
84: } /* end of compare error */
85: } /* end of WHILE loop */
86: } /* end of subtest 1 */
87:
88:
89:
90: /************************************************************************
91: *
92: * SUBTEST 2 - load_negate through memory
93: *
94: ************************************************************************/
95: lnd_2()
96: {
97: force_loop = FALSE;
98: subtest = 2;
99: for( index = 0; index < max_lnd_1_index; index++ ) {
100: dbl_ld_acc = lnd_1_data[index].ld; /* get value to negate */
101: dbl_expected = lnd_1_data[index].exp; /* get expected result */
102: /*
103: * If LOOP ON ERROR is set, this is the loop for this subtest.
104: * The force loop flag is set after the first error.
105: */
106: asm("_lnd_2_lp1:");
107: asm("lnd _dbl_ld_acc"); /* load and negate the value */
108: asm("std _dbl_st_acc"); /* store the result */
109: if( force_loop )
110: asm("brb _lnd_2_lp1");; /* loop on the error */
111: /*
112: * end error loop - test the results
113: */
114: if( (dbl_st_acc.m != dbl_expected.m) || /* compare the final & */
115: (dbl_st_acc.l != dbl_expected.l) ) { /* the expected values */
116: errcnt++; /* bump the error count */
117: if( prt_error ) {
118: writes(" \n"); /* start a new print line */
119: writes("cycle: ");
120: writed( cycle );
121: writes(" LND test ");
122: writed( test_no );
123: writes(", subtest 2 (Cache Data) - BAD FINAL ACC\n");
124: print_lnd_data();
125: writes(", index = ");
126: writed( index );
127: writec('\n');
128: writes(" Acc expected = ");
129: write32h( dbl_expected.m );
130: writec(' ');
131: writes( dbl_expected.l );
132: writec('\n');
133: }
134: if( halt_flg )
135: lnd_er_halt( BAD_ACC_HLT ); /* halt on the error */
136: if( loop_on_err ) {
137: force_loop = TRUE; /* set the force loop flag */
138: asm("brw _lnd_2_lp1");; /* and loop on the error */
139: } /* end of loop on error */
140: } /* end of compare error */
141: } /* end of WHILE loop */
142: } /* end of subtest 2 */
143:
144:
145:
146: /************************************************************************
147: *
148: * SUBTEST 3 - Check for register corruption
149: *
150: ************************************************************************/
151: lnd_3()
152: {
153: force_loop = FALSE; /* clear force_loop flg */
154: subtest = 3;
155: fill_reg_buf( load_regs ); /* get patterns for regs */
156: index = 0;
157: dbl_ld_acc = lnd_1_data[index].ld; /* get value to negate */
158: dbl_expected = lnd_1_data[index].exp; /* get expected result */
159: /*
160: * If LOOP ON ERROR is set, this is the loop for this subtest.
161: * The force loop flag is set after the first error.
162: */
163: asm("_lnd_3_lp1:");
164: asm("loadr $0x1fff,_load_regs"); /* load regs 0 - 12 */
165: asm("nop");
166: asm("lnd _dbl_ld_acc"); /* load and negate the value */
167: asm("nop");
168: asm("storer $0x1fff,_store_regs"); /* store regs 0 - 12 */
169: asm("stf _dbl_st_acc"); /* save the accumulator */
170: if( force_loop )
171: asm("brb _lnd_3_lp1");; /* loop on the error */
172: /*
173: * Now compare the stored register values to those that were loaded
174: */
175: index2 = 0;
176: while( (load_regs[index2] == store_regs[index2]) && (index2 < 13) )
177: index2++; /* check reg values */
178: if( index2 < 13 ) { /* error if index2 < 13 */
179: errcnt++; /* bump the error count */
180: if( prt_error ) {
181: writes(" \n"); /* start a new print line */
182: writes("cycle: ");
183: writed( cycle );
184: writes(" LND test ");
185: writed( test_no );
186: writes(", subtest 3 - A REGISTER WAS CHANGED\n");
187: print_lnd_data(); /* print the operands */
188: writes("\n");
189: writes("register "); /* print the information */
190: writed( index2 ); /* about the corrupted */
191: writes(" = "); /* register */
192: write32h( store_regs[index2] );
193: writes(", should be = ");
194: write32h( load_regs[index2] );
195: writes("\n");
196: }
197: if( halt_flg )
198: lnd_er_halt( BAD_REG_HLT ); /* halt on the error */
199: if( loop_on_err ) {
200: force_loop = TRUE; /* set the force loop flag */
201: asm("brw _lnd_3_lp1");; /* and loop on the error */
202: } /* end of loop on error */
203: } /* end of register corruption error */
204: } /* end of subtest 3 */
205:
206:
207:
208: /************************************************************************
209: *
210: * SUBTEST 4 - Check for PSL corruption
211: *
212: ************************************************************************/
213: lnd_4()
214: {
215: force_loop = FALSE; /* clear force_loop flg */
216: subtest = 4;
217: fill_reg_buf( load_regs ); /* get patterns for regs */
218: for( index = 0; index < 3; index++ ) {
219: dbl_ld_acc = lnd_1_data[index].ld; /* get value to negate */
220: dbl_expected = lnd_1_data[index].exp; /* get expected */
221: sgl_dummy1 = status_array[status_index]; /* status = +, -, 0 */
222: /*
223: * If LOOP ON ERROR is set, this is the loop for this subtest.
224: * The force loop flag is set after the first error.
225: */
226: asm("_lnd_4_lp1:");
227: asm("tstl _sgl_dummy1"); /* set the PSL status */
228: asm("movpsl _init_psl"); /* save the initial PSL */
229: asm("lnd _dbl_ld_acc"); /* load and negate the value */
230: asm("nop");
231: asm("movpsl _psl_val"); /* save the final PSL */
232: asm("stf _dbl_st_acc"); /* save the accumulator */
233: if( force_loop )
234: asm("brb _lnd_4_lp1");; /* loop on the error */
235: /*
236: * Now compare the final PSL to the initial PSL -they should be the same
237: */
238: exp_psl = init_psl;
239: if( psl_val != init_psl ) {
240: errcnt++; /* bump the error count */
241: if( prt_error ) {
242: writes(" \n"); /* start a new print line */
243: writes("cycle: ");
244: writed( cycle );
245: writes(" LND test ");
246: writed( test_no );
247: writes(", subtest 4 - INCORRECT FINAL PSL\n");
248: print_lnd_data(); /* print the operands */
249: writes("\n");
250: writes("initial PSL = ");
251: write32h( init_psl );
252: writes(", final PSL = ");
253: write32h( psl_val );
254: writes(", expected PSL = ");
255: write32h( exp_psl );
256: writes("\n");
257: }
258: if( halt_flg )
259: lnd_er_halt( BAD_PSL_HLT ); /* halt on the error */
260: if( loop_on_err ) {
261: force_loop = TRUE; /* set the force loop flag */
262: asm("brw _lnd_4_lp1");; /* and loop on the error */
263: } /* end of loop on error */
264: } /* end of PSL corruption error */
265: } /* end of WHILE loop */
266: } /* end of subtest 4 */
267:
268:
269:
270: /**************************************************************************
271: *
272: * PRINT THE DATA AND STORE RESULTS
273: *
274: * Acc loaded = xxxxxxxx xxxxxxxx, Acc stored = xxxxxxxx xxxxxxxx, index = xx
275: * Acc expected = xxxxxxxx xxxxxxxx
276: **************************************************************************/
277: print_lnd_data()
278: {
279: writes(" Acc loaded = ");
280: write32h( dbl_ld_acc.m );
281: writec(' ');
282: write32h( dbl_ld_acc.l );
283: writes(", Acc. stored = ");
284: write32h( dbl_st_acc.m );
285: writec(' ');
286: write32h( dbl_st_acc.l );
287: }
288:
289:
290:
291: /**************************************************************************
292: *
293: * HALT ON ERROR ROUTINE
294: *
295: **************************************************************************/
296: lnd_er_halt( halt_code )
297: int halt_code;
298: {
299: sgl_value_1 = dbl_ld_acc.m;
300: sgl_value_2 = dbl_ld_acc.l;
301: sgl_value_3 = dbl_st_acc.m;
302: sgl_value_4 = dbl_st_acc.l;
303: sgl_dummy1 = halt_code; /* get the error type */
304: asm("movl _test_no,r0"); /* r0 = test number */
305: asm("movl _subtest,r1"); /* r1 = subtest number */
306: asm("movl _sgl_dummy1,r2"); /* r2 = error code */
307: asm("movl _cycle,r3"); /* r3 = cycle count */
308: asm("movl _sgl_value_1,r4"); /* r4 = MS operand 1 */
309: asm("movl _sgl_value_2,r5"); /* r5 = LS operand 1 */
310: asm("movl _sgl_value_3,r6"); /* r6 = MS result */
311: asm("movl _sgl_value_4,r7"); /* r7 = LS result */
312: if( halt_code == BAD_ACC_HLT ) {
313: sgl_value_1 = dbl_expected.m;
314: sgl_value_2 = dbl_expected.l;
315: asm("movl _sgl_value_1,r8"); /* r8 = MS expected */
316: asm("movl _sgl_value_2,r9"); /* r9 = LS expected */
317: asm("movl _index,r10"); /* r10 = data index */
318: } else
319: if( halt_code == BAD_REG_HLT ) {
320: sgl_dummy1 = load_regs[index2];
321: sgl_dummy2 = store_regs[index2];
322: asm("movl _index2,r8"); /* r8 = bad register # */
323: asm("movl _sgl_dummy2,r9"); /* r9 = actual value */
324: asm("movl _sgl_dummy1,r10"); /* r10 = expected value */
325: } else
326: if( halt_code == BAD_PSL_HLT ) {
327: asm("movl _init_psl,r8"); /* r8 = initial PSL */
328: asm("movl _psl_val,r9"); /* r9 = final PSL */
329: asm("movl _exp_psl,r10"); /* r10 = expected PSL */
330: };
331: asm("halt"); /* HALT ... */
332: }
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