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Up to [Power 6/32 Unix Tahoe 4.2BSD] / cci / d / macro4|
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Power 6/32 Unix version 1.21
1 00000000 LL0:
2 00000000 .data
3 000008ac * .text
4 00000000 .align 1
5 00000000 .globl _lnd
6 00000000 _lnd:
7 00019D00 0000 .word L215
8 00019D02 #
9 00019D02 # #include "fpp_defs.h"
10 00019D02 #
11 00019D02 #
12 00019D02 # /*****************************************************************************
13 00019D02 # *
14 00019D02 # * LND - DOUBLE PRECISION FLOATING POINT LOAD_NEGATE TEST
15 00019D02 # *
16 00019D02 # *****************************************************************************/
17 00019D02 # lnd()
18 00019D02 # {
19 00019D02 11 41 jbr L217
20 00019D04 L218:
21 00019D04 # asm(".globl _lnd_t");
22 00019D04 .globl _lnd_t
23 00019D04 # asm("_lnd_t:"); /* entry address */
24 00019D04 _lnd_t:
25 00019D04 # if( ( cycle == 1 ) && ( prt_hdrs ) ) /* print headers on 1st pass */
26 00019D04 1d effffffff6 01 cmpl _cycle,$1
27 00019D0B 21 15 jneq L219
28 00019D0D 5d efffffffed tstl _prt_hdrs
29 00019D13 31 0d jeql L219
30 00019D15 # writes(" LND");
31 00019D15 .data 1
32 000008ac * L221:
33 000008ac * 204C4E4400 .ascii " LND\0"
34 000008b1 * .text
35 00019D15 dd 8f000008ac pushl $L221
36 00019D1B fe 08 efffffffde callf $8,_writes
37 00019D22 # lnd_1(); /* load through a register */
38 00019D22 L219:
39 00019D22 fe 04 ef0000001f callf $4,_lnd_1
40 00019D29 # lnd_2(); /* load through the cache */
41 00019D29 fe 04 ef000001f0 callf $4,_lnd_2
42 00019D30 # lnd_3(); /* register stability */
43 00019D30 fe 04 ef00000373 callf $4,_lnd_3
44 00019D37 # lnd_4(); /* PSL stability test */
45 00019D37 fe 04 ef0000053c callf $4,_lnd_4
46 00019D3E # asm("jmp *return"); /* return to the test monitor */
47 00019D3E 71 ffffffffbc jmp *return
48 00019D44 # }
49 00019D44 40 ret#2
50 00019D45 .set L215,0x0
51 00019D45 L217:
52 00019D45 11 bd jbr L218
53 00019D47 .data
54 000008ac * .text
55 00019D47 00 .align 1
56 00019D48 .globl _lnd_1
57 00019D48 _lnd_1:
58 00019D48 0000 .word L226
59 00019D4A #
60 00019D4A #
61 00019D4A #
62 00019D4A # /************************************************************************
63 00019D4A # *
64 00019D4A # * SUBTEST 1 - load_negate through a register
65 00019D4A # *
66 00019D4A # ************************************************************************/
67 00019D4A # lnd_1()
68 00019D4A # {
69 00019D4A 13 01cf jbr L228
70 00019D4D L229:
71 00019D4D # force_loop = FALSE;
72 00019D4D 4d efffffffad clrl _force_loop
73 00019D53 # subtest = 1;
74 00019D53 0d 01 efffffffa6 movl $1,_subtest
75 00019D5A # for( index = 0; index < max_lnd_1_index; index++ ) {
76 00019D5A 4d efffffffa0 clrl _index
77 00019D60 L232:
78 00019D60 1d efffffff9a efffffff95 cmpl _index,_max_lnd_1_index
79 00019D6B 91 03 13 01ab jgeq L231
80 00019D70 # sgl_value_1 = lnd_1_data[index].ld.m; /* get operands MSW */
81 00019D70 0d efffffff8a 50 movl _index,r0
82 00019D77 48 04 50 50 shll $4,r0,r0
83 00019D7B 0d e000000000 efffffff7a movl _lnd_1_data(r0),_sgl_value_1
84 00019D86 # sgl_value_2 = lnd_1_data[index].ld.l; /* get operands LSW */
85 00019D86 0d efffffff74 50 movl _index,r0
86 00019D8D 48 04 50 50 shll $4,r0,r0
87 00019D91 0d e000000004 efffffff64 movl _lnd_1_data+4(r0),_sgl_value_2
88 00019D9C # dbl_expected = lnd_1_data[index].exp; /* get expected result */
89 00019D9C 48 04 efffffff5d 50 shll $4,_index,r0
90 00019DA4 0c 8f00000008 50 addl2 $_lnd_1_data+8,r0
91 00019DAB 0d a004 efffffff51 movl 4(r0),_dbl_expected+4
92 00019DB3 0d 60 efffffff46 movl (r0),_dbl_expected
93 00019DBA # dbl_ld_acc.m = sgl_value_1;
94 00019DBA 0d efffffff40 efffffff3b movl _sgl_value_1,_dbl_ld_acc
95 00019DC5 # dbl_ld_acc.l = sgl_value_2;
96 00019DC5 0d efffffff35 efffffff34 movl _sgl_value_2,_dbl_ld_acc+4
97 00019DD0 # /*
98 00019DD0 # * If LOOP ON ERROR is set, this is the loop for this subtest.
99 00019DD0 # * The force loop flag is set after the first error.
100 00019DD0 # */
101 00019DD0 # asm("_lnd_1_lp1:");
102 00019DD0 _lnd_1_lp1:
103 00019DD0 # asm("movl _sgl_value_1,r4"); /* put the value to negate */
104 00019DD0 0d efffffff2a 54 movl _sgl_value_1,r4
105 00019DD7 # asm("movl _sgl_value_2,r5"); /* in r6 and r7 */
106 00019DD7 0d efffffff23 55 movl _sgl_value_2,r5
107 00019DDE # asm("lnd r4"); /* load and negate value */
108 00019DDE 17 54 lnd r4
109 00019DE0 # asm("std r6"); /* store the result in r6 */
110 00019DE0 27 56 std r6
111 00019DE2 # if( force_loop ) /* and r7 */
112 00019DE2 5d efffffff18 tstl _force_loop
113 00019DE8 31 02 jeql L233
114 00019DEA # asm("brb _lnd_1_lp1");; /* loop on the error */
115 00019DEA 11 e4 brb _lnd_1_lp1
116 00019DEC L233:
117 00019DEC # /*
118 00019DEC # * end error loop - test the results
119 00019DEC # */
120 00019DEC # asm("movl r6,_sgl_value_3"); /* move R6 data to cache */
121 00019DEC 0d 56 efffffff0d movl r6,_sgl_value_3
122 00019DF3 # asm("movl r7,_sgl_value_4"); /* move R7 data to cache */
123 00019DF3 0d 57 efffffff06 movl r7,_sgl_value_4
124 00019DFA # dbl_st_acc.m = sgl_value_3;
125 00019DFA 0d efffffff00 effffffefb movl _sgl_value_3,_dbl_st_acc
126 00019E05 # dbl_st_acc.l = sgl_value_4;
127 00019E05 0d effffffef5 effffffef4 movl _sgl_value_4,_dbl_st_acc+4
128 00019E10 # if( ( sgl_value_3 != dbl_expected.m ) ||/* COMPARE the values */
129 00019E10 # ( sgl_value_4 != dbl_expected.l ) ){
130 00019E10 1d effffffeea effffffee5 cmpl _sgl_value_3,_dbl_expected
131 00019E1B 21 10 jneq L9999
132 00019E1D 1d effffffedd effffffedc cmpl _sgl_value_4,_dbl_expected+4
133 00019E28 21 03 13 00e5 jeql L234
134 00019E2D L9999:
135 00019E2D # errcnt++; /* bump the error count */
136 00019E2D 6d effffffecd incl _errcnt
137 00019E33 # if( prt_error ) {
138 00019E33 5d effffffec7 tstl _prt_error
139 00019E39 21 03 13 00b1 jeql L235
140 00019E3E # writes(" \n"); /* start a new print line */
141 00019E3E .data 1
142 000008b1 * L236:
143 000008b1 * 200A00 .ascii " \12\0"
144 000008b4 * .text
145 00019E3E dd 8f000008b1 pushl $L236
146 00019E44 fe 08 effffffeb5 callf $8,_writes
147 00019E4B # writes("cycle: ");
148 00019E4B .data 1
149 000008b4 * L237:
150 000008b4 * 6379636C653A2000 .ascii "cycle: \0"
151 000008bc * .text
152 00019E4B dd 8f000008b4 pushl $L237
153 00019E51 fe 08 effffffea8 callf $8,_writes
154 00019E58 # writed( cycle );
155 00019E58 dd effffffea2 pushl _cycle
156 00019E5E fe 08 effffffe9b callf $8,_writed
157 00019E65 # writes(" LND test ");
158 00019E65 .data 1
159 000008bc * L239:
160 000008bc * 20204C4E4420746573742000 .ascii " LND test \0"
161 000008c8 * .text
162 00019E65 dd 8f000008bc pushl $L239
163 00019E6B fe 08 effffffe8e callf $8,_writes
164 00019E72 # writed( test_no );
165 00019E72 dd effffffe88 pushl _test_no
166 00019E78 fe 08 effffffe81 callf $8,_writed
167 00019E7F # writes(", subtest 1 (Reg. Data) - BAD FINAL ACC\n");
168 00019E7F .data 1
169 000008c8 * L240:
170 000008c8 * 2C20737562746573742031202 .ascii ", subtest 1 (Reg. Data) - BAD FINAL ACC\12\0"
85265672E204461746129202D
204241442046494E414C20414
3430A00
171 000008f1 * .text
172 00019E7F dd 8f000008c8 pushl $L240
173 00019E85 fe 08 effffffe74 callf $8,_writes
174 00019E8C # print_lnd_data();
175 00019E8C fe 04 ef000005a9 callf $4,_print_lnd_data
176 00019E93 # writes(", index = ");
177 00019E93 .data 1
178 000008f1 * L242:
179 000008f1 * 2C202020696E646578203D200 .ascii ", index = \0"
0
180 000008fe * .text
181 00019E93 dd 8f000008f1 pushl $L242
182 00019E99 fe 08 effffffe60 callf $8,_writes
183 00019EA0 # writed( index );
184 00019EA0 dd effffffe5a pushl _index
185 00019EA6 fe 08 effffffe53 callf $8,_writed
186 00019EAD # writec('\n');
187 00019EAD dd 0a pushl $10
188 00019EAF fe 08 effffffe4a callf $8,_writec
189 00019EB6 # writes(" Acc expected = ");
190 00019EB6 .data 1
191 000008fe * L244:
192 000008fe * 2020202020202020202020202 .ascii " Acc expected = \0"
0202020202020202020202020
2020202020202020416363206
578706563746564203D2000
193 0000092f * .text
194 00019EB6 dd 8f000008fe pushl $L244
195 00019EBC fe 08 effffffe3d callf $8,_writes
196 00019EC3 # write32h( dbl_expected.m );
197 00019EC3 dd effffffe37 pushl _dbl_expected
198 00019EC9 fe 08 effffffe30 callf $8,_write32h
199 00019ED0 # writec(' ');
200 00019ED0 dd 20 pushl $32
201 00019ED2 fe 08 effffffe27 callf $8,_writec
202 00019ED9 # writes( dbl_expected.l );
203 00019ED9 dd effffffe25 pushl _dbl_expected+4
204 00019EDF fe 08 effffffe1a callf $8,_writes
205 00019EE6 # writec('\n');
206 00019EE6 dd 0a pushl $10
207 00019EE8 fe 08 effffffe11 callf $8,_writec
208 00019EEF # }
209 00019EEF # if( halt_flg )
210 00019EEF L235:
211 00019EEF 5d effffffe0b tstl _halt_flg
212 00019EF5 31 09 jeql L246
213 00019EF7 # lnd_er_halt( BAD_ACC_HLT ); /* halt on the error */
214 00019EF7 dd 01 pushl $1
215 00019EF9 fe 08 ef000005a4 callf $8,_lnd_er_halt
216 00019F00 # if( loop_on_err ) {
217 00019F00 L246:
218 00019F00 5d effffffdfa tstl _loop_on_err
219 00019F06 31 0a jeql L248
220 00019F08 # force_loop = TRUE; /* set the force loop flag */
221 00019F08 0d 01 effffffdf1 movl $1,_force_loop
222 00019F0F # asm("brw _lnd_1_lp1");; /* and loop on the error */
223 00019F0F 13 febe brw _lnd_1_lp1
224 00019F12 # } /* end of loop on error */
225 00019F12 # } /* end of compare error */
226 00019F12 L248:
227 00019F12 # } /* end of WHILE loop */
228 00019F12 L234:
229 00019F12 L230:
230 00019F12 6d effffffde8 incl _index
231 00019F18 13 fe45 jbr L232
232 00019F1B L231:
233 00019F1B # } /* end of subtest 1 */
234 00019F1B 40 ret#2
235 00019F1C .set L226,0x0
236 00019F1C L228:
237 00019F1C 13 fe2e jbr L229
238 00019F1F .data
239 000008ac * .text
240 00019F1F 00 .align 1
241 00019F20 .globl _lnd_2
242 00019F20 _lnd_2:
243 00019F20 0000 .word L249
244 00019F22 #
245 00019F22 #
246 00019F22 #
247 00019F22 # /************************************************************************
248 00019F22 # *
249 00019F22 # * SUBTEST 2 - load_negate through memory
250 00019F22 # *
251 00019F22 # ************************************************************************/
252 00019F22 # lnd_2()
253 00019F22 # {
254 00019F22 13 0181 jbr L251
255 00019F25 L252:
256 00019F25 # force_loop = FALSE;
257 00019F25 4d effffffdd5 clrl _force_loop
258 00019F2B # subtest = 2;
259 00019F2B 0d 02 effffffdce movl $2,_subtest
260 00019F32 # for( index = 0; index < max_lnd_1_index; index++ ) {
261 00019F32 4d effffffdc8 clrl _index
262 00019F38 L255:
263 00019F38 1d effffffdc2 effffffdbd cmpl _index,_max_lnd_1_index
264 00019F43 91 03 13 015d jgeq L254
265 00019F48 # dbl_ld_acc = lnd_1_data[index].ld; /* get value to negate */
266 00019F48 48 04 effffffdb1 50 shll $4,_index,r0
267 00019F50 0c 8f00000000 50 addl2 $_lnd_1_data,r0
268 00019F57 0d a004 effffffda5 movl 4(r0),_dbl_ld_acc+4
269 00019F5F 0d 60 effffffd9a movl (r0),_dbl_ld_acc
270 00019F66 # dbl_expected = lnd_1_data[index].exp; /* get expected result */
271 00019F66 48 04 effffffd93 50 shll $4,_index,r0
272 00019F6E 0c 8f00000008 50 addl2 $_lnd_1_data+8,r0
273 00019F75 0d a004 effffffd87 movl 4(r0),_dbl_expected+4
274 00019F7D 0d 60 effffffd7c movl (r0),_dbl_expected
275 00019F84 # /*
276 00019F84 # * If LOOP ON ERROR is set, this is the loop for this subtest.
277 00019F84 # * The force loop flag is set after the first error.
278 00019F84 # */
279 00019F84 # asm("_lnd_2_lp1:");
280 00019F84 _lnd_2_lp1:
281 00019F84 # asm("lnd _dbl_ld_acc"); /* load and negate the value */
282 00019F84 17 effffffd76 lnd _dbl_ld_acc
283 00019F8A # asm("std _dbl_st_acc"); /* store the result */
284 00019F8A 27 effffffd70 std _dbl_st_acc
285 00019F90 # if( force_loop )
286 00019F90 5d effffffd6a tstl _force_loop
287 00019F96 31 02 jeql L256
288 00019F98 # asm("brb _lnd_2_lp1");; /* loop on the error */
289 00019F98 11 ea brb _lnd_2_lp1
290 00019F9A L256:
291 00019F9A # /*
292 00019F9A # * end error loop - test the results
293 00019F9A # */
294 00019F9A # if( (dbl_st_acc.m != dbl_expected.m) || /* compare the final & */
295 00019F9A # (dbl_st_acc.l != dbl_expected.l) ) { /* the expected values */
296 00019F9A 1d effffffd60 effffffd5b cmpl _dbl_st_acc,_dbl_expected
297 00019FA5 21 10 jneq L9998
298 00019FA7 1d effffffd57 effffffd52 cmpl _dbl_st_acc+4,_dbl_expected+4
299 00019FB2 21 03 13 00e5 jeql L257
300 00019FB7 L9998:
301 00019FB7 # errcnt++; /* bump the error count */
302 00019FB7 6d effffffd43 incl _errcnt
303 00019FBD # if( prt_error ) {
304 00019FBD 5d effffffd3d tstl _prt_error
305 00019FC3 21 03 13 00b1 jeql L258
306 00019FC8 # writes(" \n"); /* start a new print line */
307 00019FC8 .data 1
308 0000092f * L259:
309 0000092f * 200A00 .ascii " \12\0"
310 00000932 * .text
311 00019FC8 dd 8f0000092f pushl $L259
312 00019FCE fe 08 effffffd2b callf $8,_writes
313 00019FD5 # writes("cycle: ");
314 00019FD5 .data 1
315 00000932 * L260:
316 00000932 * 6379636C653A2000 .ascii "cycle: \0"
317 0000093a * .text
318 00019FD5 dd 8f00000932 pushl $L260
319 00019FDB fe 08 effffffd1e callf $8,_writes
320 00019FE2 # writed( cycle );
321 00019FE2 dd effffffd18 pushl _cycle
322 00019FE8 fe 08 effffffd11 callf $8,_writed
323 00019FEF # writes(" LND test ");
324 00019FEF .data 1
325 0000093a * L261:
326 0000093a * 20204C4E4420746573742000 .ascii " LND test \0"
327 00000946 * .text
328 00019FEF dd 8f0000093a pushl $L261
329 00019FF5 fe 08 effffffd04 callf $8,_writes
330 00019FFC # writed( test_no );
331 00019FFC dd effffffcfe pushl _test_no
332 0001A002 fe 08 effffffcf7 callf $8,_writed
333 0001A009 # writes(", subtest 2 (Cache Data) - BAD FINAL ACC\n");
334 0001A009 .data 1
335 00000946 * L262:
336 00000946 * 2C20737562746573742032202 .ascii ", subtest 2 (Cache Data) - BAD FINAL ACC\12\0"
8436163686520446174612920
2D204241442046494E414C204
143430A00
337 00000970 * .text
338 0001A009 dd 8f00000946 pushl $L262
339 0001A00F fe 08 effffffcea callf $8,_writes
340 0001A016 # print_lnd_data();
341 0001A016 fe 04 ef0000041f callf $4,_print_lnd_data
342 0001A01D # writes(", index = ");
343 0001A01D .data 1
344 00000970 * L263:
345 00000970 * 2C202020696E646578203D200 .ascii ", index = \0"
0
346 0000097d * .text
347 0001A01D dd 8f00000970 pushl $L263
348 0001A023 fe 08 effffffcd6 callf $8,_writes
349 0001A02A # writed( index );
350 0001A02A dd effffffcd0 pushl _index
351 0001A030 fe 08 effffffcc9 callf $8,_writed
352 0001A037 # writec('\n');
353 0001A037 dd 0a pushl $10
354 0001A039 fe 08 effffffcc0 callf $8,_writec
355 0001A040 # writes(" Acc expected = ");
356 0001A040 .data 1
357 0000097d * L264:
358 0000097d * 2020202020202020202020202 .ascii " Acc expected = \0"
0202020202020202020202020
2020202020202020416363206
578706563746564203D2000
359 000009ae * .text
360 0001A040 dd 8f0000097d pushl $L264
361 0001A046 fe 08 effffffcb3 callf $8,_writes
362 0001A04D # write32h( dbl_expected.m );
363 0001A04D dd effffffcad pushl _dbl_expected
364 0001A053 fe 08 effffffca6 callf $8,_write32h
365 0001A05A # writec(' ');
366 0001A05A dd 20 pushl $32
367 0001A05C fe 08 effffffc9d callf $8,_writec
368 0001A063 # writes( dbl_expected.l );
369 0001A063 dd effffffc9b pushl _dbl_expected+4
370 0001A069 fe 08 effffffc90 callf $8,_writes
371 0001A070 # writec('\n');
372 0001A070 dd 0a pushl $10
373 0001A072 fe 08 effffffc87 callf $8,_writec
374 0001A079 # }
375 0001A079 # if( halt_flg )
376 0001A079 L258:
377 0001A079 5d effffffc81 tstl _halt_flg
378 0001A07F 31 09 jeql L265
379 0001A081 # lnd_er_halt( BAD_ACC_HLT ); /* halt on the error */
380 0001A081 dd 01 pushl $1
381 0001A083 fe 08 ef0000041a callf $8,_lnd_er_halt
382 0001A08A # if( loop_on_err ) {
383 0001A08A L265:
384 0001A08A 5d effffffc70 tstl _loop_on_err
385 0001A090 31 0a jeql L266
386 0001A092 # force_loop = TRUE; /* set the force loop flag */
387 0001A092 0d 01 effffffc67 movl $1,_force_loop
388 0001A099 # asm("brw _lnd_2_lp1");; /* and loop on the error */
389 0001A099 13 fee8 brw _lnd_2_lp1
390 0001A09C # } /* end of loop on error */
391 0001A09C # } /* end of compare error */
392 0001A09C L266:
393 0001A09C # } /* end of WHILE loop */
394 0001A09C L257:
395 0001A09C L253:
396 0001A09C 6d effffffc5e incl _index
397 0001A0A2 13 fe93 jbr L255
398 0001A0A5 L254:
399 0001A0A5 # } /* end of subtest 2 */
400 0001A0A5 40 ret#2
401 0001A0A6 .set L249,0x0
402 0001A0A6 L251:
403 0001A0A6 13 fe7c jbr L252
404 0001A0A9 .data
405 000008ac * .text
406 0001A0A9 00 .align 1
407 0001A0AA .globl _lnd_3
408 0001A0AA _lnd_3:
409 0001A0AA 0000 .word L267
410 0001A0AC #
411 0001A0AC #
412 0001A0AC #
413 0001A0AC # /************************************************************************
414 0001A0AC # *
415 0001A0AC # * SUBTEST 3 - Check for register corruption
416 0001A0AC # *
417 0001A0AC # ************************************************************************/
418 0001A0AC # lnd_3()
419 0001A0AC # {
420 0001A0AC 13 01c8 jbr L269
421 0001A0AF L270:
422 0001A0AF # force_loop = FALSE; /* clear force_loop flg */
423 0001A0AF 4d effffffc4b clrl _force_loop
424 0001A0B5 # subtest = 3;
425 0001A0B5 0d 03 effffffc44 movl $3,_subtest
426 0001A0BC # fill_reg_buf( load_regs ); /* get patterns for regs */
427 0001A0BC dd 8f00000000 pushl $_load_regs
428 0001A0C2 fe 08 effffffc37 callf $8,_fill_reg_buf
429 0001A0C9 # index = 0;
430 0001A0C9 4d effffffc31 clrl _index
431 0001A0CF # dbl_ld_acc = lnd_1_data[index].ld; /* get value to negate */
432 0001A0CF 48 04 effffffc2a 50 shll $4,_index,r0
433 0001A0D7 0c 8f00000000 50 addl2 $_lnd_1_data,r0
434 0001A0DE 0d a004 effffffc1e movl 4(r0),_dbl_ld_acc+4
435 0001A0E6 0d 60 effffffc13 movl (r0),_dbl_ld_acc
436 0001A0ED # dbl_expected = lnd_1_data[index].exp; /* get expected result */
437 0001A0ED 48 04 effffffc0c 50 shll $4,_index,r0
438 0001A0F5 0c 8f00000008 50 addl2 $_lnd_1_data+8,r0
439 0001A0FC 0d a004 effffffc00 movl 4(r0),_dbl_expected+4
440 0001A104 0d 60 effffffbf5 movl (r0),_dbl_expected
441 0001A10B # /*
442 0001A10B # * If LOOP ON ERROR is set, this is the loop for this subtest.
443 0001A10B # * The force loop flag is set after the first error.
444 0001A10B # */
445 0001A10B # asm("_lnd_3_lp1:");
446 0001A10B _lnd_3_lp1:
447 0001A10B # asm("loadr $0x1fff,_load_regs"); /* load regs 0 - 12 */
448 0001A10B ab 891fff effffffbec loadr $0x1fff,_load_regs
449 0001A114 # asm("nop");
450 0001A114 10 nop
451 0001A115 # asm("lnd _dbl_ld_acc"); /* load and negate the value */
452 0001A115 17 effffffbe5 lnd _dbl_ld_acc
453 0001A11B # asm("nop");
454 0001A11B 10 nop
455 0001A11C # asm("storer $0x1fff,_store_regs"); /* store regs 0 - 12 */
456 0001A11C bb 891fff effffffbdb storer $0x1fff,_store_regs
457 0001A125 # asm("stf _dbl_st_acc"); /* save the accumulator */
458 0001A125 26 effffffbd5 stf _dbl_st_acc
459 0001A12B # if( force_loop )
460 0001A12B 5d effffffbcf tstl _force_loop
461 0001A131 31 02 jeql L272
462 0001A133 # asm("brb _lnd_3_lp1");; /* loop on the error */
463 0001A133 11 d6 brb _lnd_3_lp1
464 0001A135 L272:
465 0001A135 # /*
466 0001A135 # * Now compare the stored register values to those that were loaded
467 0001A135 # */
468 0001A135 # index2 = 0;
469 0001A135 4d effffffbc5 clrl _index2
470 0001A13B # while( (load_regs[index2] == store_regs[index2]) && (index2 < 13) )
471 0001A13B L273:
472 0001A13B 0d effffffbbf 50 movl _index2,r0
473 0001A142 0d effffffbb8 51 movl _index2,r1
474 0001A149 1d 40effffffbb0 cmpl _load_regs[r0],_store_regs[r1]
41effffffbaa
475 0001A156 21 11 jneq L274
476 0001A158 1d effffffba2 0d cmpl _index2,$13
477 0001A15F 81 08 jgeq L274
478 0001A161 # index2++; /* check reg values */
479 0001A161 6d effffffb99 incl _index2
480 0001A167 11 d2 jbr L273
481 0001A169 L274:
482 0001A169 # if( index2 < 13 ) { /* error if index2 < 13 */
483 0001A169 1d effffffb91 0d cmpl _index2,$13
484 0001A170 91 03 13 0101 jgeq L275
485 0001A175 # errcnt++; /* bump the error count */
486 0001A175 6d effffffb85 incl _errcnt
487 0001A17B # if( prt_error ) {
488 0001A17B 5d effffffb7f tstl _prt_error
489 0001A181 21 03 13 00cd jeql L276
490 0001A186 # writes(" \n"); /* start a new print line */
491 0001A186 .data 1
492 000009ae * L277:
493 000009ae * 200A00 .ascii " \12\0"
494 000009b1 * .text
495 0001A186 dd 8f000009ae pushl $L277
496 0001A18C fe 08 effffffb6d callf $8,_writes
497 0001A193 # writes("cycle: ");
498 0001A193 .data 1
499 000009b1 * L278:
500 000009b1 * 6379636C653A2000 .ascii "cycle: \0"
501 000009b9 * .text
502 0001A193 dd 8f000009b1 pushl $L278
503 0001A199 fe 08 effffffb60 callf $8,_writes
504 0001A1A0 # writed( cycle );
505 0001A1A0 dd effffffb5a pushl _cycle
506 0001A1A6 fe 08 effffffb53 callf $8,_writed
507 0001A1AD # writes(" LND test ");
508 0001A1AD .data 1
509 000009b9 * L279:
510 000009b9 * 20204C4E4420746573742000 .ascii " LND test \0"
511 000009c5 * .text
512 0001A1AD dd 8f000009b9 pushl $L279
513 0001A1B3 fe 08 effffffb46 callf $8,_writes
514 0001A1BA # writed( test_no );
515 0001A1BA dd effffffb40 pushl _test_no
516 0001A1C0 fe 08 effffffb39 callf $8,_writed
517 0001A1C7 # writes(", subtest 3 - A REGISTER WAS CHANGED\n");
518 0001A1C7 .data 1
519 000009c5 * L280:
520 000009c5 * 2C20737562746573742033202 .ascii ", subtest 3 - A REGISTER WAS CHANGED\12\0"
D204120524547495354455220
574153204348414E4745440A0
0
521 000009eb * .text
522 0001A1C7 dd 8f000009c5 pushl $L280
523 0001A1CD fe 08 effffffb2c callf $8,_writes
524 0001A1D4 # print_lnd_data(); /* print the operands */
525 0001A1D4 fe 04 ef00000261 callf $4,_print_lnd_data
526 0001A1DB # writes("\n");
527 0001A1DB .data 1
528 000009eb * L281:
529 000009eb * 0A00 .ascii "\12\0"
530 000009ed * .text
531 0001A1DB dd 8f000009eb pushl $L281
532 0001A1E1 fe 08 effffffb18 callf $8,_writes
533 0001A1E8 # writes("register "); /* print the information */
534 0001A1E8 .data 1
535 000009ed * L282:
536 000009ed * 72656769737465722000 .ascii "register \0"
537 000009f7 * .text
538 0001A1E8 dd 8f000009ed pushl $L282
539 0001A1EE fe 08 effffffb0b callf $8,_writes
540 0001A1F5 # writed( index2 ); /* about the corrupted */
541 0001A1F5 dd effffffb05 pushl _index2
542 0001A1FB fe 08 effffffafe callf $8,_writed
543 0001A202 # writes(" = "); /* register */
544 0001A202 .data 1
545 000009f7 * L283:
546 000009f7 * 203D2000 .ascii " = \0"
547 000009fb * .text
548 0001A202 dd 8f000009f7 pushl $L283
549 0001A208 fe 08 effffffaf1 callf $8,_writes
550 0001A20F # write32h( store_regs[index2] );
551 0001A20F 0d effffffaeb 50 movl _index2,r0
552 0001A216 dd 40effffffae3 pushl _store_regs[r0]
553 0001A21D fe 08 effffffadc callf $8,_write32h
554 0001A224 # writes(", should be = ");
555 0001A224 .data 1
556 000009fb * L284:
557 000009fb * 2C202073686F756C642062652 .ascii ", should be = \0"
03D2000
558 00000a0b * .text
559 0001A224 dd 8f000009fb pushl $L284
560 0001A22A fe 08 effffffacf callf $8,_writes
561 0001A231 # write32h( load_regs[index2] );
562 0001A231 0d effffffac9 50 movl _index2,r0
563 0001A238 dd 40effffffac1 pushl _load_regs[r0]
564 0001A23F fe 08 effffffaba callf $8,_write32h
565 0001A246 # writes("\n");
566 0001A246 .data 1
567 00000a0b * L285:
568 00000a0b * 0A00 .ascii "\12\0"
569 00000a0d * .text
570 0001A246 dd 8f00000a0b pushl $L285
571 0001A24C fe 08 effffffaad callf $8,_writes
572 0001A253 # }
573 0001A253 # if( halt_flg )
574 0001A253 L276:
575 0001A253 5d effffffaa7 tstl _halt_flg
576 0001A259 31 09 jeql L286
577 0001A25B # lnd_er_halt( BAD_REG_HLT ); /* halt on the error */
578 0001A25B dd 02 pushl $2
579 0001A25D fe 08 ef00000240 callf $8,_lnd_er_halt
580 0001A264 # if( loop_on_err ) {
581 0001A264 L286:
582 0001A264 5d effffffa96 tstl _loop_on_err
583 0001A26A 31 0a jeql L287
584 0001A26C # force_loop = TRUE; /* set the force loop flag */
585 0001A26C 0d 01 effffffa8d movl $1,_force_loop
586 0001A273 # asm("brw _lnd_3_lp1");; /* and loop on the error */
587 0001A273 13 fe95 brw _lnd_3_lp1
588 0001A276 # } /* end of loop on error */
589 0001A276 # } /* end of register corruption error */
590 0001A276 L287:
591 0001A276 # } /* end of subtest 3 */
592 0001A276 L275:
593 0001A276 40 ret#2
594 0001A277 .set L267,0x0
595 0001A277 L269:
596 0001A277 13 fe35 jbr L270
597 0001A27A .data
598 000008ac * .text
599 0001A27A .align 1
600 0001A27A .globl _lnd_4
601 0001A27A _lnd_4:
602 0001A27A 0000 .word L288
603 0001A27C #
604 0001A27C #
605 0001A27C #
606 0001A27C # /************************************************************************
607 0001A27C # *
608 0001A27C # * SUBTEST 4 - Check for PSL corruption
609 0001A27C # *
610 0001A27C # ************************************************************************/
611 0001A27C # lnd_4()
612 0001A27C # {
613 0001A27C 13 01ba jbr L290
614 0001A27F L291:
615 0001A27F # force_loop = FALSE; /* clear force_loop flg */
616 0001A27F 4d effffffa7b clrl _force_loop
617 0001A285 # subtest = 4;
618 0001A285 0d 04 effffffa74 movl $4,_subtest
619 0001A28C # fill_reg_buf( load_regs ); /* get patterns for regs */
620 0001A28C dd 8f00000000 pushl $_load_regs
621 0001A292 fe 08 effffffa67 callf $8,_fill_reg_buf
622 0001A299 # for( index = 0; index < 3; index++ ) {
623 0001A299 4d effffffa61 clrl _index
624 0001A29F L294:
625 0001A29F 1d effffffa5b 03 cmpl _index,$3
626 0001A2A6 91 03 13 018d jgeq L293
627 0001A2AB # dbl_ld_acc = lnd_1_data[index].ld; /* get value to negate */
628 0001A2AB 48 04 effffffa4e 50 shll $4,_index,r0
629 0001A2B3 0c 8f00000000 50 addl2 $_lnd_1_data,r0
630 0001A2BA 0d a004 effffffa42 movl 4(r0),_dbl_ld_acc+4
631 0001A2C2 0d 60 effffffa37 movl (r0),_dbl_ld_acc
632 0001A2C9 # dbl_expected = lnd_1_data[index].exp; /* get expected */
633 0001A2C9 48 04 effffffa30 50 shll $4,_index,r0
634 0001A2D1 0c 8f00000008 50 addl2 $_lnd_1_data+8,r0
635 0001A2D8 0d a004 effffffa24 movl 4(r0),_dbl_expected+4
636 0001A2E0 0d 60 effffffa19 movl (r0),_dbl_expected
637 0001A2E7 # sgl_dummy1 = status_array[status_index]; /* status = +, -, 0 */
638 0001A2E7 0d effffffa13 50 movl _status_index,r0
639 0001A2EE 0d 40effffffa0b movl _status_array[r0],_sgl_dummy1
effffffa06
640 0001A2FA # /*
641 0001A2FA # * If LOOP ON ERROR is set, this is the loop for this subtest.
642 0001A2FA # * The force loop flag is set after the first error.
643 0001A2FA # */
644 0001A2FA # asm("_lnd_4_lp1:");
645 0001A2FA _lnd_4_lp1:
646 0001A2FA # asm("tstl _sgl_dummy1"); /* set the PSL status */
647 0001A2FA 5d effffffa00 tstl _sgl_dummy1
648 0001A300 # asm("movpsl _init_psl"); /* save the initial PSL */
649 0001A300 cd effffff9fa movpsl _init_psl
650 0001A306 # asm("lnd _dbl_ld_acc"); /* load and negate the value */
651 0001A306 17 effffff9f4 lnd _dbl_ld_acc
652 0001A30C # asm("nop");
653 0001A30C 10 nop
654 0001A30D # asm("movpsl _psl_val"); /* save the final PSL */
655 0001A30D cd effffff9ed movpsl _psl_val
656 0001A313 # asm("stf _dbl_st_acc"); /* save the accumulator */
657 0001A313 26 effffff9e7 stf _dbl_st_acc
658 0001A319 # if( force_loop )
659 0001A319 5d effffff9e1 tstl _force_loop
660 0001A31F 31 02 jeql L295
661 0001A321 # asm("brb _lnd_4_lp1");; /* loop on the error */
662 0001A321 11 d7 brb _lnd_4_lp1
663 0001A323 L295:
664 0001A323 # /*
665 0001A323 # * Now compare the final PSL to the initial PSL -they should be the same
666 0001A323 # */
667 0001A323 # exp_psl = init_psl;
668 0001A323 0d effffff9d7 effffff9d2 movl _init_psl,_exp_psl
669 0001A32E # if( psl_val != init_psl ) {
670 0001A32E 1d effffff9cc effffff9c7 cmpl _psl_val,_init_psl
671 0001A339 21 03 13 00f1 jeql L296
672 0001A33E # errcnt++; /* bump the error count */
673 0001A33E 6d effffff9bc incl _errcnt
674 0001A344 # if( prt_error ) {
675 0001A344 5d effffff9b6 tstl _prt_error
676 0001A34A 21 03 13 00bd jeql L297
677 0001A34F # writes(" \n"); /* start a new print line */
678 0001A34F .data 1
679 00000a0d * L298:
680 00000a0d * 200A00 .ascii " \12\0"
681 00000a10 * .text
682 0001A34F dd 8f00000a0d pushl $L298
683 0001A355 fe 08 effffff9a4 callf $8,_writes
684 0001A35C # writes("cycle: ");
685 0001A35C .data 1
686 00000a10 * L299:
687 00000a10 * 6379636C653A2000 .ascii "cycle: \0"
688 00000a18 * .text
689 0001A35C dd 8f00000a10 pushl $L299
690 0001A362 fe 08 effffff997 callf $8,_writes
691 0001A369 # writed( cycle );
692 0001A369 dd effffff991 pushl _cycle
693 0001A36F fe 08 effffff98a callf $8,_writed
694 0001A376 # writes(" LND test ");
695 0001A376 .data 1
696 00000a18 * L300:
697 00000a18 * 20204C4E4420746573742000 .ascii " LND test \0"
698 00000a24 * .text
699 0001A376 dd 8f00000a18 pushl $L300
700 0001A37C fe 08 effffff97d callf $8,_writes
701 0001A383 # writed( test_no );
702 0001A383 dd effffff977 pushl _test_no
703 0001A389 fe 08 effffff970 callf $8,_writed
704 0001A390 # writes(", subtest 4 - INCORRECT FINAL PSL\n");
705 0001A390 .data 1
706 00000a24 * L301:
707 00000a24 * 2C20737562746573742034202 .ascii ", subtest 4 - INCORRECT FINAL PSL\12\0"
D20494E434F52524543542046
494E414C2050534C0A00
708 00000a47 * .text
709 0001A390 dd 8f00000a24 pushl $L301
710 0001A396 fe 08 effffff963 callf $8,_writes
711 0001A39D # print_lnd_data(); /* print the operands */
712 0001A39D fe 04 ef00000098 callf $4,_print_lnd_data
713 0001A3A4 # writes("\n");
714 0001A3A4 .data 1
715 00000a47 * L302:
716 00000a47 * 0A00 .ascii "\12\0"
717 00000a49 * .text
718 0001A3A4 dd 8f00000a47 pushl $L302
719 0001A3AA fe 08 effffff94f callf $8,_writes
720 0001A3B1 # writes("initial PSL = ");
721 0001A3B1 .data 1
722 00000a49 * L303:
723 00000a49 * 696E697469616C2050534C203 .ascii "initial PSL = \0"
D2000
724 00000a58 * .text
725 0001A3B1 dd 8f00000a49 pushl $L303
726 0001A3B7 fe 08 effffff942 callf $8,_writes
727 0001A3BE # write32h( init_psl );
728 0001A3BE dd effffff93c pushl _init_psl
729 0001A3C4 fe 08 effffff935 callf $8,_write32h
730 0001A3CB # writes(", final PSL = ");
731 0001A3CB .data 1
732 00000a58 * L304:
733 00000a58 * 2C202066696E616C2050534C2 .ascii ", final PSL = \0"
03D2000
734 00000a68 * .text
735 0001A3CB dd 8f00000a58 pushl $L304
736 0001A3D1 fe 08 effffff928 callf $8,_writes
737 0001A3D8 # write32h( psl_val );
738 0001A3D8 dd effffff922 pushl _psl_val
739 0001A3DE fe 08 effffff91b callf $8,_write32h
740 0001A3E5 # writes(", expected PSL = ");
741 0001A3E5 .data 1
742 00000a68 * L305:
743 00000a68 * 2C20206578706563746564205 .ascii ", expected PSL = \0"
0534C203D2000
744 00000a7b * .text
745 0001A3E5 dd 8f00000a68 pushl $L305
746 0001A3EB fe 08 effffff90e callf $8,_writes
747 0001A3F2 # write32h( exp_psl );
748 0001A3F2 dd effffff908 pushl _exp_psl
749 0001A3F8 fe 08 effffff901 callf $8,_write32h
750 0001A3FF # writes("\n");
751 0001A3FF .data 1
752 00000a7b * L306:
753 00000a7b * 0A00 .ascii "\12\0"
754 00000a7d * .text
755 0001A3FF dd 8f00000a7b pushl $L306
756 0001A405 fe 08 effffff8f4 callf $8,_writes
757 0001A40C # }
758 0001A40C # if( halt_flg )
759 0001A40C L297:
760 0001A40C 5d effffff8ee tstl _halt_flg
761 0001A412 31 09 jeql L307
762 0001A414 # lnd_er_halt( BAD_PSL_HLT ); /* halt on the error */
763 0001A414 dd 03 pushl $3
764 0001A416 fe 08 ef00000087 callf $8,_lnd_er_halt
765 0001A41D # if( loop_on_err ) {
766 0001A41D L307:
767 0001A41D 5d effffff8dd tstl _loop_on_err
768 0001A423 31 0a jeql L308
769 0001A425 # force_loop = TRUE; /* set the force loop flag */
770 0001A425 0d 01 effffff8d4 movl $1,_force_loop
771 0001A42C # asm("brw _lnd_4_lp1");; /* and loop on the error */
772 0001A42C 13 fecb brw _lnd_4_lp1
773 0001A42F # } /* end of loop on error */
774 0001A42F # } /* end of PSL corruption error */
775 0001A42F L308:
776 0001A42F # } /* end of WHILE loop */
777 0001A42F L296:
778 0001A42F L292:
779 0001A42F 6d effffff8cb incl _index
780 0001A435 13 fe67 jbr L294
781 0001A438 L293:
782 0001A438 # } /* end of subtest 4 */
783 0001A438 40 ret#2
784 0001A439 .set L288,0x0
785 0001A439 L290:
786 0001A439 13 fe43 jbr L291
787 0001A43C .data
788 000008ac * .text
789 0001A43C .align 1
790 0001A43C .globl _print_lnd_data
791 0001A43C _print_lnd_data:
792 0001A43C 0000 .word L309
793 0001A43E #
794 0001A43E #
795 0001A43E #
796 0001A43E # /**************************************************************************
797 0001A43E # *
798 0001A43E # * PRINT THE DATA AND STORE RESULTS
799 0001A43E # *
800 0001A43E # * Acc loaded = xxxxxxxx xxxxxxxx, Acc stored = xxxxxxxx xxxxxxxx, index = xx
801 0001A43E # * Acc expected = xxxxxxxx xxxxxxxx
802 0001A43E # **************************************************************************/
803 0001A43E # print_lnd_data()
804 0001A43E # {
805 0001A43E 11 61 jbr L311
806 0001A440 L312:
807 0001A440 # writes(" Acc loaded = ");
808 0001A440 .data 1
809 00000a7d * L313:
810 00000a7d * 20416363206C6F61646564203 .ascii " Acc loaded = \0"
D2000
811 00000a8c * .text
812 0001A440 dd 8f00000a7d pushl $L313
813 0001A446 fe 08 effffff8b3 callf $8,_writes
814 0001A44D # write32h( dbl_ld_acc.m );
815 0001A44D dd effffff8ad pushl _dbl_ld_acc
816 0001A453 fe 08 effffff8a6 callf $8,_write32h
817 0001A45A # writec(' ');
818 0001A45A dd 20 pushl $32
819 0001A45C fe 08 effffff89d callf $8,_writec
820 0001A463 # write32h( dbl_ld_acc.l );
821 0001A463 dd effffff89b pushl _dbl_ld_acc+4
822 0001A469 fe 08 effffff890 callf $8,_write32h
823 0001A470 # writes(", Acc. stored = ");
824 0001A470 .data 1
825 00000a8c * L314:
826 00000a8c * 2C20204163632E2073746F726 .ascii ", Acc. stored = \0"
564203D2000
827 00000a9e * .text
828 0001A470 dd 8f00000a8c pushl $L314
829 0001A476 fe 08 effffff883 callf $8,_writes
830 0001A47D # write32h( dbl_st_acc.m );
831 0001A47D dd effffff87d pushl _dbl_st_acc
832 0001A483 fe 08 effffff876 callf $8,_write32h
833 0001A48A # writec(' ');
834 0001A48A dd 20 pushl $32
835 0001A48C fe 08 effffff86d callf $8,_writec
836 0001A493 # write32h( dbl_st_acc.l );
837 0001A493 dd effffff86b pushl _dbl_st_acc+4
838 0001A499 fe 08 effffff860 callf $8,_write32h
839 0001A4A0 # }
840 0001A4A0 40 ret#2
841 0001A4A1 .set L309,0x0
842 0001A4A1 L311:
843 0001A4A1 11 9d jbr L312
844 0001A4A3 .data
845 000008ac * .text
846 0001A4A3 00 .align 1
847 0001A4A4 .globl _lnd_er_halt
848 0001A4A4 _lnd_er_halt:
849 0001A4A4 0000 .word L315
850 0001A4A6 #
851 0001A4A6 #
852 0001A4A6 #
853 0001A4A6 # /**************************************************************************
854 0001A4A6 # *
855 0001A4A6 # * HALT ON ERROR ROUTINE
856 0001A4A6 # *
857 0001A4A6 # **************************************************************************/
858 0001A4A6 # lnd_er_halt( halt_code )
859 0001A4A6 # int halt_code;
860 0001A4A6 # {
861 0001A4A6 13 00ff jbr L317
862 0001A4A9 L318:
863 0001A4A9 # sgl_value_1 = dbl_ld_acc.m;
864 0001A4A9 0d effffff851 effffff84c movl _dbl_ld_acc,_sgl_value_1
865 0001A4B4 # sgl_value_2 = dbl_ld_acc.l;
866 0001A4B4 0d effffff84a effffff841 movl _dbl_ld_acc+4,_sgl_value_2
867 0001A4BF # sgl_value_3 = dbl_st_acc.m;
868 0001A4BF 0d effffff83b effffff836 movl _dbl_st_acc,_sgl_value_3
869 0001A4CA # sgl_value_4 = dbl_st_acc.l;
870 0001A4CA 0d effffff834 effffff82b movl _dbl_st_acc+4,_sgl_value_4
871 0001A4D5 # sgl_dummy1 = halt_code; /* get the error type */
872 0001A4D5 0d ad04 effffff823 movl 4(fp),_sgl_dummy1
873 0001A4DD # asm("movl _test_no,r0"); /* r0 = test number */
874 0001A4DD 0d effffff81d 50 movl _test_no,r0
875 0001A4E4 # asm("movl _subtest,r1"); /* r1 = subtest number */
876 0001A4E4 0d effffff816 51 movl _subtest,r1
877 0001A4EB # asm("movl _sgl_dummy1,r2"); /* r2 = error code */
878 0001A4EB 0d effffff80f 52 movl _sgl_dummy1,r2
879 0001A4F2 # asm("movl _cycle,r3"); /* r3 = cycle count */
880 0001A4F2 0d effffff808 53 movl _cycle,r3
881 0001A4F9 # asm("movl _sgl_value_1,r4"); /* r4 = MS operand 1 */
882 0001A4F9 0d effffff801 54 movl _sgl_value_1,r4
883 0001A500 # asm("movl _sgl_value_2,r5"); /* r5 = LS operand 1 */
884 0001A500 0d effffff7fa 55 movl _sgl_value_2,r5
885 0001A507 # asm("movl _sgl_value_3,r6"); /* r6 = MS result */
886 0001A507 0d effffff7f3 56 movl _sgl_value_3,r6
887 0001A50E # asm("movl _sgl_value_4,r7"); /* r7 = LS result */
888 0001A50E 0d effffff7ec 57 movl _sgl_value_4,r7
889 0001A515 # if( halt_code == BAD_ACC_HLT ) {
890 0001A515 1d ad04 01 cmpl 4(fp),$1
891 0001A519 21 2d jneq L319
892 0001A51B # sgl_value_1 = dbl_expected.m;
893 0001A51B 0d effffff7df effffff7da movl _dbl_expected,_sgl_value_1
894 0001A526 # sgl_value_2 = dbl_expected.l;
895 0001A526 0d effffff7d8 effffff7cf movl _dbl_expected+4,_sgl_value_2
896 0001A531 # asm("movl _sgl_value_1,r8"); /* r8 = MS expected */
897 0001A531 0d effffff7c9 58 movl _sgl_value_1,r8
898 0001A538 # asm("movl _sgl_value_2,r9"); /* r9 = LS expected */
899 0001A538 0d effffff7c2 59 movl _sgl_value_2,r9
900 0001A53F # asm("movl _index,r10"); /* r10 = data index */
901 0001A53F 0d effffff7bb 5a movl _index,r10
902 0001A546 # } else
903 0001A546 11 5e jbr L320
904 0001A548 L319:
905 0001A548 # if( halt_code == BAD_REG_HLT ) {
906 0001A548 1d ad04 02 cmpl 4(fp),$2
907 0001A54C 21 3d jneq L321
908 0001A54E # sgl_dummy1 = load_regs[index2];
909 0001A54E 0d effffff7ac 50 movl _index2,r0
910 0001A555 0d 40effffff7a4 movl _load_regs[r0],_sgl_dummy1
effffff79f
911 0001A561 # sgl_dummy2 = store_regs[index2];
912 0001A561 0d effffff799 50 movl _index2,r0
913 0001A568 0d 40effffff791 movl _store_regs[r0],_sgl_dummy2
effffff78c
914 0001A574 # asm("movl _index2,r8"); /* r8 = bad register # */
915 0001A574 0d effffff786 58 movl _index2,r8
916 0001A57B # asm("movl _sgl_dummy2,r9"); /* r9 = actual value */
917 0001A57B 0d effffff77f 59 movl _sgl_dummy2,r9
918 0001A582 # asm("movl _sgl_dummy1,r10"); /* r10 = expected value */
919 0001A582 0d effffff778 5a movl _sgl_dummy1,r10
920 0001A589 # } else
921 0001A589 11 1b jbr L322
922 0001A58B L321:
923 0001A58B # if( halt_code == BAD_PSL_HLT ) {
924 0001A58B 1d ad04 03 cmpl 4(fp),$3
925 0001A58F 21 15 jneq L323
926 0001A591 # asm("movl _init_psl,r8"); /* r8 = initial PSL */
927 0001A591 0d effffff769 58 movl _init_psl,r8
928 0001A598 # asm("movl _psl_val,r9"); /* r9 = final PSL */
929 0001A598 0d effffff762 59 movl _psl_val,r9
930 0001A59F # asm("movl _exp_psl,r10"); /* r10 = expected PSL */
931 0001A59F 0d effffff75b 5a movl _exp_psl,r10
932 0001A5A6 # };
933 0001A5A6 L323:
934 0001A5A6 L322:
935 0001A5A6 L320:
936 0001A5A6 # asm("halt"); /* HALT ... */
937 0001A5A6 00 halt
938 0001A5A7 # }
939 0001A5A7 40 ret#2
940 0001A5A8 .set L315,0x0
941 0001A5A8 L317:
942 0001A5A8 13 fefe jbr L318
943 0001A5AB .data
943 000342AB .data
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