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Up to [Power 6/32 Unix Tahoe 4.2BSD] / cci / d / macro4|
Return to monitor.lst CVS log | Up to [Power 6/32 Unix Tahoe 4.2BSD] / cci / d / macro4 |
1.1 root 1: 1 00000000 LL0:
2: 2 00000000 .data
3: 3 00000254 * .text
4: 4 00000000 .align 1
5: 5 00000000 .globl _monitor
6: 6 00000000 _monitor:
7: 7 0000C1E4 0000 .word L277
8: 8 0000C1E6 #
9: 9 0000C1E6 # #include "macro4_defs.h"
10: 10 0000C1E6 #
11: 11 0000C1E6 # /*********************************************************************
12: 12 0000C1E6 # *
13: 13 0000C1E6 # * MONITOR FOR THE FPP INSTRUCTION TESTS
14: 14 0000C1E6 # *
15: 15 0000C1E6 # * 20-Jul-85 : written
16: 16 0000C1E6 # *********************************************************************/
17: 17 0000C1E6 # monitor()
18: 18 0000C1E6 # {
19: 19 0000C1E6 13 01fe jbr L279
20: 20 0000C1E9 L280:
21: 21 0000C1E9 # int no_subtests; /* number of tests in the table */
22: 22 0000C1E9 # force_loop = FALSE; /* clear the 'force loop' flag */
23: 23 0000C1E9 4d effffffff5 clrl _force_loop
24: 24 0000C1EF # cycle = 0; /* clear the cycle count */
25: 25 0000C1EF 4d efffffffef clrl _cycle
26: 26 0000C1F5 # errcnt = 0; /* clear the error count */
27: 27 0000C1F5 4d efffffffe9 clrl _errcnt
28: 28 0000C1FB # error = FALSE; /* clear the current error flag */
29: 29 0000C1FB 4d efffffffe3 clrl _error
30: 30 0000C201 # if( no_fpp_wcs ) {
31: 31 0000C201 5d efffffffdd tstl _no_fpp_wcs
32: 32 0000C207 31 15 jeql L281
33: 33 0000C209 # test_tbl = no_fpp_test_tbl; /* use the NO-FPP tests */
34: 34 0000C209 0d 8f00000000 efffffffd0 movl $_no_fpp_test_tbl,_test_tbl
35: 35 0000C214 # no_subtests = no_fpp_test_cnt;
36: 36 0000C214 0d efffffffca adc8 movl _no_fpp_test_cnt,-56(fp)
37: 37 0000C21C # } else {
38: 38 0000C21C 11 13 jbr L282
39: 39 0000C21E L281:
40: 40 0000C21E # test_tbl = fpp_test_tbl; /* use the FPP tests */
41: 41 0000C21E 0d 8f00000000 efffffffbb movl $_fpp_test_tbl,_test_tbl
42: 42 0000C229 # no_subtests = fpp_test_cnt;
43: 43 0000C229 0d efffffffb5 adc8 movl _fpp_test_cnt,-56(fp)
44: 44 0000C231 # }
45: 45 0000C231 L282:
46: 46 0000C231 # /*
47: 47 0000C231 # * Print the Header information and enable the Data Cache if desired
48: 48 0000C231 # */
49: 49 0000C231 # if( prt_hdrs ) {
50: 50 0000C231 5d efffffffad tstl _prt_hdrs
51: 51 0000C237 31 31 jeql L283
52: 52 0000C239 # writes("\nMacro4 Test");
53: 53 0000C239 .data 1
54: 54 00000254 * L285:
55: 55 00000254 * 0A4D6163726F3420546573740 .ascii "\12Macro4 Test\0"
56: 0
57: 56 00000261 * .text
58: 57 0000C239 dd 8f00000254 pushl $L285
59: 58 0000C23F fe 08 efffffff9e callf $8,_writes
60: 59 0000C246 # if( no_fpp_wcs )
61: 60 0000C246 5d efffffff98 tstl _no_fpp_wcs
62: 61 0000C24C 31 0f jeql L286
63: 62 0000C24E # writes(" - FPP is NOT installed");
64: 63 0000C24E .data 1
65: 64 00000261 * L287:
66: 65 00000261 * 202D20465050206973204E4F5 .ascii " - FPP is NOT installed\0"
67: 420696E7374616C6C656400
68: 66 00000279 * .text
69: 67 0000C24E dd 8f00000261 pushl $L287
70: 68 0000C254 fe 08 efffffff89 callf $8,_writes
71: 69 0000C25B # else
72: 70 0000C25B 11 0d jbr L288
73: 71 0000C25D L286:
74: 72 0000C25D # writes(" - FPP is installed");
75: 73 0000C25D .data 1
76: 74 00000279 * L289:
77: 75 00000279 * 202D2046505020697320696E7 .ascii " - FPP is installed\0"
78: 374616C6C656400
79: 76 0000028d * .text
80: 77 0000C25D dd 8f00000279 pushl $L289
81: 78 0000C263 fe 08 efffffff7a callf $8,_writes
82: 79 0000C26A L288:
83: 80 0000C26A # }
84: 81 0000C26A # if( en_data_cache ) {
85: 82 0000C26A L283:
86: 83 0000C26A 5d efffffff74 tstl _en_data_cache
87: 84 0000C270 31 1d jeql L290
88: 85 0000C272 # if( prt_hdrs )
89: 86 0000C272 5d efffffff6c tstl _prt_hdrs
90: 87 0000C278 31 0d jeql L291
91: 88 0000C27A # writes(" - Data Cache Enabled: \n");
92: 89 0000C27A .data 1
93: 90 0000028d * L292:
94: 91 0000028d * 20202D2044617461204361636 .ascii " - Data Cache Enabled: \12\0"
95: 86520456E61626C65643A200A
96: 00
97: 92 000002a7 * .text
98: 93 0000C27A dd 8f0000028d pushl $L292
99: 94 0000C280 fe 08 efffffff5d callf $8,_writes
100: 95 0000C287 # asm("mtpr $1,$25"); /* purge all data cache pages */
101: 96 0000C287 L291:
102: 97 0000C287 ad 01 19 mtpr $1,$25
103: 98 0000C28A # asm("mtpr $1,$27"); /* enable the data cache */
104: 99 0000C28A ad 01 1b mtpr $1,$27
105: 100 0000C28D # } else {
106: 101 0000C28D 11 18 jbr L293
107: 102 0000C28F L290:
108: 103 0000C28F # if( prt_hdrs )
109: 104 0000C28F 5d efffffff4f tstl _prt_hdrs
110: 105 0000C295 31 0d jeql L294
111: 106 0000C297 # writes(" - Data Cache Disabled: \n");
112: 107 0000C297 .data 1
113: 108 000002a7 * L295:
114: 109 000002a7 * 20202D2044617461204361636 .ascii " - Data Cache Disabled: \12\0"
115: 8652044697361626C65643A20
116: 0A00
117: 110 000002c2 * .text
118: 111 0000C297 dd 8f000002a7 pushl $L295
119: 112 0000C29D fe 08 efffffff40 callf $8,_writes
120: 113 0000C2A4 # asm("mtpr $2,$27"); /* disable the data cache */
121: 114 0000C2A4 L294:
122: 115 0000C2A4 ad 02 1b mtpr $2,$27
123: 116 0000C2A7 # }
124: 117 0000C2A7 L293:
125: 118 0000C2A7 # /*
126: 119 0000C2A7 # * Check the run list to see if a specific test is called for
127: 120 0000C2A7 # */
128: 121 0000C2A7 # for( cycle = 1; ( (cycle <= count) || nonstop ); cycle++ ) {
129: 122 0000C2A7 0d 01 efffffff36 movl $1,_cycle
130: 123 0000C2AE L298:
131: 124 0000C2AE 1d efffffff30 efffffff2b cmpl _cycle,_count
132: 125 0000C2B9 51 0b jleq L9999
133: 126 0000C2BB 5d efffffff23 tstl _nonstop
134: 127 0000C2C1 21 03 13 0092 jeql L297
135: 128 0000C2C6 L9999:
136: 129 0000C2C6 # if( (prt_hdrs) && (cycle != 1) ) /* show we're still running */
137: 130 0000C2C6 5d efffffff18 tstl _prt_hdrs
138: 131 0000C2CC 31 12 jeql L299
139: 132 0000C2CE 1d efffffff10 01 cmpl _cycle,$1
140: 133 0000C2D5 31 09 jeql L299
141: 134 0000C2D7 # writec('.');
142: 135 0000C2D7 dd 2e pushl $46
143: 136 0000C2D9 fe 08 efffffff04 callf $8,_writec
144: 137 0000C2E0 # if( (run_list > 0) && /* run 1 test only */
145: 138 0000C2E0 L299:
146: 139 0000C2E0 # (run_list <= no_subtests) ) {
147: 140 0000C2E0 5d effffffefe tstl _run_list
148: 141 0000C2E6 51 33 jleq L301
149: 142 0000C2E8 1d effffffef6 adc8 cmpl _run_list,-56(fp)
150: 143 0000C2F0 41 29 jgtr L301
151: 144 0000C2F2 # test_no = run_list;
152: 145 0000C2F2 0d effffffeec effffffee7 movl _run_list,_test_no
153: 146 0000C2FD # test_index = run_list - 1;
154: 147 0000C2FD 3c 01 effffffee0 50 subl3 $1,_run_list,r0
155: 148 0000C305 0d 50 effffffed8 movl r0,_test_index
156: 149 0000C30C # sched_test( test_index ); /* run the test */
157: 150 0000C30C dd effffffed2 pushl _test_index
158: 151 0000C312 fe 08 ef000000d5 callf $8,_sched_test
159: 152 0000C319 # } else { /* run all tests */
160: 153 0000C319 11 34 jbr L303
161: 154 0000C31B L301:
162: 155 0000C31B # for(test_index=0; test_index<no_subtests; test_index++) {
163: 156 0000C31B 4d effffffec3 clrl _test_index
164: 157 0000C321 L306:
165: 158 0000C321 1d effffffebd adc8 cmpl _test_index,-56(fp)
166: 159 0000C329 81 24 jgeq L305
167: 160 0000C32B # test_no = test_index + 1;
168: 161 0000C32B 1c 01 effffffeb2 50 addl3 $1,_test_index,r0
169: 162 0000C333 0d 50 effffffeaa movl r0,_test_no
170: 163 0000C33A # sched_test( test_index ); /* run the test */
171: 164 0000C33A dd effffffea4 pushl _test_index
172: 165 0000C340 fe 08 ef000000a7 callf $8,_sched_test
173: 166 0000C347 # }
174: 167 0000C347 L304:
175: 168 0000C347 6d effffffe97 incl _test_index
176: 169 0000C34D 11 d2 jbr L306
177: 170 0000C34F L305:
178: 171 0000C34F # } /* end of test-all-instructions */
179: 172 0000C34F L303:
180: 173 0000C34F # } /* end of test cycles - done with the test */
181: 174 0000C34F L296:
182: 175 0000C34F 6d effffffe8f incl _cycle
183: 176 0000C355 13 ff56 jbr L298
184: 177 0000C358 L297:
185: 178 0000C358 # cycle--; /* correct cycle count */
186: 179 0000C358 7d effffffe86 decl _cycle
187: 180 0000C35E # if( prt_hdrs ) {
188: 181 0000C35E 5d effffffe80 tstl _prt_hdrs
189: 182 0000C364 31 61 jeql L307
190: 183 0000C366 # /* if( !error ) */
191: 184 0000C366 # writec('\n'); /* new line if no current errors */
192: 185 0000C366 dd 0a pushl $10
193: 186 0000C368 fe 08 effffffe75 callf $8,_writec
194: 187 0000C36F # writes("Cycles Complete = ");
195: 188 0000C36F .data 1
196: 189 000002c2 * L308:
197: 190 000002c2 * 4379636C657320436F6D706C6 .ascii "Cycles Complete = \0"
198: 57465203D2000
199: 191 000002d5 * .text
200: 192 0000C36F dd 8f000002c2 pushl $L308
201: 193 0000C375 fe 08 effffffe68 callf $8,_writes
202: 194 0000C37C # writed( cycle );
203: 195 0000C37C dd effffffe62 pushl _cycle
204: 196 0000C382 fe 08 effffffe5b callf $8,_writed
205: 197 0000C389 # if( errcnt ) {
206: 198 0000C389 5d effffffe55 tstl _errcnt
207: 199 0000C38F 31 29 jeql L310
208: 200 0000C391 # writes(", Error Count = " );
209: 201 0000C391 .data 1
210: 202 000002d5 * L311:
211: 203 000002d5 * 2C20204572726F7220436F756 .ascii ", Error Count = \0"
212: E74203D2000
213: 204 000002e7 * .text
214: 205 0000C391 dd 8f000002d5 pushl $L311
215: 206 0000C397 fe 08 effffffe46 callf $8,_writes
216: 207 0000C39E # writed( errcnt );
217: 208 0000C39E dd effffffe40 pushl _errcnt
218: 209 0000C3A4 fe 08 effffffe39 callf $8,_writed
219: 210 0000C3AB # writes(", Test Complete\n");
220: 211 0000C3AB .data 1
221: 212 000002e7 * L312:
222: 213 000002e7 * 2C20205465737420436F6D706 .ascii ", Test Complete\12\0"
223: C6574650A00
224: 214 000002f9 * .text
225: 215 0000C3AB dd 8f000002e7 pushl $L312
226: 216 0000C3B1 fe 08 effffffe2c callf $8,_writes
227: 217 0000C3B8 # } else
228: 218 0000C3B8 11 0d jbr L313
229: 219 0000C3BA L310:
230: 220 0000C3BA # writes(", TEST PASSED -NO ERRORS!!! \n");
231: 221 0000C3BA .data 1
232: 222 000002f9 * L314:
233: 223 000002f9 * 2C20205445535420504153534 .ascii ", TEST PASSED -NO ERRORS!!! \12\0"
234: 544202D4E4F204552524F5253
235: 212121200A00
236: 224 00000318 * .text
237: 225 0000C3BA dd 8f000002f9 pushl $L314
238: 226 0000C3C0 fe 08 effffffe1d callf $8,_writes
239: 227 0000C3C7 L313:
240: 228 0000C3C7 # };
241: 229 0000C3C7 L307:
242: 230 0000C3C7 # /*
243: 231 0000C3C7 # * Set up the registers to halt
244: 232 0000C3C7 # */
245: 233 0000C3C7 # asm("movl _errcnt,r0"); /* set error count for halt */
246: 234 0000C3C7 0d effffffe17 50 movl _errcnt,r0
247: 235 0000C3CE # asm("bneq 1f");
248: 236 0000C3CE 21 07 bneq 1f
249: 237 0000C3D0 # asm("movl $0xCAFEBABE,r0");; /* set the no-error flag */
250: 238 0000C3D0 0d 8fcafebabe 50 movl $0xCAFEBABE,r0
251: 239 0000C3D7 # asm("1:");
252: 240 0000C3D7 1:
253: 241 0000C3D7 # asm("movl _OPTIONS,r1"); /* restore options to r1 */
254: 242 0000C3D7 0d effffffe07 51 movl _OPTIONS,r1
255: 243 0000C3DE # asm("movl _cycle,r2"); /* move cycle count to r2 */
256: 244 0000C3DE 0d effffffe00 52 movl _cycle,r2
257: 245 0000C3E5 # asm("halt");;
258: 246 0000C3E5 00 halt
259: 247 0000C3E6 # }
260: 248 0000C3E6 40 ret#2
261: 249 0000C3E7 .set L277,0x0
262: 250 0000C3E7 L279:
263: 251 0000C3E7 3c 38 5d 5e subl3 $56,fp,sp
264: 252 0000C3EB 13 fdfb jbr L280
265: 253 0000C3EE .data
266: 254 00000254 * .text
267: 255 0000C3EE .align 1
268: 256 0000C3EE .globl _sched_test
269: 257 0000C3EE _sched_test:
270: 258 0000C3EE 0000 .word L315
271: 259 0000C3F0 #
272: 260 0000C3F0 #
273: 261 0000C3F0 #
274: 262 0000C3F0 # /***********************************************************************
275: 263 0000C3F0 # *
276: 264 0000C3F0 # * Start the current subtest
277: 265 0000C3F0 # *
278: 266 0000C3F0 # * The test may come back here after an unexpected event so the monitor's
279: 267 0000C3F0 # * stack and frame pointers are saved. Funny things happen if we try to
280: 268 0000C3F0 # * exit from this routine with the wrong frame pointer. Unexpected events
281: 269 0000C3F0 # * will either return indirectly through "return" or they will just halt.
282: 270 0000C3F0 # *
283: 271 0000C3F0 # ***********************************************************************/
284: 272 0000C3F0 # sched_test( test_index )
285: 273 0000C3F0 # int test_index;
286: 274 0000C3F0 # {
287: 275 0000C3F0 11 43 jbr L317
288: 276 0000C3F2 L318:
289: 277 0000C3F2 # asm("moval (r13),_monitor_fp"); /* save the frame ptr */
290: 278 0000C3F2 ed 6d effffffdeb moval (r13),_monitor_fp
291: 279 0000C3F9 # asm("moval (r14),_monitor_sp"); /* save the stack ptr */
292: 280 0000C3F9 ed 6e effffffde4 moval (r14),_monitor_sp
293: 281 0000C400 # test_ptr = test_tbl[ test_index ]; /* get ptr to test */
294: 282 0000C400 0d ad04 50 movl 4(fp),r0
295: 283 0000C404 48 02 50 50 shll $2,r0,r0
296: 284 0000C408 1c 50 effffffdd5 50 addl3 r0,_test_tbl,r0
297: 285 0000C410 0d 60 effffffdcd movl (r0),_test_ptr
298: 286 0000C417 # asm("jmp *_test_ptr"); /* execute the test */
299: 287 0000C417 71 fffffffdc7 jmp *_test_ptr
300: 288 0000C41D # asm(".globl _sched_return");
301: 289 0000C41D .globl _sched_return
302: 290 0000C41D # asm("_sched_return:"); /* return here after the test */
303: 291 0000C41D _sched_return:
304: 292 0000C41D # asm("nop");
305: 293 0000C41D 10 nop
306: 294 0000C41E # asm("movl _monitor_fp,r13"); /* restore the frame pointer */
307: 295 0000C41E 0d effffffdc0 5d movl _monitor_fp,r13
308: 296 0000C425 # asm("movl _monitor_sp,r14");; /* restore the stack pointer */
309: 297 0000C425 0d effffffdb9 5e movl _monitor_sp,r14
310: 298 0000C42C # if( FALSE ) {
311: 299 0000C42C 11 06 jbr L319
312: 300 0000C42E # asm(".align 2");
313: 301 0000C42E 0000 .align 2
314: 302 0000C430 # asm(".globl return"); /* event return is through here */
315: 303 0000C430 .globl return
316: 304 0000C430 # asm("return:");
317: 305 0000C430 return:
318: 306 0000C430 # asm(".long _sched_return");;
319: 307 0000C430 00000239 .long _sched_return
320: 308 0000C434 # }
321: 309 0000C434 # }
322: 310 0000C434 L319:
323: 311 0000C434 40 ret#2
324: 312 0000C435 .set L315,0x0
325: 313 0000C435 L317:
326: 314 0000C435 11 bb jbr L318
327: 315 0000C437 .data
328: 316 00000254 * #
329: 316 00000254 * #
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