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Up to [Power 6/32 Unix Tahoe 4.2BSD] / cci / d / macro4|
Return to monitor.lst CVS log | Up to [Power 6/32 Unix Tahoe 4.2BSD] / cci / d / macro4 |
Power 6/32 Unix version 1.21
1 00000000 LL0:
2 00000000 .data
3 00000254 * .text
4 00000000 .align 1
5 00000000 .globl _monitor
6 00000000 _monitor:
7 0000C1E4 0000 .word L277
8 0000C1E6 #
9 0000C1E6 # #include "macro4_defs.h"
10 0000C1E6 #
11 0000C1E6 # /*********************************************************************
12 0000C1E6 # *
13 0000C1E6 # * MONITOR FOR THE FPP INSTRUCTION TESTS
14 0000C1E6 # *
15 0000C1E6 # * 20-Jul-85 : written
16 0000C1E6 # *********************************************************************/
17 0000C1E6 # monitor()
18 0000C1E6 # {
19 0000C1E6 13 01fe jbr L279
20 0000C1E9 L280:
21 0000C1E9 # int no_subtests; /* number of tests in the table */
22 0000C1E9 # force_loop = FALSE; /* clear the 'force loop' flag */
23 0000C1E9 4d effffffff5 clrl _force_loop
24 0000C1EF # cycle = 0; /* clear the cycle count */
25 0000C1EF 4d efffffffef clrl _cycle
26 0000C1F5 # errcnt = 0; /* clear the error count */
27 0000C1F5 4d efffffffe9 clrl _errcnt
28 0000C1FB # error = FALSE; /* clear the current error flag */
29 0000C1FB 4d efffffffe3 clrl _error
30 0000C201 # if( no_fpp_wcs ) {
31 0000C201 5d efffffffdd tstl _no_fpp_wcs
32 0000C207 31 15 jeql L281
33 0000C209 # test_tbl = no_fpp_test_tbl; /* use the NO-FPP tests */
34 0000C209 0d 8f00000000 efffffffd0 movl $_no_fpp_test_tbl,_test_tbl
35 0000C214 # no_subtests = no_fpp_test_cnt;
36 0000C214 0d efffffffca adc8 movl _no_fpp_test_cnt,-56(fp)
37 0000C21C # } else {
38 0000C21C 11 13 jbr L282
39 0000C21E L281:
40 0000C21E # test_tbl = fpp_test_tbl; /* use the FPP tests */
41 0000C21E 0d 8f00000000 efffffffbb movl $_fpp_test_tbl,_test_tbl
42 0000C229 # no_subtests = fpp_test_cnt;
43 0000C229 0d efffffffb5 adc8 movl _fpp_test_cnt,-56(fp)
44 0000C231 # }
45 0000C231 L282:
46 0000C231 # /*
47 0000C231 # * Print the Header information and enable the Data Cache if desired
48 0000C231 # */
49 0000C231 # if( prt_hdrs ) {
50 0000C231 5d efffffffad tstl _prt_hdrs
51 0000C237 31 31 jeql L283
52 0000C239 # writes("\nMacro4 Test");
53 0000C239 .data 1
54 00000254 * L285:
55 00000254 * 0A4D6163726F3420546573740 .ascii "\12Macro4 Test\0"
0
56 00000261 * .text
57 0000C239 dd 8f00000254 pushl $L285
58 0000C23F fe 08 efffffff9e callf $8,_writes
59 0000C246 # if( no_fpp_wcs )
60 0000C246 5d efffffff98 tstl _no_fpp_wcs
61 0000C24C 31 0f jeql L286
62 0000C24E # writes(" - FPP is NOT installed");
63 0000C24E .data 1
64 00000261 * L287:
65 00000261 * 202D20465050206973204E4F5 .ascii " - FPP is NOT installed\0"
420696E7374616C6C656400
66 00000279 * .text
67 0000C24E dd 8f00000261 pushl $L287
68 0000C254 fe 08 efffffff89 callf $8,_writes
69 0000C25B # else
70 0000C25B 11 0d jbr L288
71 0000C25D L286:
72 0000C25D # writes(" - FPP is installed");
73 0000C25D .data 1
74 00000279 * L289:
75 00000279 * 202D2046505020697320696E7 .ascii " - FPP is installed\0"
374616C6C656400
76 0000028d * .text
77 0000C25D dd 8f00000279 pushl $L289
78 0000C263 fe 08 efffffff7a callf $8,_writes
79 0000C26A L288:
80 0000C26A # }
81 0000C26A # if( en_data_cache ) {
82 0000C26A L283:
83 0000C26A 5d efffffff74 tstl _en_data_cache
84 0000C270 31 1d jeql L290
85 0000C272 # if( prt_hdrs )
86 0000C272 5d efffffff6c tstl _prt_hdrs
87 0000C278 31 0d jeql L291
88 0000C27A # writes(" - Data Cache Enabled: \n");
89 0000C27A .data 1
90 0000028d * L292:
91 0000028d * 20202D2044617461204361636 .ascii " - Data Cache Enabled: \12\0"
86520456E61626C65643A200A
00
92 000002a7 * .text
93 0000C27A dd 8f0000028d pushl $L292
94 0000C280 fe 08 efffffff5d callf $8,_writes
95 0000C287 # asm("mtpr $1,$25"); /* purge all data cache pages */
96 0000C287 L291:
97 0000C287 ad 01 19 mtpr $1,$25
98 0000C28A # asm("mtpr $1,$27"); /* enable the data cache */
99 0000C28A ad 01 1b mtpr $1,$27
100 0000C28D # } else {
101 0000C28D 11 18 jbr L293
102 0000C28F L290:
103 0000C28F # if( prt_hdrs )
104 0000C28F 5d efffffff4f tstl _prt_hdrs
105 0000C295 31 0d jeql L294
106 0000C297 # writes(" - Data Cache Disabled: \n");
107 0000C297 .data 1
108 000002a7 * L295:
109 000002a7 * 20202D2044617461204361636 .ascii " - Data Cache Disabled: \12\0"
8652044697361626C65643A20
0A00
110 000002c2 * .text
111 0000C297 dd 8f000002a7 pushl $L295
112 0000C29D fe 08 efffffff40 callf $8,_writes
113 0000C2A4 # asm("mtpr $2,$27"); /* disable the data cache */
114 0000C2A4 L294:
115 0000C2A4 ad 02 1b mtpr $2,$27
116 0000C2A7 # }
117 0000C2A7 L293:
118 0000C2A7 # /*
119 0000C2A7 # * Check the run list to see if a specific test is called for
120 0000C2A7 # */
121 0000C2A7 # for( cycle = 1; ( (cycle <= count) || nonstop ); cycle++ ) {
122 0000C2A7 0d 01 efffffff36 movl $1,_cycle
123 0000C2AE L298:
124 0000C2AE 1d efffffff30 efffffff2b cmpl _cycle,_count
125 0000C2B9 51 0b jleq L9999
126 0000C2BB 5d efffffff23 tstl _nonstop
127 0000C2C1 21 03 13 0092 jeql L297
128 0000C2C6 L9999:
129 0000C2C6 # if( (prt_hdrs) && (cycle != 1) ) /* show we're still running */
130 0000C2C6 5d efffffff18 tstl _prt_hdrs
131 0000C2CC 31 12 jeql L299
132 0000C2CE 1d efffffff10 01 cmpl _cycle,$1
133 0000C2D5 31 09 jeql L299
134 0000C2D7 # writec('.');
135 0000C2D7 dd 2e pushl $46
136 0000C2D9 fe 08 efffffff04 callf $8,_writec
137 0000C2E0 # if( (run_list > 0) && /* run 1 test only */
138 0000C2E0 L299:
139 0000C2E0 # (run_list <= no_subtests) ) {
140 0000C2E0 5d effffffefe tstl _run_list
141 0000C2E6 51 33 jleq L301
142 0000C2E8 1d effffffef6 adc8 cmpl _run_list,-56(fp)
143 0000C2F0 41 29 jgtr L301
144 0000C2F2 # test_no = run_list;
145 0000C2F2 0d effffffeec effffffee7 movl _run_list,_test_no
146 0000C2FD # test_index = run_list - 1;
147 0000C2FD 3c 01 effffffee0 50 subl3 $1,_run_list,r0
148 0000C305 0d 50 effffffed8 movl r0,_test_index
149 0000C30C # sched_test( test_index ); /* run the test */
150 0000C30C dd effffffed2 pushl _test_index
151 0000C312 fe 08 ef000000d5 callf $8,_sched_test
152 0000C319 # } else { /* run all tests */
153 0000C319 11 34 jbr L303
154 0000C31B L301:
155 0000C31B # for(test_index=0; test_index<no_subtests; test_index++) {
156 0000C31B 4d effffffec3 clrl _test_index
157 0000C321 L306:
158 0000C321 1d effffffebd adc8 cmpl _test_index,-56(fp)
159 0000C329 81 24 jgeq L305
160 0000C32B # test_no = test_index + 1;
161 0000C32B 1c 01 effffffeb2 50 addl3 $1,_test_index,r0
162 0000C333 0d 50 effffffeaa movl r0,_test_no
163 0000C33A # sched_test( test_index ); /* run the test */
164 0000C33A dd effffffea4 pushl _test_index
165 0000C340 fe 08 ef000000a7 callf $8,_sched_test
166 0000C347 # }
167 0000C347 L304:
168 0000C347 6d effffffe97 incl _test_index
169 0000C34D 11 d2 jbr L306
170 0000C34F L305:
171 0000C34F # } /* end of test-all-instructions */
172 0000C34F L303:
173 0000C34F # } /* end of test cycles - done with the test */
174 0000C34F L296:
175 0000C34F 6d effffffe8f incl _cycle
176 0000C355 13 ff56 jbr L298
177 0000C358 L297:
178 0000C358 # cycle--; /* correct cycle count */
179 0000C358 7d effffffe86 decl _cycle
180 0000C35E # if( prt_hdrs ) {
181 0000C35E 5d effffffe80 tstl _prt_hdrs
182 0000C364 31 61 jeql L307
183 0000C366 # /* if( !error ) */
184 0000C366 # writec('\n'); /* new line if no current errors */
185 0000C366 dd 0a pushl $10
186 0000C368 fe 08 effffffe75 callf $8,_writec
187 0000C36F # writes("Cycles Complete = ");
188 0000C36F .data 1
189 000002c2 * L308:
190 000002c2 * 4379636C657320436F6D706C6 .ascii "Cycles Complete = \0"
57465203D2000
191 000002d5 * .text
192 0000C36F dd 8f000002c2 pushl $L308
193 0000C375 fe 08 effffffe68 callf $8,_writes
194 0000C37C # writed( cycle );
195 0000C37C dd effffffe62 pushl _cycle
196 0000C382 fe 08 effffffe5b callf $8,_writed
197 0000C389 # if( errcnt ) {
198 0000C389 5d effffffe55 tstl _errcnt
199 0000C38F 31 29 jeql L310
200 0000C391 # writes(", Error Count = " );
201 0000C391 .data 1
202 000002d5 * L311:
203 000002d5 * 2C20204572726F7220436F756 .ascii ", Error Count = \0"
E74203D2000
204 000002e7 * .text
205 0000C391 dd 8f000002d5 pushl $L311
206 0000C397 fe 08 effffffe46 callf $8,_writes
207 0000C39E # writed( errcnt );
208 0000C39E dd effffffe40 pushl _errcnt
209 0000C3A4 fe 08 effffffe39 callf $8,_writed
210 0000C3AB # writes(", Test Complete\n");
211 0000C3AB .data 1
212 000002e7 * L312:
213 000002e7 * 2C20205465737420436F6D706 .ascii ", Test Complete\12\0"
C6574650A00
214 000002f9 * .text
215 0000C3AB dd 8f000002e7 pushl $L312
216 0000C3B1 fe 08 effffffe2c callf $8,_writes
217 0000C3B8 # } else
218 0000C3B8 11 0d jbr L313
219 0000C3BA L310:
220 0000C3BA # writes(", TEST PASSED -NO ERRORS!!! \n");
221 0000C3BA .data 1
222 000002f9 * L314:
223 000002f9 * 2C20205445535420504153534 .ascii ", TEST PASSED -NO ERRORS!!! \12\0"
544202D4E4F204552524F5253
212121200A00
224 00000318 * .text
225 0000C3BA dd 8f000002f9 pushl $L314
226 0000C3C0 fe 08 effffffe1d callf $8,_writes
227 0000C3C7 L313:
228 0000C3C7 # };
229 0000C3C7 L307:
230 0000C3C7 # /*
231 0000C3C7 # * Set up the registers to halt
232 0000C3C7 # */
233 0000C3C7 # asm("movl _errcnt,r0"); /* set error count for halt */
234 0000C3C7 0d effffffe17 50 movl _errcnt,r0
235 0000C3CE # asm("bneq 1f");
236 0000C3CE 21 07 bneq 1f
237 0000C3D0 # asm("movl $0xCAFEBABE,r0");; /* set the no-error flag */
238 0000C3D0 0d 8fcafebabe 50 movl $0xCAFEBABE,r0
239 0000C3D7 # asm("1:");
240 0000C3D7 1:
241 0000C3D7 # asm("movl _OPTIONS,r1"); /* restore options to r1 */
242 0000C3D7 0d effffffe07 51 movl _OPTIONS,r1
243 0000C3DE # asm("movl _cycle,r2"); /* move cycle count to r2 */
244 0000C3DE 0d effffffe00 52 movl _cycle,r2
245 0000C3E5 # asm("halt");;
246 0000C3E5 00 halt
247 0000C3E6 # }
248 0000C3E6 40 ret#2
249 0000C3E7 .set L277,0x0
250 0000C3E7 L279:
251 0000C3E7 3c 38 5d 5e subl3 $56,fp,sp
252 0000C3EB 13 fdfb jbr L280
253 0000C3EE .data
254 00000254 * .text
255 0000C3EE .align 1
256 0000C3EE .globl _sched_test
257 0000C3EE _sched_test:
258 0000C3EE 0000 .word L315
259 0000C3F0 #
260 0000C3F0 #
261 0000C3F0 #
262 0000C3F0 # /***********************************************************************
263 0000C3F0 # *
264 0000C3F0 # * Start the current subtest
265 0000C3F0 # *
266 0000C3F0 # * The test may come back here after an unexpected event so the monitor's
267 0000C3F0 # * stack and frame pointers are saved. Funny things happen if we try to
268 0000C3F0 # * exit from this routine with the wrong frame pointer. Unexpected events
269 0000C3F0 # * will either return indirectly through "return" or they will just halt.
270 0000C3F0 # *
271 0000C3F0 # ***********************************************************************/
272 0000C3F0 # sched_test( test_index )
273 0000C3F0 # int test_index;
274 0000C3F0 # {
275 0000C3F0 11 43 jbr L317
276 0000C3F2 L318:
277 0000C3F2 # asm("moval (r13),_monitor_fp"); /* save the frame ptr */
278 0000C3F2 ed 6d effffffdeb moval (r13),_monitor_fp
279 0000C3F9 # asm("moval (r14),_monitor_sp"); /* save the stack ptr */
280 0000C3F9 ed 6e effffffde4 moval (r14),_monitor_sp
281 0000C400 # test_ptr = test_tbl[ test_index ]; /* get ptr to test */
282 0000C400 0d ad04 50 movl 4(fp),r0
283 0000C404 48 02 50 50 shll $2,r0,r0
284 0000C408 1c 50 effffffdd5 50 addl3 r0,_test_tbl,r0
285 0000C410 0d 60 effffffdcd movl (r0),_test_ptr
286 0000C417 # asm("jmp *_test_ptr"); /* execute the test */
287 0000C417 71 fffffffdc7 jmp *_test_ptr
288 0000C41D # asm(".globl _sched_return");
289 0000C41D .globl _sched_return
290 0000C41D # asm("_sched_return:"); /* return here after the test */
291 0000C41D _sched_return:
292 0000C41D # asm("nop");
293 0000C41D 10 nop
294 0000C41E # asm("movl _monitor_fp,r13"); /* restore the frame pointer */
295 0000C41E 0d effffffdc0 5d movl _monitor_fp,r13
296 0000C425 # asm("movl _monitor_sp,r14");; /* restore the stack pointer */
297 0000C425 0d effffffdb9 5e movl _monitor_sp,r14
298 0000C42C # if( FALSE ) {
299 0000C42C 11 06 jbr L319
300 0000C42E # asm(".align 2");
301 0000C42E 0000 .align 2
302 0000C430 # asm(".globl return"); /* event return is through here */
303 0000C430 .globl return
304 0000C430 # asm("return:");
305 0000C430 return:
306 0000C430 # asm(".long _sched_return");;
307 0000C430 00000239 .long _sched_return
308 0000C434 # }
309 0000C434 # }
310 0000C434 L319:
311 0000C434 40 ret#2
312 0000C435 .set L315,0x0
313 0000C435 L317:
314 0000C435 11 bb jbr L318
315 0000C437 .data
316 00000254 * #
316 00000254 * #
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