![[BACK]](/cvsweb/icons/back.gif){kind=icon}
Return to negd.c CVS log ![[TXT]](/cvsweb/icons/text.gif){kind=icon}
![[DIR]](/cvsweb/icons/dir.gif){kind=icon}
Up to [Power 6/32 Unix Tahoe 4.2BSD] / cci / d / macro4|
Return to negd.c CVS log | Up to [Power 6/32 Unix Tahoe 4.2BSD] / cci / d / macro4 |
1.1 root 1:
2: #include "fpp_defs.h"
3:
4:
5: /*****************************************************************************
6: *
7: * NEGD - DOUBLE PRECISION FLOATING POINT LOAD_NEGATE TEST
8: *
9: *****************************************************************************/
10: negd()
11: {
12: asm(".globl _negd_t");
13: asm("_negd_t:"); /* entry address */
14: if( ( cycle ==1 ) && ( prt_hdrs ) ) /* print headers on 1st pass */
15: writes(" NEGD");
16: negd_1(); /* negate through the cache */
17: negd_2(); /* register stability */
18: negd_3(); /* PSL stability test */
19: asm("jmp *return"); /* return to the test monitor */
20: }
21:
22:
23:
24: /************************************************************************
25: *
26: * SUBTEST 1 - negate through memory
27: *
28: ************************************************************************/
29: negd_1()
30: {
31: force_loop = FALSE;
32: subtest = 1;
33: for( index = 0; index < max_lnd_1_index; index++ ) {
34: dbl_ld_acc = lnd_1_data[index].ld; /* get value to negate */
35: dbl_expected = lnd_1_data[index].exp; /* expected result */
36: /*
37: * If LOOP ON ERROR is set, this is the loop for this subtest.
38: * The force loop flag is set after the first error.
39: */
40: asm("_negd_1_lp1:");
41: asm("ldd _dbl_ld_acc"); /* load the value */
42: asm("negd"); /* negate the value */
43: asm("std _dbl_st_acc"); /* store the result */
44: if( force_loop )
45: asm("brb _negd_1_lp1");; /* loop on the error */
46: /*
47: * end error loop - test the results
48: */
49: if( (dbl_st_acc.m != dbl_expected.m ) || /* COMPARE the values*/
50: (dbl_st_acc.l != dbl_expected.l ) ) {
51: errcnt++; /* bump the error count */
52: if( prt_error ) {
53: writes(" \n"); /* start a new print line */
54: writes("cycle: ");
55: writed( cycle );
56: writes(" NEGD test ");
57: writed( test_no );
58: writes(", subtest 1 (Cache Data) - BAD FINAL ACC\n");
59: print_negd_data();
60: writes(", index = ");
61: writed( index );
62: writec('\n');
63: writes(" Acc expected = ");
64: write32h( dbl_expected.m );
65: writec(' ');
66: write32h( dbl_expected.l );
67: writec('\n');
68: }
69: if( halt_flg )
70: negd_er_halt( BAD_ACC_HLT ); /* halt on the error */
71: if( loop_on_err ) {
72: force_loop = TRUE; /* set the force loop flag */
73: asm("brw _negd_1_lp1");; /* and loop on the error */
74: } /* end of loop on error */
75: } /* end of compare error */
76: } /* end of WHILE loop */
77: } /* end of subtest 1 */
78:
79:
80:
81: /************************************************************************
82: *
83: * SUBTEST 2 - Check for register corruption
84: *
85: ************************************************************************/
86: negd_2()
87: {
88: force_loop = FALSE; /* clear force_loop flg */
89: subtest = 2;
90: fill_reg_buf( load_regs ); /* get patterns for regs */
91: index = 0;
92: dbl_ld_acc = lnd_1_data[0].ld; /* get value to negate */
93: /* if( no_fpp_wcs ) /* */
94: /* dbl_expected = dbl_ld_acc; /* expected = loaded */
95: /* else /* */
96: /* dbl_expected = lnd_1_data[index].exp; /* expected result */
97: /*
98: * If LOOP ON ERROR is set, this is the loop for this subtest.
99: * The force loop flag is set after the first error.
100: */
101: asm("ldd _dbl_ld_acc"); /* load the initial value */
102: asm("_negd_2_lp1:");
103: asm("loadr $0x1fff,_load_regs"); /* load regs 0 - 12 */
104: asm("nop");
105: asm("negd"); /* negate the value */
106: asm("nop");
107: asm("storer $0x1fff,_store_regs"); /* store regs 0 - 12 */
108: asm("std _dbl_st_acc"); /* save the accumulator */
109: if( force_loop )
110: asm("brb _negd_2_lp1");; /* loop on the error */
111: /*
112: * Now compare the stored register values to those that were loaded
113: */
114: index2 = 0;
115: while( (load_regs[index2] == store_regs[index2]) && (index2 < 13) )
116: index2++; /* check reg values */
117: if( index2 < 13 ) { /* error if index2 < 13 */
118: errcnt++; /* bump the error count */
119: if( prt_error ) {
120: writes(" \n"); /* start a new print line */
121: writes("cycle: ");
122: writed( cycle );
123: writes(" NEGD test ");
124: writed( test_no );
125: writes(", subtest 2 - A REGISTER WAS MODIFIED\n");
126: print_negd_data(); /* print the operands */
127: writes("\n");
128: writes("register "); /* print the information */
129: writed( index2 ); /* about the corrupted */
130: writes(" = "); /* register */
131: write32h( store_regs[index2] );
132: writes(", should be = ");
133: write32h( load_regs[index2] );
134: writes("\n");
135: }
136: if( halt_flg )
137: negd_er_halt( BAD_REG_HLT ); /* halt on the error */
138: if( loop_on_err ) {
139: force_loop = TRUE; /* set the force loop flag */
140: asm("brw _negd_2_lp1");; /* and loop on the error */
141: } /* end of loop on error */
142: } /* end of register corruption error */
143: } /* end of subtest 2 */
144:
145:
146:
147: /************************************************************************
148: *
149: * SUBTEST 3 - Check for PSL corruption
150: *
151: ************************************************************************/
152: negd_3()
153: {
154: force_loop = FALSE; /* clear force_loop flg */
155: subtest = 3;
156: fill_reg_buf( load_regs ); /* get patterns for regs */
157: for( index = 0; index < 3; index++ ) {
158: dbl_ld_acc = lnd_1_data[index].ld; /* get value to negate */
159: /* if( no_fpp_wcs ) /* */
160: /* dbl_expected = dbl_ld_acc; /* expected = loaded */
161: /* else /* */
162: /* dbl_expected = lnd_1_data[index].exp; /* expected result */
163: sgl_dummy1 = status_array[status_index]; /* status = +, -, 0 */
164: /*
165: * If LOOP ON ERROR is set, this is the loop for this subtest.
166: * The force loop flag is set after the first error.
167: */
168: asm("_negd_3_lp1:");
169: asm("ldd _dbl_ld_acc"); /* load the initial value */
170: asm("tstl _sgl_dummy1"); /* set the PSL status */
171: asm("movpsl _init_psl"); /* save the initial PSL */
172: asm("negd"); /* negate the value */
173: asm("nop");
174: asm("movpsl _psl_val"); /* save the final PSL */
175: asm("std _dbl_st_acc"); /* save the accumulator */
176: if( force_loop )
177: asm("brb _negd_3_lp1");; /* loop on the error */
178: /*
179: * Now compare the final PSL to the initial PSL -they should be the same
180: */
181: exp_psl = init_psl;
182: if( psl_val != exp_psl ) {
183: errcnt++; /* bump the error count */
184: if( prt_error ) {
185: writes(" \n"); /* start a new print line */
186: writes("cycle: ");
187: writed( cycle );
188: writes(" NEGD test ");
189: writed( test_no );
190: writes(", subtest 3 - INCORRECT FINAL PSL\n");
191: print_negd_data(); /* print the operands */
192: writes("\n");
193: writes("initial PSL = ");
194: write32h( init_psl );
195: writes(", final PSL = ");
196: write32h( psl_val );
197: writes(", expected PSL = ");
198: write32h( exp_psl );
199: writes("\n");
200: }
201: if( halt_flg )
202: negd_er_halt( BAD_PSL_HLT ); /* halt on the error */
203: if( loop_on_err ) {
204: force_loop = TRUE; /* set the force loop flag */
205: asm("brw _negd_3_lp1");; /* and loop on the error */
206: } /* end of loop on error */
207: } /* end of PSL corruption error */
208: } /* end of WHILE loop */
209: } /* end of subtest 3 */
210:
211:
212:
213: /**************************************************************************
214: *
215: * PRINT THE DATA AND STORE RESULTS
216: *
217: * initial Acc = xxxxxxxx xxxxxxxx, final Acc = xxxxxxxx xxxxxxxx, index = xx
218: * expected = xxxxxxxx xxxxxxxx
219: **************************************************************************/
220: print_negd_data()
221: {
222: writes("initial Acc = ");
223: write32h( dbl_ld_acc.m );
224: writec(' ');
225: write32h( dbl_ld_acc.l );
226: writes(", final Acc = ");
227: write32h( dbl_st_acc.m );
228: writec(' ');
229: write32h( dbl_st_acc.l );
230: }
231:
232:
233:
234: /**************************************************************************
235: *
236: * HALT ON ERROR ROUTINE
237: *
238: **************************************************************************/
239: negd_er_halt( halt_code )
240: int halt_code;
241: {
242: sgl_value_1 = dbl_ld_acc.m;
243: sgl_value_2 = dbl_ld_acc.l;
244: sgl_value_3 = dbl_st_acc.m;
245: sgl_value_4 = dbl_st_acc.l;
246: sgl_dummy1 = halt_code; /* get the error type */
247: asm("movl _test_no,r0"); /* r0 = test number */
248: asm("movl _subtest,r1"); /* r1 = subtest number */
249: asm("movl _sgl_dummy1,r2"); /* r2 = error code */
250: asm("movl _cycle,r3"); /* r3 = cycle count */
251: asm("movl _sgl_value_1,r4"); /* r4 = MS operand 1 */
252: asm("movl _sgl_value_2,r5"); /* r5 = LS operand 1 */
253: asm("movl _sgl_value_3,r6"); /* r6 = MS stored */
254: asm("movl _sgl_value_4,r7"); /* r7 = LS stored */
255: if( halt_code == BAD_ACC_HLT ) {
256: sgl_value_1 = dbl_expected.m;
257: sgl_value_2 = dbl_expected.l;
258: asm("movl _sgl_value_1,r8"); /* r8 = MS expected */
259: asm("movl _sgl_value_2,r9"); /* r9 = LS expected */
260: asm("movl _index,r10"); /* r10 = data index */
261: } else
262: if( halt_code == BAD_REG_HLT ) {
263: sgl_dummy1 = load_regs[index2];
264: sgl_dummy2 = store_regs[index2];
265: asm("movl _index2,r8"); /* r8 = bad register # */
266: asm("movl _sgl_dummy2,r9"); /* r9 = actual value */
267: asm("movl _sgl_dummy1,r10"); /* r10 = expected value */
268: } else
269: if( halt_code == BAD_PSL_HLT ) {
270: asm("movl _init_psl,r8"); /* r8 = initial PSL */
271: asm("movl _psl_val,r9"); /* r9 = final PSL */
272: asm("movl _exp_psl,r10"); /* r10 = expected PSL */
273: };
274: asm("halt"); /* HALT ... */
275: }
This archive runs on limited infrastructure. Preserving old code on modern bandwidth. Automated agents are requested to crawl responsibly.