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Up to [Power 6/32 Unix Tahoe 4.2BSD] / cci / d / macro4|
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1.1 root 1: 1 00000000 LL0:
2: 2 00000000 .data
3: 3 0000068c * .text
4: 4 00000000 .align 1
5: 5 00000000 .globl _negd
6: 6 00000000 _negd:
7: 7 0001A5AC 0000 .word L215
8: 8 0001A5AE #
9: 9 0001A5AE # #include "fpp_defs.h"
10: 10 0001A5AE #
11: 11 0001A5AE #
12: 12 0001A5AE # /*****************************************************************************
13: 13 0001A5AE # *
14: 14 0001A5AE # * NEGD - DOUBLE PRECISION FLOATING POINT LOAD_NEGATE TEST
15: 15 0001A5AE # *
16: 16 0001A5AE # *****************************************************************************/
17: 17 0001A5AE # negd()
18: 18 0001A5AE # {
19: 19 0001A5AE 11 3a jbr L217
20: 20 0001A5B0 L218:
21: 21 0001A5B0 # asm(".globl _negd_t");
22: 22 0001A5B0 .globl _negd_t
23: 23 0001A5B0 # asm("_negd_t:"); /* entry address */
24: 24 0001A5B0 _negd_t:
25: 25 0001A5B0 # if( ( cycle ==1 ) && ( prt_hdrs ) ) /* print headers on 1st pass */
26: 26 0001A5B0 1d effffffff6 01 cmpl _cycle,$1
27: 27 0001A5B7 21 15 jneq L219
28: 28 0001A5B9 5d efffffffed tstl _prt_hdrs
29: 29 0001A5BF 31 0d jeql L219
30: 30 0001A5C1 # writes(" NEGD");
31: 31 0001A5C1 .data 1
32: 32 0000068c * L221:
33: 33 0000068c * 204E45474400 .ascii " NEGD\0"
34: 34 00000692 * .text
35: 35 0001A5C1 dd 8f0000068c pushl $L221
36: 36 0001A5C7 fe 08 efffffffde callf $8,_writes
37: 37 0001A5CE # negd_1(); /* negate through the cache */
38: 38 0001A5CE L219:
39: 39 0001A5CE fe 04 ef00000017 callf $4,_negd_1
40: 40 0001A5D5 # negd_2(); /* register stability */
41: 41 0001A5D5 fe 04 ef0000019a callf $4,_negd_2
42: 42 0001A5DC # negd_3(); /* PSL stability test */
43: 43 0001A5DC fe 04 ef0000033f callf $4,_negd_3
44: 44 0001A5E3 # asm("jmp *return"); /* return to the test monitor */
45: 45 0001A5E3 71 ffffffffc3 jmp *return
46: 46 0001A5E9 # }
47: 47 0001A5E9 40 ret#2
48: 48 0001A5EA .set L215,0x0
49: 49 0001A5EA L217:
50: 50 0001A5EA 11 c4 jbr L218
51: 51 0001A5EC .data
52: 52 0000068c * .text
53: 53 0001A5EC .align 1
54: 54 0001A5EC .globl _negd_1
55: 55 0001A5EC _negd_1:
56: 56 0001A5EC 0000 .word L225
57: 57 0001A5EE #
58: 58 0001A5EE #
59: 59 0001A5EE #
60: 60 0001A5EE # /************************************************************************
61: 61 0001A5EE # *
62: 62 0001A5EE # * SUBTEST 1 - negate through memory
63: 63 0001A5EE # *
64: 64 0001A5EE # ************************************************************************/
65: 65 0001A5EE # negd_1()
66: 66 0001A5EE # {
67: 67 0001A5EE 13 0182 jbr L227
68: 68 0001A5F1 L228:
69: 69 0001A5F1 # force_loop = FALSE;
70: 70 0001A5F1 4d efffffffb5 clrl _force_loop
71: 71 0001A5F7 # subtest = 1;
72: 72 0001A5F7 0d 01 efffffffae movl $1,_subtest
73: 73 0001A5FE # for( index = 0; index < max_lnd_1_index; index++ ) {
74: 74 0001A5FE 4d efffffffa8 clrl _index
75: 75 0001A604 L231:
76: 76 0001A604 1d efffffffa2 efffffff9d cmpl _index,_max_lnd_1_index
77: 77 0001A60F 91 03 13 015e jgeq L230
78: 78 0001A614 # dbl_ld_acc = lnd_1_data[index].ld; /* get value to negate */
79: 79 0001A614 48 04 efffffff91 50 shll $4,_index,r0
80: 80 0001A61C 0c 8f00000000 50 addl2 $_lnd_1_data,r0
81: 81 0001A623 0d a004 efffffff85 movl 4(r0),_dbl_ld_acc+4
82: 82 0001A62B 0d 60 efffffff7a movl (r0),_dbl_ld_acc
83: 83 0001A632 # dbl_expected = lnd_1_data[index].exp; /* expected result */
84: 84 0001A632 48 04 efffffff73 50 shll $4,_index,r0
85: 85 0001A63A 0c 8f00000008 50 addl2 $_lnd_1_data+8,r0
86: 86 0001A641 0d a004 efffffff67 movl 4(r0),_dbl_expected+4
87: 87 0001A649 0d 60 efffffff5c movl (r0),_dbl_expected
88: 88 0001A650 # /*
89: 89 0001A650 # * If LOOP ON ERROR is set, this is the loop for this subtest.
90: 90 0001A650 # * The force loop flag is set after the first error.
91: 91 0001A650 # */
92: 92 0001A650 # asm("_negd_1_lp1:");
93: 93 0001A650 _negd_1_lp1:
94: 94 0001A650 # asm("ldd _dbl_ld_acc"); /* load the value */
95: 95 0001A650 07 efffffff56 ldd _dbl_ld_acc
96: 96 0001A656 # asm("negd"); /* negate the value */
97: 97 0001A656 b7 negd
98: 98 0001A657 # asm("std _dbl_st_acc"); /* store the result */
99: 99 0001A657 27 efffffff4f std _dbl_st_acc
100: 100 0001A65D # if( force_loop )
101: 101 0001A65D 5d efffffff49 tstl _force_loop
102: 102 0001A663 31 02 jeql L232
103: 103 0001A665 # asm("brb _negd_1_lp1");; /* loop on the error */
104: 104 0001A665 11 e9 brb _negd_1_lp1
105: 105 0001A667 L232:
106: 106 0001A667 # /*
107: 107 0001A667 # * end error loop - test the results
108: 108 0001A667 # */
109: 109 0001A667 # if( (dbl_st_acc.m != dbl_expected.m ) || /* COMPARE the values*/
110: 110 0001A667 # (dbl_st_acc.l != dbl_expected.l ) ) {
111: 111 0001A667 1d efffffff3f efffffff3a cmpl _dbl_st_acc,_dbl_expected
112: 112 0001A672 21 10 jneq L9999
113: 113 0001A674 1d efffffff36 efffffff31 cmpl _dbl_st_acc+4,_dbl_expected+4
114: 114 0001A67F 21 03 13 00e5 jeql L233
115: 115 0001A684 L9999:
116: 116 0001A684 # errcnt++; /* bump the error count */
117: 117 0001A684 6d efffffff22 incl _errcnt
118: 118 0001A68A # if( prt_error ) {
119: 119 0001A68A 5d efffffff1c tstl _prt_error
120: 120 0001A690 21 03 13 00b1 jeql L234
121: 121 0001A695 # writes(" \n"); /* start a new print line */
122: 122 0001A695 .data 1
123: 123 00000692 * L235:
124: 124 00000692 * 200A00 .ascii " \12\0"
125: 125 00000695 * .text
126: 126 0001A695 dd 8f00000692 pushl $L235
127: 127 0001A69B fe 08 efffffff0a callf $8,_writes
128: 128 0001A6A2 # writes("cycle: ");
129: 129 0001A6A2 .data 1
130: 130 00000695 * L236:
131: 131 00000695 * 6379636C653A2000 .ascii "cycle: \0"
132: 132 0000069d * .text
133: 133 0001A6A2 dd 8f00000695 pushl $L236
134: 134 0001A6A8 fe 08 effffffefd callf $8,_writes
135: 135 0001A6AF # writed( cycle );
136: 136 0001A6AF dd effffffef7 pushl _cycle
137: 137 0001A6B5 fe 08 effffffef0 callf $8,_writed
138: 138 0001A6BC # writes(" NEGD test ");
139: 139 0001A6BC .data 1
140: 140 0000069d * L238:
141: 141 0000069d * 20204E4547442074657374200 .ascii " NEGD test \0"
142: 0
143: 142 000006aa * .text
144: 143 0001A6BC dd 8f0000069d pushl $L238
145: 144 0001A6C2 fe 08 effffffee3 callf $8,_writes
146: 145 0001A6C9 # writed( test_no );
147: 146 0001A6C9 dd effffffedd pushl _test_no
148: 147 0001A6CF fe 08 effffffed6 callf $8,_writed
149: 148 0001A6D6 # writes(", subtest 1 (Cache Data) - BAD FINAL ACC\n");
150: 149 0001A6D6 .data 1
151: 150 000006aa * L239:
152: 151 000006aa * 2C20737562746573742031202 .ascii ", subtest 1 (Cache Data) - BAD FINAL ACC\12\0"
153: 8436163686520446174612920
154: 2D204241442046494E414C204
155: 143430A00
156: 152 000006d4 * .text
157: 153 0001A6D6 dd 8f000006aa pushl $L239
158: 154 0001A6DC fe 08 effffffec9 callf $8,_writes
159: 155 0001A6E3 # print_negd_data();
160: 156 0001A6E3 fe 04 ef000003de callf $4,_print_negd_data
161: 157 0001A6EA # writes(", index = ");
162: 158 0001A6EA .data 1
163: 159 000006d4 * L241:
164: 160 000006d4 * 2C2020696E646578203D2000 .ascii ", index = \0"
165: 161 000006e0 * .text
166: 162 0001A6EA dd 8f000006d4 pushl $L241
167: 163 0001A6F0 fe 08 effffffeb5 callf $8,_writes
168: 164 0001A6F7 # writed( index );
169: 165 0001A6F7 dd effffffeaf pushl _index
170: 166 0001A6FD fe 08 effffffea8 callf $8,_writed
171: 167 0001A704 # writec('\n');
172: 168 0001A704 dd 0a pushl $10
173: 169 0001A706 fe 08 effffffe9f callf $8,_writec
174: 170 0001A70D # writes(" Acc expected = ");
175: 171 0001A70D .data 1
176: 172 000006e0 * L243:
177: 173 000006e0 * 2020202020202020202020202 .ascii " Acc expected = \0"
178: 0202020202020202020202020
179: 2020202020204163632065787
180: 06563746564203D2000
181: 174 0000070f * .text
182: 175 0001A70D dd 8f000006e0 pushl $L243
183: 176 0001A713 fe 08 effffffe92 callf $8,_writes
184: 177 0001A71A # write32h( dbl_expected.m );
185: 178 0001A71A dd effffffe8c pushl _dbl_expected
186: 179 0001A720 fe 08 effffffe85 callf $8,_write32h
187: 180 0001A727 # writec(' ');
188: 181 0001A727 dd 20 pushl $32
189: 182 0001A729 fe 08 effffffe7c callf $8,_writec
190: 183 0001A730 # write32h( dbl_expected.l );
191: 184 0001A730 dd effffffe7a pushl _dbl_expected+4
192: 185 0001A736 fe 08 effffffe6f callf $8,_write32h
193: 186 0001A73D # writec('\n');
194: 187 0001A73D dd 0a pushl $10
195: 188 0001A73F fe 08 effffffe66 callf $8,_writec
196: 189 0001A746 # }
197: 190 0001A746 # if( halt_flg )
198: 191 0001A746 L234:
199: 192 0001A746 5d effffffe60 tstl _halt_flg
200: 193 0001A74C 31 09 jeql L245
201: 194 0001A74E # negd_er_halt( BAD_ACC_HLT ); /* halt on the error */
202: 195 0001A74E dd 01 pushl $1
203: 196 0001A750 fe 08 ef000003d9 callf $8,_negd_er_halt
204: 197 0001A757 # if( loop_on_err ) {
205: 198 0001A757 L245:
206: 199 0001A757 5d effffffe4f tstl _loop_on_err
207: 200 0001A75D 31 0a jeql L247
208: 201 0001A75F # force_loop = TRUE; /* set the force loop flag */
209: 202 0001A75F 0d 01 effffffe46 movl $1,_force_loop
210: 203 0001A766 # asm("brw _negd_1_lp1");; /* and loop on the error */
211: 204 0001A766 13 fee7 brw _negd_1_lp1
212: 205 0001A769 # } /* end of loop on error */
213: 206 0001A769 # } /* end of compare error */
214: 207 0001A769 L247:
215: 208 0001A769 # } /* end of WHILE loop */
216: 209 0001A769 L233:
217: 210 0001A769 L229:
218: 211 0001A769 6d effffffe3d incl _index
219: 212 0001A76F 13 fe92 jbr L231
220: 213 0001A772 L230:
221: 214 0001A772 # } /* end of subtest 1 */
222: 215 0001A772 40 ret#2
223: 216 0001A773 .set L225,0x0
224: 217 0001A773 L227:
225: 218 0001A773 13 fe7b jbr L228
226: 219 0001A776 .data
227: 220 0000068c * .text
228: 221 0001A776 .align 1
229: 222 0001A776 .globl _negd_2
230: 223 0001A776 _negd_2:
231: 224 0001A776 0000 .word L248
232: 225 0001A778 #
233: 226 0001A778 #
234: 227 0001A778 #
235: 228 0001A778 # /************************************************************************
236: 229 0001A778 # *
237: 230 0001A778 # * SUBTEST 2 - Check for register corruption
238: 231 0001A778 # *
239: 232 0001A778 # ************************************************************************/
240: 233 0001A778 # negd_2()
241: 234 0001A778 # {
242: 235 0001A778 13 01a3 jbr L250
243: 236 0001A77B L251:
244: 237 0001A77B # force_loop = FALSE; /* clear force_loop flg */
245: 238 0001A77B 4d effffffe2b clrl _force_loop
246: 239 0001A781 # subtest = 2;
247: 240 0001A781 0d 02 effffffe24 movl $2,_subtest
248: 241 0001A788 # fill_reg_buf( load_regs ); /* get patterns for regs */
249: 242 0001A788 dd 8f00000000 pushl $_load_regs
250: 243 0001A78E fe 08 effffffe17 callf $8,_fill_reg_buf
251: 244 0001A795 # index = 0;
252: 245 0001A795 4d effffffe11 clrl _index
253: 246 0001A79B # dbl_ld_acc = lnd_1_data[0].ld; /* get value to negate */
254: 247 0001A79B 0d effffffe0f effffffe0a movl _lnd_1_data+4,_dbl_ld_acc+4
255: 248 0001A7A6 0d effffffe00 effffffdfb movl _lnd_1_data,_dbl_ld_acc
256: 249 0001A7B1 # /* if( no_fpp_wcs ) /* */
257: 250 0001A7B1 # /* dbl_expected = dbl_ld_acc; /* expected = loaded */
258: 251 0001A7B1 # /* else /* */
259: 252 0001A7B1 # /* dbl_expected = lnd_1_data[index].exp; /* expected result */
260: 253 0001A7B1 # /*
261: 254 0001A7B1 # * If LOOP ON ERROR is set, this is the loop for this subtest.
262: 255 0001A7B1 # * The force loop flag is set after the first error.
263: 256 0001A7B1 # */
264: 257 0001A7B1 # asm("ldd _dbl_ld_acc"); /* load the initial value */
265: 258 0001A7B1 07 effffffdf5 ldd _dbl_ld_acc
266: 259 0001A7B7 # asm("_negd_2_lp1:");
267: 260 0001A7B7 _negd_2_lp1:
268: 261 0001A7B7 # asm("loadr $0x1fff,_load_regs"); /* load regs 0 - 12 */
269: 262 0001A7B7 ab 891fff effffffdec loadr $0x1fff,_load_regs
270: 263 0001A7C0 # asm("nop");
271: 264 0001A7C0 10 nop
272: 265 0001A7C1 # asm("negd"); /* negate the value */
273: 266 0001A7C1 b7 negd
274: 267 0001A7C2 # asm("nop");
275: 268 0001A7C2 10 nop
276: 269 0001A7C3 # asm("storer $0x1fff,_store_regs"); /* store regs 0 - 12 */
277: 270 0001A7C3 bb 891fff effffffde0 storer $0x1fff,_store_regs
278: 271 0001A7CC # asm("std _dbl_st_acc"); /* save the accumulator */
279: 272 0001A7CC 27 effffffdda std _dbl_st_acc
280: 273 0001A7D2 # if( force_loop )
281: 274 0001A7D2 5d effffffdd4 tstl _force_loop
282: 275 0001A7D8 31 02 jeql L253
283: 276 0001A7DA # asm("brb _negd_2_lp1");; /* loop on the error */
284: 277 0001A7DA 11 db brb _negd_2_lp1
285: 278 0001A7DC L253:
286: 279 0001A7DC # /*
287: 280 0001A7DC # * Now compare the stored register values to those that were loaded
288: 281 0001A7DC # */
289: 282 0001A7DC # index2 = 0;
290: 283 0001A7DC 4d effffffdca clrl _index2
291: 284 0001A7E2 # while( (load_regs[index2] == store_regs[index2]) && (index2 < 13) )
292: 285 0001A7E2 L254:
293: 286 0001A7E2 0d effffffdc4 50 movl _index2,r0
294: 287 0001A7E9 0d effffffdbd 51 movl _index2,r1
295: 288 0001A7F0 1d 40effffffdb5 cmpl _load_regs[r0],_store_regs[r1]
296: 41effffffdaf
297: 289 0001A7FD 21 11 jneq L255
298: 290 0001A7FF 1d effffffda7 0d cmpl _index2,$13
299: 291 0001A806 81 08 jgeq L255
300: 292 0001A808 # index2++; /* check reg values */
301: 293 0001A808 6d effffffd9e incl _index2
302: 294 0001A80E 11 d2 jbr L254
303: 295 0001A810 L255:
304: 296 0001A810 # if( index2 < 13 ) { /* error if index2 < 13 */
305: 297 0001A810 1d effffffd96 0d cmpl _index2,$13
306: 298 0001A817 91 03 13 0101 jgeq L256
307: 299 0001A81C # errcnt++; /* bump the error count */
308: 300 0001A81C 6d effffffd8a incl _errcnt
309: 301 0001A822 # if( prt_error ) {
310: 302 0001A822 5d effffffd84 tstl _prt_error
311: 303 0001A828 21 03 13 00cd jeql L257
312: 304 0001A82D # writes(" \n"); /* start a new print line */
313: 305 0001A82D .data 1
314: 306 0000070f * L258:
315: 307 0000070f * 200A00 .ascii " \12\0"
316: 308 00000712 * .text
317: 309 0001A82D dd 8f0000070f pushl $L258
318: 310 0001A833 fe 08 effffffd72 callf $8,_writes
319: 311 0001A83A # writes("cycle: ");
320: 312 0001A83A .data 1
321: 313 00000712 * L259:
322: 314 00000712 * 6379636C653A2000 .ascii "cycle: \0"
323: 315 0000071a * .text
324: 316 0001A83A dd 8f00000712 pushl $L259
325: 317 0001A840 fe 08 effffffd65 callf $8,_writes
326: 318 0001A847 # writed( cycle );
327: 319 0001A847 dd effffffd5f pushl _cycle
328: 320 0001A84D fe 08 effffffd58 callf $8,_writed
329: 321 0001A854 # writes(" NEGD test ");
330: 322 0001A854 .data 1
331: 323 0000071a * L260:
332: 324 0000071a * 20204E4547442074657374200 .ascii " NEGD test \0"
333: 0
334: 325 00000727 * .text
335: 326 0001A854 dd 8f0000071a pushl $L260
336: 327 0001A85A fe 08 effffffd4b callf $8,_writes
337: 328 0001A861 # writed( test_no );
338: 329 0001A861 dd effffffd45 pushl _test_no
339: 330 0001A867 fe 08 effffffd3e callf $8,_writed
340: 331 0001A86E # writes(", subtest 2 - A REGISTER WAS MODIFIED\n");
341: 332 0001A86E .data 1
342: 333 00000727 * L261:
343: 334 00000727 * 2C20737562746573742032202 .ascii ", subtest 2 - A REGISTER WAS MODIFIED\12\0"
344: D204120524547495354455220
345: 574153204D4F4449464945440
346: A00
347: 335 0000074e * .text
348: 336 0001A86E dd 8f00000727 pushl $L261
349: 337 0001A874 fe 08 effffffd31 callf $8,_writes
350: 338 0001A87B # print_negd_data(); /* print the operands */
351: 339 0001A87B fe 04 ef00000246 callf $4,_print_negd_data
352: 340 0001A882 # writes("\n");
353: 341 0001A882 .data 1
354: 342 0000074e * L262:
355: 343 0000074e * 0A00 .ascii "\12\0"
356: 344 00000750 * .text
357: 345 0001A882 dd 8f0000074e pushl $L262
358: 346 0001A888 fe 08 effffffd1d callf $8,_writes
359: 347 0001A88F # writes("register "); /* print the information */
360: 348 0001A88F .data 1
361: 349 00000750 * L263:
362: 350 00000750 * 72656769737465722000 .ascii "register \0"
363: 351 0000075a * .text
364: 352 0001A88F dd 8f00000750 pushl $L263
365: 353 0001A895 fe 08 effffffd10 callf $8,_writes
366: 354 0001A89C # writed( index2 ); /* about the corrupted */
367: 355 0001A89C dd effffffd0a pushl _index2
368: 356 0001A8A2 fe 08 effffffd03 callf $8,_writed
369: 357 0001A8A9 # writes(" = "); /* register */
370: 358 0001A8A9 .data 1
371: 359 0000075a * L264:
372: 360 0000075a * 203D2000 .ascii " = \0"
373: 361 0000075e * .text
374: 362 0001A8A9 dd 8f0000075a pushl $L264
375: 363 0001A8AF fe 08 effffffcf6 callf $8,_writes
376: 364 0001A8B6 # write32h( store_regs[index2] );
377: 365 0001A8B6 0d effffffcf0 50 movl _index2,r0
378: 366 0001A8BD dd 40effffffce8 pushl _store_regs[r0]
379: 367 0001A8C4 fe 08 effffffce1 callf $8,_write32h
380: 368 0001A8CB # writes(", should be = ");
381: 369 0001A8CB .data 1
382: 370 0000075e * L265:
383: 371 0000075e * 2C202073686F756C642062652 .ascii ", should be = \0"
384: 03D2000
385: 372 0000076e * .text
386: 373 0001A8CB dd 8f0000075e pushl $L265
387: 374 0001A8D1 fe 08 effffffcd4 callf $8,_writes
388: 375 0001A8D8 # write32h( load_regs[index2] );
389: 376 0001A8D8 0d effffffcce 50 movl _index2,r0
390: 377 0001A8DF dd 40effffffcc6 pushl _load_regs[r0]
391: 378 0001A8E6 fe 08 effffffcbf callf $8,_write32h
392: 379 0001A8ED # writes("\n");
393: 380 0001A8ED .data 1
394: 381 0000076e * L266:
395: 382 0000076e * 0A00 .ascii "\12\0"
396: 383 00000770 * .text
397: 384 0001A8ED dd 8f0000076e pushl $L266
398: 385 0001A8F3 fe 08 effffffcb2 callf $8,_writes
399: 386 0001A8FA # }
400: 387 0001A8FA # if( halt_flg )
401: 388 0001A8FA L257:
402: 389 0001A8FA 5d effffffcac tstl _halt_flg
403: 390 0001A900 31 09 jeql L267
404: 391 0001A902 # negd_er_halt( BAD_REG_HLT ); /* halt on the error */
405: 392 0001A902 dd 02 pushl $2
406: 393 0001A904 fe 08 ef00000225 callf $8,_negd_er_halt
407: 394 0001A90B # if( loop_on_err ) {
408: 395 0001A90B L267:
409: 396 0001A90B 5d effffffc9b tstl _loop_on_err
410: 397 0001A911 31 0a jeql L268
411: 398 0001A913 # force_loop = TRUE; /* set the force loop flag */
412: 399 0001A913 0d 01 effffffc92 movl $1,_force_loop
413: 400 0001A91A # asm("brw _negd_2_lp1");; /* and loop on the error */
414: 401 0001A91A 13 fe9a brw _negd_2_lp1
415: 402 0001A91D # } /* end of loop on error */
416: 403 0001A91D # } /* end of register corruption error */
417: 404 0001A91D L268:
418: 405 0001A91D # } /* end of subtest 2 */
419: 406 0001A91D L256:
420: 407 0001A91D 40 ret#2
421: 408 0001A91E .set L248,0x0
422: 409 0001A91E L250:
423: 410 0001A91E 13 fe5a jbr L251
424: 411 0001A921 .data
425: 412 0000068c * .text
426: 413 0001A921 00 .align 1
427: 414 0001A922 .globl _negd_3
428: 415 0001A922 _negd_3:
429: 416 0001A922 0000 .word L269
430: 417 0001A924 #
431: 418 0001A924 #
432: 419 0001A924 #
433: 420 0001A924 # /************************************************************************
434: 421 0001A924 # *
435: 422 0001A924 # * SUBTEST 3 - Check for PSL corruption
436: 423 0001A924 # *
437: 424 0001A924 # ************************************************************************/
438: 425 0001A924 # negd_3()
439: 426 0001A924 # {
440: 427 0001A924 13 019d jbr L271
441: 428 0001A927 L272:
442: 429 0001A927 # force_loop = FALSE; /* clear force_loop flg */
443: 430 0001A927 4d effffffc7f clrl _force_loop
444: 431 0001A92D # subtest = 3;
445: 432 0001A92D 0d 03 effffffc78 movl $3,_subtest
446: 433 0001A934 # fill_reg_buf( load_regs ); /* get patterns for regs */
447: 434 0001A934 dd 8f00000000 pushl $_load_regs
448: 435 0001A93A fe 08 effffffc6b callf $8,_fill_reg_buf
449: 436 0001A941 # for( index = 0; index < 3; index++ ) {
450: 437 0001A941 4d effffffc65 clrl _index
451: 438 0001A947 L275:
452: 439 0001A947 1d effffffc5f 03 cmpl _index,$3
453: 440 0001A94E 91 03 13 0170 jgeq L274
454: 441 0001A953 # dbl_ld_acc = lnd_1_data[index].ld; /* get value to negate */
455: 442 0001A953 48 04 effffffc52 50 shll $4,_index,r0
456: 443 0001A95B 0c 8f00000000 50 addl2 $_lnd_1_data,r0
457: 444 0001A962 0d a004 effffffc46 movl 4(r0),_dbl_ld_acc+4
458: 445 0001A96A 0d 60 effffffc3b movl (r0),_dbl_ld_acc
459: 446 0001A971 # /* if( no_fpp_wcs ) /* */
460: 447 0001A971 # /* dbl_expected = dbl_ld_acc; /* expected = loaded */
461: 448 0001A971 # /* else /* */
462: 449 0001A971 # /* dbl_expected = lnd_1_data[index].exp; /* expected result */
463: 450 0001A971 # sgl_dummy1 = status_array[status_index]; /* status = +, -, 0 */
464: 451 0001A971 0d effffffc35 50 movl _status_index,r0
465: 452 0001A978 0d 40effffffc2d movl _status_array[r0],_sgl_dummy1
466: effffffc28
467: 453 0001A984 # /*
468: 454 0001A984 # * If LOOP ON ERROR is set, this is the loop for this subtest.
469: 455 0001A984 # * The force loop flag is set after the first error.
470: 456 0001A984 # */
471: 457 0001A984 # asm("_negd_3_lp1:");
472: 458 0001A984 _negd_3_lp1:
473: 459 0001A984 # asm("ldd _dbl_ld_acc"); /* load the initial value */
474: 460 0001A984 07 effffffc22 ldd _dbl_ld_acc
475: 461 0001A98A # asm("tstl _sgl_dummy1"); /* set the PSL status */
476: 462 0001A98A 5d effffffc1c tstl _sgl_dummy1
477: 463 0001A990 # asm("movpsl _init_psl"); /* save the initial PSL */
478: 464 0001A990 cd effffffc16 movpsl _init_psl
479: 465 0001A996 # asm("negd"); /* negate the value */
480: 466 0001A996 b7 negd
481: 467 0001A997 # asm("nop");
482: 468 0001A997 10 nop
483: 469 0001A998 # asm("movpsl _psl_val"); /* save the final PSL */
484: 470 0001A998 cd effffffc0e movpsl _psl_val
485: 471 0001A99E # asm("std _dbl_st_acc"); /* save the accumulator */
486: 472 0001A99E 27 effffffc08 std _dbl_st_acc
487: 473 0001A9A4 # if( force_loop )
488: 474 0001A9A4 5d effffffc02 tstl _force_loop
489: 475 0001A9AA 31 02 jeql L276
490: 476 0001A9AC # asm("brb _negd_3_lp1");; /* loop on the error */
491: 477 0001A9AC 11 d6 brb _negd_3_lp1
492: 478 0001A9AE L276:
493: 479 0001A9AE # /*
494: 480 0001A9AE # * Now compare the final PSL to the initial PSL -they should be the same
495: 481 0001A9AE # */
496: 482 0001A9AE # exp_psl = init_psl;
497: 483 0001A9AE 0d effffffbf8 effffffbf3 movl _init_psl,_exp_psl
498: 484 0001A9B9 # if( psl_val != exp_psl ) {
499: 485 0001A9B9 1d effffffbed effffffbe8 cmpl _psl_val,_exp_psl
500: 486 0001A9C4 21 03 13 00f1 jeql L277
501: 487 0001A9C9 # errcnt++; /* bump the error count */
502: 488 0001A9C9 6d effffffbdd incl _errcnt
503: 489 0001A9CF # if( prt_error ) {
504: 490 0001A9CF 5d effffffbd7 tstl _prt_error
505: 491 0001A9D5 21 03 13 00bd jeql L278
506: 492 0001A9DA # writes(" \n"); /* start a new print line */
507: 493 0001A9DA .data 1
508: 494 00000770 * L279:
509: 495 00000770 * 200A00 .ascii " \12\0"
510: 496 00000773 * .text
511: 497 0001A9DA dd 8f00000770 pushl $L279
512: 498 0001A9E0 fe 08 effffffbc5 callf $8,_writes
513: 499 0001A9E7 # writes("cycle: ");
514: 500 0001A9E7 .data 1
515: 501 00000773 * L280:
516: 502 00000773 * 6379636C653A2000 .ascii "cycle: \0"
517: 503 0000077b * .text
518: 504 0001A9E7 dd 8f00000773 pushl $L280
519: 505 0001A9ED fe 08 effffffbb8 callf $8,_writes
520: 506 0001A9F4 # writed( cycle );
521: 507 0001A9F4 dd effffffbb2 pushl _cycle
522: 508 0001A9FA fe 08 effffffbab callf $8,_writed
523: 509 0001AA01 # writes(" NEGD test ");
524: 510 0001AA01 .data 1
525: 511 0000077b * L281:
526: 512 0000077b * 20204E4547442074657374200 .ascii " NEGD test \0"
527: 0
528: 513 00000788 * .text
529: 514 0001AA01 dd 8f0000077b pushl $L281
530: 515 0001AA07 fe 08 effffffb9e callf $8,_writes
531: 516 0001AA0E # writed( test_no );
532: 517 0001AA0E dd effffffb98 pushl _test_no
533: 518 0001AA14 fe 08 effffffb91 callf $8,_writed
534: 519 0001AA1B # writes(", subtest 3 - INCORRECT FINAL PSL\n");
535: 520 0001AA1B .data 1
536: 521 00000788 * L282:
537: 522 00000788 * 2C20737562746573742033202 .ascii ", subtest 3 - INCORRECT FINAL PSL\12\0"
538: D20494E434F52524543542046
539: 494E414C2050534C0A00
540: 523 000007ab * .text
541: 524 0001AA1B dd 8f00000788 pushl $L282
542: 525 0001AA21 fe 08 effffffb84 callf $8,_writes
543: 526 0001AA28 # print_negd_data(); /* print the operands */
544: 527 0001AA28 fe 04 ef00000099 callf $4,_print_negd_data
545: 528 0001AA2F # writes("\n");
546: 529 0001AA2F .data 1
547: 530 000007ab * L283:
548: 531 000007ab * 0A00 .ascii "\12\0"
549: 532 000007ad * .text
550: 533 0001AA2F dd 8f000007ab pushl $L283
551: 534 0001AA35 fe 08 effffffb70 callf $8,_writes
552: 535 0001AA3C # writes("initial PSL = ");
553: 536 0001AA3C .data 1
554: 537 000007ad * L284:
555: 538 000007ad * 696E697469616C2050534C203 .ascii "initial PSL = \0"
556: D2000
557: 539 000007bc * .text
558: 540 0001AA3C dd 8f000007ad pushl $L284
559: 541 0001AA42 fe 08 effffffb63 callf $8,_writes
560: 542 0001AA49 # write32h( init_psl );
561: 543 0001AA49 dd effffffb5d pushl _init_psl
562: 544 0001AA4F fe 08 effffffb56 callf $8,_write32h
563: 545 0001AA56 # writes(", final PSL = ");
564: 546 0001AA56 .data 1
565: 547 000007bc * L285:
566: 548 000007bc * 2C202066696E616C2050534C2 .ascii ", final PSL = \0"
567: 03D2000
568: 549 000007cc * .text
569: 550 0001AA56 dd 8f000007bc pushl $L285
570: 551 0001AA5C fe 08 effffffb49 callf $8,_writes
571: 552 0001AA63 # write32h( psl_val );
572: 553 0001AA63 dd effffffb43 pushl _psl_val
573: 554 0001AA69 fe 08 effffffb3c callf $8,_write32h
574: 555 0001AA70 # writes(", expected PSL = ");
575: 556 0001AA70 .data 1
576: 557 000007cc * L286:
577: 558 000007cc * 2C20206578706563746564205 .ascii ", expected PSL = \0"
578: 0534C203D2000
579: 559 000007df * .text
580: 560 0001AA70 dd 8f000007cc pushl $L286
581: 561 0001AA76 fe 08 effffffb2f callf $8,_writes
582: 562 0001AA7D # write32h( exp_psl );
583: 563 0001AA7D dd effffffb29 pushl _exp_psl
584: 564 0001AA83 fe 08 effffffb22 callf $8,_write32h
585: 565 0001AA8A # writes("\n");
586: 566 0001AA8A .data 1
587: 567 000007df * L287:
588: 568 000007df * 0A00 .ascii "\12\0"
589: 569 000007e1 * .text
590: 570 0001AA8A dd 8f000007df pushl $L287
591: 571 0001AA90 fe 08 effffffb15 callf $8,_writes
592: 572 0001AA97 # }
593: 573 0001AA97 # if( halt_flg )
594: 574 0001AA97 L278:
595: 575 0001AA97 5d effffffb0f tstl _halt_flg
596: 576 0001AA9D 31 09 jeql L288
597: 577 0001AA9F # negd_er_halt( BAD_PSL_HLT ); /* halt on the error */
598: 578 0001AA9F dd 03 pushl $3
599: 579 0001AAA1 fe 08 ef00000088 callf $8,_negd_er_halt
600: 580 0001AAA8 # if( loop_on_err ) {
601: 581 0001AAA8 L288:
602: 582 0001AAA8 5d effffffafe tstl _loop_on_err
603: 583 0001AAAE 31 0a jeql L289
604: 584 0001AAB0 # force_loop = TRUE; /* set the force loop flag */
605: 585 0001AAB0 0d 01 effffffaf5 movl $1,_force_loop
606: 586 0001AAB7 # asm("brw _negd_3_lp1");; /* and loop on the error */
607: 587 0001AAB7 13 feca brw _negd_3_lp1
608: 588 0001AABA # } /* end of loop on error */
609: 589 0001AABA # } /* end of PSL corruption error */
610: 590 0001AABA L289:
611: 591 0001AABA # } /* end of WHILE loop */
612: 592 0001AABA L277:
613: 593 0001AABA L273:
614: 594 0001AABA 6d effffffaec incl _index
615: 595 0001AAC0 13 fe84 jbr L275
616: 596 0001AAC3 L274:
617: 597 0001AAC3 # } /* end of subtest 3 */
618: 598 0001AAC3 40 ret#2
619: 599 0001AAC4 .set L269,0x0
620: 600 0001AAC4 L271:
621: 601 0001AAC4 13 fe60 jbr L272
622: 602 0001AAC7 .data
623: 603 0000068c * .text
624: 604 0001AAC7 00 .align 1
625: 605 0001AAC8 .globl _print_negd_data
626: 606 0001AAC8 _print_negd_data:
627: 607 0001AAC8 0000 .word L290
628: 608 0001AACA #
629: 609 0001AACA #
630: 610 0001AACA #
631: 611 0001AACA # /**************************************************************************
632: 612 0001AACA # *
633: 613 0001AACA # * PRINT THE DATA AND STORE RESULTS
634: 614 0001AACA # *
635: 615 0001AACA # * initial Acc = xxxxxxxx xxxxxxxx, final Acc = xxxxxxxx xxxxxxxx, index = xx
636: 616 0001AACA # * expected = xxxxxxxx xxxxxxxx
637: 617 0001AACA # **************************************************************************/
638: 618 0001AACA # print_negd_data()
639: 619 0001AACA # {
640: 620 0001AACA 11 61 jbr L292
641: 621 0001AACC L293:
642: 622 0001AACC # writes("initial Acc = ");
643: 623 0001AACC .data 1
644: 624 000007e1 * L294:
645: 625 000007e1 * 696E697469616C20416363203 .ascii "initial Acc = \0"
646: D2000
647: 626 000007f0 * .text
648: 627 0001AACC dd 8f000007e1 pushl $L294
649: 628 0001AAD2 fe 08 effffffad3 callf $8,_writes
650: 629 0001AAD9 # write32h( dbl_ld_acc.m );
651: 630 0001AAD9 dd effffffacd pushl _dbl_ld_acc
652: 631 0001AADF fe 08 effffffac6 callf $8,_write32h
653: 632 0001AAE6 # writec(' ');
654: 633 0001AAE6 dd 20 pushl $32
655: 634 0001AAE8 fe 08 effffffabd callf $8,_writec
656: 635 0001AAEF # write32h( dbl_ld_acc.l );
657: 636 0001AAEF dd effffffabb pushl _dbl_ld_acc+4
658: 637 0001AAF5 fe 08 effffffab0 callf $8,_write32h
659: 638 0001AAFC # writes(", final Acc = ");
660: 639 0001AAFC .data 1
661: 640 000007f0 * L295:
662: 641 000007f0 * 2C202066696E616C204163632 .ascii ", final Acc = \0"
663: 03D2000
664: 642 00000800 * .text
665: 643 0001AAFC dd 8f000007f0 pushl $L295
666: 644 0001AB02 fe 08 effffffaa3 callf $8,_writes
667: 645 0001AB09 # write32h( dbl_st_acc.m );
668: 646 0001AB09 dd effffffa9d pushl _dbl_st_acc
669: 647 0001AB0F fe 08 effffffa96 callf $8,_write32h
670: 648 0001AB16 # writec(' ');
671: 649 0001AB16 dd 20 pushl $32
672: 650 0001AB18 fe 08 effffffa8d callf $8,_writec
673: 651 0001AB1F # write32h( dbl_st_acc.l );
674: 652 0001AB1F dd effffffa8b pushl _dbl_st_acc+4
675: 653 0001AB25 fe 08 effffffa80 callf $8,_write32h
676: 654 0001AB2C # }
677: 655 0001AB2C 40 ret#2
678: 656 0001AB2D .set L290,0x0
679: 657 0001AB2D L292:
680: 658 0001AB2D 11 9d jbr L293
681: 659 0001AB2F .data
682: 660 0000068c * .text
683: 661 0001AB2F 00 .align 1
684: 662 0001AB30 .globl _negd_er_halt
685: 663 0001AB30 _negd_er_halt:
686: 664 0001AB30 0000 .word L296
687: 665 0001AB32 #
688: 666 0001AB32 #
689: 667 0001AB32 #
690: 668 0001AB32 # /**************************************************************************
691: 669 0001AB32 # *
692: 670 0001AB32 # * HALT ON ERROR ROUTINE
693: 671 0001AB32 # *
694: 672 0001AB32 # **************************************************************************/
695: 673 0001AB32 # negd_er_halt( halt_code )
696: 674 0001AB32 # int halt_code;
697: 675 0001AB32 # {
698: 676 0001AB32 13 00ff jbr L298
699: 677 0001AB35 L299:
700: 678 0001AB35 # sgl_value_1 = dbl_ld_acc.m;
701: 679 0001AB35 0d effffffa71 effffffa6c movl _dbl_ld_acc,_sgl_value_1
702: 680 0001AB40 # sgl_value_2 = dbl_ld_acc.l;
703: 681 0001AB40 0d effffffa6a effffffa61 movl _dbl_ld_acc+4,_sgl_value_2
704: 682 0001AB4B # sgl_value_3 = dbl_st_acc.m;
705: 683 0001AB4B 0d effffffa5b effffffa56 movl _dbl_st_acc,_sgl_value_3
706: 684 0001AB56 # sgl_value_4 = dbl_st_acc.l;
707: 685 0001AB56 0d effffffa54 effffffa4b movl _dbl_st_acc+4,_sgl_value_4
708: 686 0001AB61 # sgl_dummy1 = halt_code; /* get the error type */
709: 687 0001AB61 0d ad04 effffffa43 movl 4(fp),_sgl_dummy1
710: 688 0001AB69 # asm("movl _test_no,r0"); /* r0 = test number */
711: 689 0001AB69 0d effffffa3d 50 movl _test_no,r0
712: 690 0001AB70 # asm("movl _subtest,r1"); /* r1 = subtest number */
713: 691 0001AB70 0d effffffa36 51 movl _subtest,r1
714: 692 0001AB77 # asm("movl _sgl_dummy1,r2"); /* r2 = error code */
715: 693 0001AB77 0d effffffa2f 52 movl _sgl_dummy1,r2
716: 694 0001AB7E # asm("movl _cycle,r3"); /* r3 = cycle count */
717: 695 0001AB7E 0d effffffa28 53 movl _cycle,r3
718: 696 0001AB85 # asm("movl _sgl_value_1,r4"); /* r4 = MS operand 1 */
719: 697 0001AB85 0d effffffa21 54 movl _sgl_value_1,r4
720: 698 0001AB8C # asm("movl _sgl_value_2,r5"); /* r5 = LS operand 1 */
721: 699 0001AB8C 0d effffffa1a 55 movl _sgl_value_2,r5
722: 700 0001AB93 # asm("movl _sgl_value_3,r6"); /* r6 = MS stored */
723: 701 0001AB93 0d effffffa13 56 movl _sgl_value_3,r6
724: 702 0001AB9A # asm("movl _sgl_value_4,r7"); /* r7 = LS stored */
725: 703 0001AB9A 0d effffffa0c 57 movl _sgl_value_4,r7
726: 704 0001ABA1 # if( halt_code == BAD_ACC_HLT ) {
727: 705 0001ABA1 1d ad04 01 cmpl 4(fp),$1
728: 706 0001ABA5 21 2d jneq L300
729: 707 0001ABA7 # sgl_value_1 = dbl_expected.m;
730: 708 0001ABA7 0d effffff9ff effffff9fa movl _dbl_expected,_sgl_value_1
731: 709 0001ABB2 # sgl_value_2 = dbl_expected.l;
732: 710 0001ABB2 0d effffff9f8 effffff9ef movl _dbl_expected+4,_sgl_value_2
733: 711 0001ABBD # asm("movl _sgl_value_1,r8"); /* r8 = MS expected */
734: 712 0001ABBD 0d effffff9e9 58 movl _sgl_value_1,r8
735: 713 0001ABC4 # asm("movl _sgl_value_2,r9"); /* r9 = LS expected */
736: 714 0001ABC4 0d effffff9e2 59 movl _sgl_value_2,r9
737: 715 0001ABCB # asm("movl _index,r10"); /* r10 = data index */
738: 716 0001ABCB 0d effffff9db 5a movl _index,r10
739: 717 0001ABD2 # } else
740: 718 0001ABD2 11 5e jbr L301
741: 719 0001ABD4 L300:
742: 720 0001ABD4 # if( halt_code == BAD_REG_HLT ) {
743: 721 0001ABD4 1d ad04 02 cmpl 4(fp),$2
744: 722 0001ABD8 21 3d jneq L302
745: 723 0001ABDA # sgl_dummy1 = load_regs[index2];
746: 724 0001ABDA 0d effffff9cc 50 movl _index2,r0
747: 725 0001ABE1 0d 40effffff9c4 movl _load_regs[r0],_sgl_dummy1
748: effffff9bf
749: 726 0001ABED # sgl_dummy2 = store_regs[index2];
750: 727 0001ABED 0d effffff9b9 50 movl _index2,r0
751: 728 0001ABF4 0d 40effffff9b1 movl _store_regs[r0],_sgl_dummy2
752: effffff9ac
753: 729 0001AC00 # asm("movl _index2,r8"); /* r8 = bad register # */
754: 730 0001AC00 0d effffff9a6 58 movl _index2,r8
755: 731 0001AC07 # asm("movl _sgl_dummy2,r9"); /* r9 = actual value */
756: 732 0001AC07 0d effffff99f 59 movl _sgl_dummy2,r9
757: 733 0001AC0E # asm("movl _sgl_dummy1,r10"); /* r10 = expected value */
758: 734 0001AC0E 0d effffff998 5a movl _sgl_dummy1,r10
759: 735 0001AC15 # } else
760: 736 0001AC15 11 1b jbr L303
761: 737 0001AC17 L302:
762: 738 0001AC17 # if( halt_code == BAD_PSL_HLT ) {
763: 739 0001AC17 1d ad04 03 cmpl 4(fp),$3
764: 740 0001AC1B 21 15 jneq L304
765: 741 0001AC1D # asm("movl _init_psl,r8"); /* r8 = initial PSL */
766: 742 0001AC1D 0d effffff989 58 movl _init_psl,r8
767: 743 0001AC24 # asm("movl _psl_val,r9"); /* r9 = final PSL */
768: 744 0001AC24 0d effffff982 59 movl _psl_val,r9
769: 745 0001AC2B # asm("movl _exp_psl,r10"); /* r10 = expected PSL */
770: 746 0001AC2B 0d effffff97b 5a movl _exp_psl,r10
771: 747 0001AC32 # };
772: 748 0001AC32 L304:
773: 749 0001AC32 L303:
774: 750 0001AC32 L301:
775: 751 0001AC32 # asm("halt"); /* HALT ... */
776: 752 0001AC32 00 halt
777: 753 0001AC33 # }
778: 754 0001AC33 40 ret#2
779: 755 0001AC34 .set L296,0x0
780: 756 0001AC34 L298:
781: 757 0001AC34 13 fefe jbr L299
782: 758 0001AC37 .data
783: 758 000351E3 .data
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