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1.1 ! root 1: #include "fpp_defs.h" ! 2: ! 3: ! 4: ! 5: /*************************************************************************** ! 6: * ! 7: * SINF - SINGLE PRECISION FLOATING POINT SINF FUNCTION TEST ! 8: * ! 9: * SINF TEST MONITOR ! 10: * ! 11: *****************************************************************************/ ! 12: sinf() ! 13: { ! 14: asm(".globl _sinf_t"); ! 15: asm("_sinf_t:"); /* entry address */ ! 16: if( ( cycle == 1 ) && ( prt_hdrs ) ) /* print headers on 1st pass */ ! 17: { ! 18: writes(" SINF"); ! 19: } ! 20: sinf_1(); /* test square root -w/ delay */ ! 21: sinf_2(); /* test square root */ ! 22: sinf_3(); /* register corruption */ ! 23: /* sinf_4(); /* test the PSL */ ! 24: sinf_5(); /* pipelined entry */ ! 25: sinf_6(); /* pipelined exit */ ! 26: asm("jmp *return"); /* return to the test monitor */ ! 27: } ! 28: ! 29: /*************************************************************************** ! 30: * ! 31: * SUBTEST 1 - SINF FUNCTION -wait till done to store ! 32: * ! 33: ***************************************************************************/ ! 34: sinf_1() ! 35: { ! 36: #define DELAY 20 /* delay 40 ticks between SINF & STF */ ! 37: force_loop = FALSE; /* clear the LOOP flag */ ! 38: subtest = 1; ! 39: index = 0; ! 40: do ! 41: { ! 42: sgl_ld_acc = sinf_1_data[index].ld; /* get the operand */ ! 43: sgl_expected = sinf_1_data[index].exp; /* get expected results */ ! 44: sgl_dummy1 = DELAY; ! 45: /* ! 46: * If LOOP ON ERROR is set, this is the loop for this subtest. ! 47: * The force loop flag is set after the first error. ! 48: */ ! 49: asm("_sinf_1_lp1:"); ! 50: asm("movl _sgl_ld_acc,r4"); /* set the data to load */ ! 51: asm("ldf r4"); /* load the accumulator */ ! 52: asm("movl _sgl_dummy1,r0"); /* get the delay factor */ ! 53: asm("sinf"); /* get ACC.'s sine */ ! 54: asm("1:"); ! 55: asm("decl r0"); /* delay to let the SINF */ ! 56: asm("bgtr 1b"); /* instruction finish */ ! 57: asm("stf r5"); /* store the result */ ! 58: if( force_loop ) ! 59: asm("brb _sinf_1_lp1");; /* loop on the error */ ! 60: /* ! 61: * end error loop ! 62: */ ! 63: asm("movl r5,_sgl_st_acc"); /* save the result */ ! 64: if( sgl_st_acc != sgl_expected ) { /* COMPARE the values */ ! 65: errcnt++; /* bump the error count */ ! 66: if ( prt_error ) { ! 67: writes(" \n"); /* start a new print line */ ! 68: writes("cycle: "); ! 69: writed( cycle ); ! 70: writes(" SINF test "); ! 71: writed( test_no ); ! 72: writes(", subtest 1 (delayed store) - BAD FINAL ACC\n"); ! 73: print_sinf_data(); ! 74: writes(", data index = "); ! 75: writed( index ); ! 76: writec('\n'); ! 77: writes(" Acc expected = "); ! 78: write32h( sgl_expected ); ! 79: writec('\n'); ! 80: } ! 81: if ( halt_flg ) /* halt on error? */ ! 82: sinf_er_halt( BAD_ACC_HLT ); ! 83: if ( loop_on_err ) ! 84: { ! 85: force_loop = TRUE; /* set the force loop flag */ ! 86: asm("jmp _sinf_1_lp1"); /* and loop */ ! 87: } ! 88: } /* end of compare error */ ! 89: } while( index++ < max_sinf_1_index ); ! 90: } /* end of subtest 1 */ ! 91: ! 92: ! 93: ! 94: /*************************************************************************** ! 95: * ! 96: * SUBTEST 2 - SINF FUNCTION ! 97: * ! 98: ***************************************************************************/ ! 99: sinf_2() ! 100: { ! 101: force_loop = FALSE; /* clear the LOOP flag */ ! 102: subtest = 2; ! 103: index = 0; ! 104: do ! 105: { ! 106: sgl_ld_acc = sinf_1_data[index].ld; /* get the operand */ ! 107: sgl_expected = sinf_1_data[index].exp; /* get expected results */ ! 108: /* ! 109: * If LOOP ON ERROR is set, this is the loop for this subtest. ! 110: * The force loop flag is set after the first error. ! 111: */ ! 112: asm("_sinf_2_lp1:"); ! 113: asm("movl _sgl_ld_acc,r4"); /* set the data to load */ ! 114: asm("ldf r4"); /* load the accumulator */ ! 115: asm("sinf"); /* get ACC.'s sine */ ! 116: asm("stf r5"); /* store the result */ ! 117: if( force_loop ) ! 118: asm("brb _sinf_2_lp1");; /* loop on the error */ ! 119: /* ! 120: * end error loop ! 121: */ ! 122: asm("movl r5,_sgl_st_acc"); /* save the result */ ! 123: if( sgl_st_acc != sgl_expected ) { /* COMPARE the values */ ! 124: errcnt++; /* bump the error count */ ! 125: if ( prt_error ) { ! 126: writes(" \n"); /* start a new print line */ ! 127: writes("cycle: "); ! 128: writed( cycle ); ! 129: writes(" SINF test "); ! 130: writed( test_no ); ! 131: writes(", subtest 2 (immediate store) - BAD FINAL ACC\n"); ! 132: print_sinf_data(); ! 133: writes(", data index = "); ! 134: writed( index ); ! 135: writec('\n'); ! 136: writes(" Acc expected = "); ! 137: write32h( sgl_expected ); ! 138: writec('\n'); ! 139: } ! 140: if ( halt_flg ) /* halt on error? */ ! 141: sinf_er_halt( BAD_ACC_HLT ); ! 142: if ( loop_on_err ) ! 143: { ! 144: force_loop = TRUE; /* set the force loop flag */ ! 145: asm("jmp _sinf_2_lp1"); /* and loop */ ! 146: } ! 147: } /* end of compare error */ ! 148: } while( index++ < max_sinf_1_index ); ! 149: } /* end of subtest 2 */ ! 150: ! 151: ! 152: ! 153: /*************************************************************************** ! 154: * ! 155: * SUBTEST 3 - REGISTER INTEGRITY WITH THE SINF FUNCTION ! 156: * ! 157: ***************************************************************************/ ! 158: sinf_3() ! 159: { ! 160: fill_reg_buf( load_regs ); /* set reg values to load */ ! 161: force_loop = FALSE; /* clear the LOOP flag */ ! 162: subtest = 3; ! 163: index = 0; ! 164: do ! 165: { ! 166: sgl_ld_acc = sinf_1_data[index].ld; /* get the operand */ ! 167: sgl_expected = sinf_1_data[index].exp; /* get expected results */ ! 168: /* ! 169: * If LOOP ON ERROR is set, this is the loop for this subtest. ! 170: * The force loop flag is set after the first error. ! 171: */ ! 172: asm("_sinf_3_lp1:"); ! 173: asm("loadr $0x1fff,_load_regs"); /* load regs 0 - 12 */ ! 174: asm("ldf _sgl_ld_acc"); /* load the accumulator */ ! 175: asm("sinf"); /* get ACC.'s sine */ ! 176: asm("stf _sgl_st_acc"); /* store the result */ ! 177: asm("storer $0x1fff,_store_regs"); /* store regs 0 - 12 */ ! 178: if( force_loop ) ! 179: asm("brb _sinf_3_lp1");; /* loop on the error */ ! 180: /* ! 181: * end error loop ! 182: */ ! 183: reg_no = 0; ! 184: regs_ok = TRUE; ! 185: while( (reg_no < 13) && (regs_ok) ) /* check 1st 12 regs */ ! 186: if( store_regs[ reg_no ] == load_regs[ reg_no ] ) ! 187: reg_no++; ! 188: else ! 189: regs_ok = FALSE; ! 190: if( !regs_ok ) { ! 191: errcnt++; /* bump the error count */ ! 192: if ( prt_error ) { ! 193: writes(" \n"); /* start a new print line */ ! 194: writes("cycle: "); ! 195: writed( cycle ); ! 196: writes(" SINF test "); ! 197: writed( test_no ); ! 198: writes(", subtest 3 - A REGISTER WAS MODIFIED\n"); { ! 199: print_sinf_data(); ! 200: writec('\n'); ! 201: writes("register "); ! 202: writed( reg_no ); ! 203: writes(" = "); ! 204: write32h( load_regs[reg_no] ); ! 205: writes(", should be = "); ! 206: write32h( store_regs[reg_no] ); ! 207: writec('\n'); ! 208: } ! 209: if ( halt_flg ) /* halt on error? */ ! 210: sinf_er_halt( BAD_REG_HLT ); ! 211: if ( loop_on_err ) ! 212: { ! 213: force_loop = TRUE; /* get the force loop flag */ ! 214: asm("jmp _sinf_3_lp1"); /* and loop */ ! 215: } ! 216: } /* end of compare error */ ! 217: } /* end of while loop */ ! 218: } while( index++ < max_sinf_1_index ); ! 219: } /* end of subtest 3 */ ! 220: ! 221: ! 222: ! 223: /************************************************************************ ! 224: * ! 225: * SUBTEST 4 - Check for PSL corruption ! 226: * ! 227: ************************************************************************/ ! 228: sinf_4() ! 229: { ! 230: force_loop = FALSE; /* clear force_loop flg */ ! 231: subtest = 4; ! 232: fill_reg_buf( load_regs ); /* get patterns for regs */ ! 233: for( index = 0; index < 3; index++ ) { ! 234: sgl_ld_acc = sinf_1_data[index].ld; /* get operand 1 */ ! 235: sgl_expected = sinf_1_data[index].exp; /* get expected */ ! 236: sgl_dummy1 = status_array[status_index]; /* status = +, -, 0 */ ! 237: /* ! 238: * If LOOP ON ERROR is set, this is the loop for this subtest. ! 239: * The force loop flag is set after the first error. ! 240: */ ! 241: asm("_sinf_4_lp1:"); ! 242: asm("ldf _sgl_ld_acc"); /* LOAD the accumulator */ ! 243: asm("nop"); ! 244: asm("tstl _sgl_dummy1"); /* set the PSL status */ ! 245: asm("movpsl _init_psl"); /* save the initial PSL */ ! 246: asm("sinf"); /* do the sine */ ! 247: asm("nop"); ! 248: asm("movpsl _psl_val"); /* save the final PSL */ ! 249: asm("stf _sgl_st_acc"); /* save the accumulator */ ! 250: if( force_loop ) ! 251: asm("brb _sinf_4_lp1");; /* loop on the error */ ! 252: /* ! 253: * Now compare the final PSL to the initial PSL -they should be the same ! 254: */ ! 255: exp_psl = init_psl; ! 256: if( psl_val != exp_psl ) { ! 257: errcnt++; /* bump the error count */ ! 258: if( prt_error ) { ! 259: writes(" \n"); /* start a new print line */ ! 260: writes("cycle: "); ! 261: writed( cycle ); ! 262: writes(" SINF test "); ! 263: writed( test_no ); ! 264: writes(", subtest 4 - INCORRECT FINAL PSL\n"); ! 265: print_sinf_data(); /* print the operands */ ! 266: writes("\n"); ! 267: writes("initial PSL = "); ! 268: write32h( init_psl ); ! 269: writes(", final PSL = "); ! 270: write32h( psl_val ); ! 271: writes(", expected PSL = "); ! 272: write32h( exp_psl ); ! 273: writes("\n"); ! 274: } ! 275: if( halt_flg ) ! 276: sinf_er_halt( BAD_PSL_HLT ); /* halt on the error */ ! 277: if( loop_on_err ) { ! 278: force_loop = TRUE; /* set the force loop flag */ ! 279: asm("brw _sinf_4_lp1");; /* and loop on the error */ ! 280: } /* end of loop on error */ ! 281: } /* end of PSL corruption error */ ! 282: } /* end of WHILE loop */ ! 283: } /* end of subtest 4 */ ! 284: ! 285: ! 286: ! 287: /************************************************************************ ! 288: * ! 289: * SUBTEST 5 - pipelined entry test ! 290: * ! 291: ************************************************************************/ ! 292: sinf_5() ! 293: { ! 294: force_loop = FALSE; ! 295: subtest = 8; ! 296: for( index = 0; index < max_sinf_1_index; index++ ) { ! 297: sgl_ld_acc = sinf_1_data[index].ld; /* get operand 1 */ ! 298: sgl_expected = sinf_1_data[index].exp; /* get expected result */ ! 299: /* ! 300: * If LOOP ON ERROR is set, this is the loop for this subtest. ! 301: * The force loop flag is set after the first error. ! 302: */ ! 303: asm("_sinf_5_lp1:"); ! 304: asm("movl $0,r0"); /* clear r0 */ ! 305: asm("ldf r0"); /* load the Acc. with 0.0 */ ! 306: asm("addf _sgl_ld_acc"); /* add the 1st operand */ ! 307: asm("sinf"); /* get the sine */ ! 308: asm("stf _sgl_st_acc"); /* store the result */ ! 309: if( force_loop ) ! 310: asm("brb _sinf_5_lp1");; /* loop on the error */ ! 311: /* ! 312: * end error loop - test the results ! 313: */ ! 314: if( sgl_st_acc != sgl_expected ) { /* COMPARE the values */ ! 315: errcnt++; /* bump the error count */ ! 316: if( prt_error ) { ! 317: writes(" \n"); /* start a new print line */ ! 318: writes("cycle: "); ! 319: writed( cycle ); ! 320: writes(" SINF test "); ! 321: writed( test_no ); ! 322: writes(", subtest 5 (Piped Entry) - BAD FINAL ACC\n"); ! 323: print_sinf_data(); ! 324: writes(", data index = "); ! 325: writed( index ); ! 326: writec('\n'); ! 327: writes(" Acc expected = "); ! 328: write32h( sgl_expected ); ! 329: writec('\n'); ! 330: } ! 331: if( halt_flg ) ! 332: sinf_er_halt( BAD_ACC_HLT ); /* halt on the error */ ! 333: if( loop_on_err ) { ! 334: force_loop = TRUE; /* set the force loop flag */ ! 335: asm("brw _sinf_5_lp1");; /* and loop on the error */ ! 336: } /* end of loop on error */ ! 337: } /* end of compare error */ ! 338: } /* end of WHILE loop */ ! 339: } /* end of subtest 5 */ ! 340: ! 341: ! 342: ! 343: /************************************************************************ ! 344: * ! 345: * SUBTEST 6 - pipelined exit test ! 346: * ! 347: ************************************************************************/ ! 348: sinf_6() ! 349: { ! 350: force_loop = FALSE; ! 351: subtest = 8; ! 352: for( index = 0; index < max_sinf_1_index; index++ ) { ! 353: sgl_ld_acc = sinf_1_data[index].ld; /* get operand 1 */ ! 354: sgl_expected = sinf_1_data[index].exp; /* get expected result */ ! 355: /* ! 356: * If LOOP ON ERROR is set, this is the loop for this subtest. ! 357: * The force loop flag is set after the first error. ! 358: */ ! 359: asm("_sinf_6_lp1:"); ! 360: asm("movl $0,r0"); /* clear r0 */ ! 361: asm("ldf _sgl_ld_acc"); /* load the Acc. */ ! 362: asm("sinf"); /* get the sine */ ! 363: asm("addf r0"); /* add a zero to the acc */ ! 364: asm("stf _sgl_st_acc"); /* store the result */ ! 365: if( force_loop ) ! 366: asm("brb _sinf_6_lp1");; /* loop on the error */ ! 367: /* ! 368: * end error loop - test the results ! 369: */ ! 370: if( sgl_st_acc != sgl_expected ) { /* COMPARE the values */ ! 371: errcnt++; /* bump the error count */ ! 372: if( prt_error ) { ! 373: writes(" \n"); /* start a new print line */ ! 374: writes("cycle: "); ! 375: writed( cycle ); ! 376: writes(" SINF test "); ! 377: writed( test_no ); ! 378: writes(", subtest 6 (Piped Exit) - BAD FINAL ACC\n"); ! 379: print_sinf_data(); ! 380: writes(", data index = "); ! 381: writed( index ); ! 382: writec('\n'); ! 383: writes(" Acc expected = "); ! 384: write32h( sgl_expected ); ! 385: writec('\n'); ! 386: } ! 387: if( halt_flg ) ! 388: sinf_er_halt( BAD_ACC_HLT ); /* halt on the error */ ! 389: if( loop_on_err ) { ! 390: force_loop = TRUE; /* set the force loop flag */ ! 391: asm("brw _sinf_6_lp1");; /* and loop on the error */ ! 392: } /* end of loop on error */ ! 393: } /* end of compare error */ ! 394: } /* end of WHILE loop */ ! 395: } /* end of subtest 6 */ ! 396: ! 397: ! 398: /************************************************************************** ! 399: * ! 400: * PRINT THE DATA AND STORE RESULTS ! 401: * ! 402: * initial Acc = xxxxxxxx, stored = xxxxxxxx, data index = xx ! 403: * Acc expected = xxxxxxxx ! 404: **************************************************************************/ ! 405: print_sinf_data() ! 406: { ! 407: writes("initial Acc = "); ! 408: write32h( sgl_ld_acc ); ! 409: writes(", final Acc = "); ! 410: write32h( sgl_st_acc ); ! 411: } ! 412: ! 413: ! 414: ! 415: /************************************************************************** ! 416: * ! 417: * HALT ON ERROR ROUTINE ! 418: * ! 419: **************************************************************************/ ! 420: sinf_er_halt( halt_code ) ! 421: int halt_code; ! 422: { ! 423: sgl_dummy1 = halt_code; /* get the error type */ ! 424: asm("movl _test_no,r0"); /* r0 = test number */ ! 425: asm("movl _subtest,r1"); /* r1 = subtest number */ ! 426: asm("movl _sgl_dummy1,r2"); /* r2 = error code */ ! 427: asm("movl _cycle,r3"); /* r3 = cycle count */ ! 428: asm("movl _sgl_ld_acc,r4"); /* r4 = initial data */ ! 429: asm("movl _sgl_st_acc,r5"); /* r5 = data stored */ ! 430: asm("movl _sgl_expected,r6"); /* r6 = data expected */ ! 431: asm("movl _index,r7"); /* r7 = data index */ ! 432: if( halt_code == BAD_REG_HLT ) { ! 433: sgl_dummy1 = load_regs[index2]; ! 434: sgl_dummy2 = store_regs[index2]; ! 435: asm("movl _index2,r6"); /* r6 = bad register # */ ! 436: asm("movl _sgl_dummy2,r7"); /* r7 = actual value */ ! 437: asm("movl _sgl_dummy1,r8"); /* r8 = expected value */ ! 438: } else ! 439: if( halt_code == BAD_PSL_HLT ) { ! 440: asm("movl _init_psl,r6"); /* r6 = initial PSL */ ! 441: asm("movl _psl_val,r7"); /* r7 = final PSL */ ! 442: asm("movl _exp_psl,r8"); /* r8 = expected PSL */ ! 443: }; ! 444: asm("halt"); /* HALT ... */ ! 445: }
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