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Up to [Power 6/32 Unix Tahoe 4.2BSD] / cci / d / macro4|
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1.1 root 1: 1 00000000 LL0:
2: 2 00000000 .data
3: 3 00000a5c * .text
4: 4 00000000 .align 1
5: 5 00000000 .globl _sinf
6: 6 00000000 _sinf:
7: 7 0002201C 0000 .word L215
8: 8 0002201E # #include "fpp_defs.h"
9: 9 0002201E #
10: 10 0002201E #
11: 11 0002201E #
12: 12 0002201E # /***************************************************************************
13: 13 0002201E # *
14: 14 0002201E # * SINF - SINGLE PRECISION FLOATING POINT SINF FUNCTION TEST
15: 15 0002201E # *
16: 16 0002201E # * SINF TEST MONITOR
17: 17 0002201E # *
18: 18 0002201E # *****************************************************************************/
19: 19 0002201E # sinf()
20: 20 0002201E # {
21: 21 0002201E 11 48 jbr L217
22: 22 00022020 L218:
23: 23 00022020 # asm(".globl _sinf_t");
24: 24 00022020 .globl _sinf_t
25: 25 00022020 # asm("_sinf_t:"); /* entry address */
26: 26 00022020 _sinf_t:
27: 27 00022020 # if( ( cycle == 1 ) && ( prt_hdrs ) ) /* print headers on 1st pass */
28: 28 00022020 1d effffffff6 01 cmpl _cycle,$1
29: 29 00022027 21 15 jneq L219
30: 30 00022029 5d efffffffed tstl _prt_hdrs
31: 31 0002202F 31 0d jeql L219
32: 32 00022031 # {
33: 33 00022031 # writes(" SINF");
34: 34 00022031 .data 1
35: 35 00000a5c * L221:
36: 36 00000a5c * 2053494E4600 .ascii " SINF\0"
37: 37 00000a62 * .text
38: 38 00022031 dd 8f00000a5c pushl $L221
39: 39 00022037 fe 08 efffffffde callf $8,_writes
40: 40 0002203E # }
41: 41 0002203E # sinf_1(); /* test square root -w/ delay */
42: 42 0002203E L219:
43: 43 0002203E fe 04 ef00000025 callf $4,_sinf_1
44: 44 00022045 # sinf_2(); /* test square root */
45: 45 00022045 fe 04 ef00000190 callf $4,_sinf_2
46: 46 0002204C # sinf_3(); /* register corruption */
47: 47 0002204C fe 04 ef000002e9 callf $4,_sinf_3
48: 48 00022053 # /* sinf_4(); /* test the PSL */
49: 49 00022053 # sinf_5(); /* pipelined entry */
50: 50 00022053 fe 04 ef00000680 callf $4,_sinf_5
51: 51 0002205A # sinf_6(); /* pipelined exit */
52: 52 0002205A fe 04 ef000007d5 callf $4,_sinf_6
53: 53 00022061 # asm("jmp *return"); /* return to the test monitor */
54: 54 00022061 71 ffffffffb5 jmp *return
55: 55 00022067 # }
56: 56 00022067 40 ret#2
57: 57 00022068 .set L215,0x0
58: 58 00022068 L217:
59: 59 00022068 11 b6 jbr L218
60: 60 0002206A .data
61: 61 00000a5c * .text
62: 62 0002206A .align 1
63: 63 0002206A .globl _sinf_1
64: 64 0002206A _sinf_1:
65: 65 0002206A 0000 .word L227
66: 66 0002206C #
67: 67 0002206C # /***************************************************************************
68: 68 0002206C # *
69: 69 0002206C # * SUBTEST 1 - SINF FUNCTION -wait till done to store
70: 70 0002206C # *
71: 71 0002206C # ***************************************************************************/
72: 72 0002206C # sinf_1()
73: 73 0002206C # {
74: 74 0002206C 13 016a jbr L229
75: 75 0002206F L230:
76: 76 0002206F # #define DELAY 20 /* delay 40 ticks between SINF & STF */
77: 77 0002206F # force_loop = FALSE; /* clear the LOOP flag */
78: 78 0002206F 4d efffffffa7 clrl _force_loop
79: 79 00022075 # subtest = 1;
80: 80 00022075 0d 01 efffffffa0 movl $1,_subtest
81: 81 0002207C # index = 0;
82: 82 0002207C 4d efffffff9a clrl _index
83: 83 00022082 # do
84: 84 00022082 L233:
85: 85 00022082 # {
86: 86 00022082 # sgl_ld_acc = sinf_1_data[index].ld; /* get the operand */
87: 87 00022082 0d efffffff94 50 movl _index,r0
88: 88 00022089 48 03 50 50 shll $3,r0,r0
89: 89 0002208D 0d e000000000 efffffff84 movl _sinf_1_data(r0),_sgl_ld_acc
90: 90 00022098 # sgl_expected = sinf_1_data[index].exp; /* get expected results */
91: 91 00022098 0d efffffff7e 50 movl _index,r0
92: 92 0002209F 48 03 50 50 shll $3,r0,r0
93: 93 000220A3 0d e000000004 efffffff6e movl _sinf_1_data+4(r0),_sgl_expected
94: 94 000220AE # sgl_dummy1 = DELAY;
95: 95 000220AE 0d 14 efffffff67 movl $20,_sgl_dummy1
96: 96 000220B5 # /*
97: 97 000220B5 # * If LOOP ON ERROR is set, this is the loop for this subtest.
98: 98 000220B5 # * The force loop flag is set after the first error.
99: 99 000220B5 # */
100: 100 000220B5 # asm("_sinf_1_lp1:");
101: 101 000220B5 _sinf_1_lp1:
102: 102 000220B5 # asm("movl _sgl_ld_acc,r4"); /* set the data to load */
103: 103 000220B5 0d efffffff61 54 movl _sgl_ld_acc,r4
104: 104 000220BC # asm("ldf r4"); /* load the accumulator */
105: 105 000220BC 06 54 ldf r4
106: 106 000220BE # asm("movl _sgl_dummy1,r0"); /* get the delay factor */
107: 107 000220BE 0d efffffff58 50 movl _sgl_dummy1,r0
108: 108 000220C5 # asm("sinf"); /* get ACC.'s sine */
109: 109 000220C5 05 sinf
110: 110 000220C6 # asm("1:");
111: 111 000220C6 1:
112: 112 000220C6 # asm("decl r0"); /* delay to let the SINF */
113: 113 000220C6 7d 50 decl r0
114: 114 000220C8 # asm("bgtr 1b"); /* instruction finish */
115: 115 000220C8 41 fc bgtr 1b
116: 116 000220CA # asm("stf r5"); /* store the result */
117: 117 000220CA 26 55 stf r5
118: 118 000220CC # if( force_loop )
119: 119 000220CC 5d efffffff4a tstl _force_loop
120: 120 000220D2 31 02 jeql L234
121: 121 000220D4 # asm("brb _sinf_1_lp1");; /* loop on the error */
122: 122 000220D4 11 df brb _sinf_1_lp1
123: 123 000220D6 L234:
124: 124 000220D6 # /*
125: 125 000220D6 # * end error loop
126: 126 000220D6 # */
127: 127 000220D6 # asm("movl r5,_sgl_st_acc"); /* save the result */
128: 128 000220D6 0d 55 efffffff3f movl r5,_sgl_st_acc
129: 129 000220DD # if( sgl_st_acc != sgl_expected ) { /* COMPARE the values */
130: 130 000220DD 1d efffffff39 efffffff34 cmpl _sgl_st_acc,_sgl_expected
131: 131 000220E8 21 03 13 00d2 jeql L235
132: 132 000220ED # errcnt++; /* bump the error count */
133: 133 000220ED 6d efffffff29 incl _errcnt
134: 134 000220F3 # if ( prt_error ) {
135: 135 000220F3 5d efffffff23 tstl _prt_error
136: 136 000220F9 21 03 13 009b jeql L236
137: 137 000220FE # writes(" \n"); /* start a new print line */
138: 138 000220FE .data 1
139: 139 00000a62 * L237:
140: 140 00000a62 * 200A00 .ascii " \12\0"
141: 141 00000a65 * .text
142: 142 000220FE dd 8f00000a62 pushl $L237
143: 143 00022104 fe 08 efffffff11 callf $8,_writes
144: 144 0002210B # writes("cycle: ");
145: 145 0002210B .data 1
146: 146 00000a65 * L238:
147: 147 00000a65 * 6379636C653A2000 .ascii "cycle: \0"
148: 148 00000a6d * .text
149: 149 0002210B dd 8f00000a65 pushl $L238
150: 150 00022111 fe 08 efffffff04 callf $8,_writes
151: 151 00022118 # writed( cycle );
152: 152 00022118 dd effffffefe pushl _cycle
153: 153 0002211E fe 08 effffffef7 callf $8,_writed
154: 154 00022125 # writes(" SINF test ");
155: 155 00022125 .data 1
156: 156 00000a6d * L240:
157: 157 00000a6d * 20202053494E4620746573742 .ascii " SINF test \0"
158: 000
159: 158 00000a7b * .text
160: 159 00022125 dd 8f00000a6d pushl $L240
161: 160 0002212B fe 08 effffffeea callf $8,_writes
162: 161 00022132 # writed( test_no );
163: 162 00022132 dd effffffee4 pushl _test_no
164: 163 00022138 fe 08 effffffedd callf $8,_writed
165: 164 0002213F # writes(", subtest 1 (delayed store) - BAD FINAL ACC\n");
166: 165 0002213F .data 1
167: 166 00000a7b * L241:
168: 167 00000a7b * 2C20737562746573742031202 .ascii ", subtest 1 (delayed store) - BAD FINAL ACC\12\0"
169: 864656C617965642073746F72
170: 6529202D204241442046494E4
171: 14C204143430A00
172: 168 00000aa8 * .text
173: 169 0002213F dd 8f00000a7b pushl $L241
174: 170 00022145 fe 08 effffffed0 callf $8,_writes
175: 171 0002214C # print_sinf_data();
176: 172 0002214C fe 04 ef0000083f callf $4,_print_sinf_data
177: 173 00022153 # writes(", data index = ");
178: 174 00022153 .data 1
179: 175 00000aa8 * L243:
180: 176 00000aa8 * 2C20206461746120696E64657 .ascii ", data index = \0"
181: 8203D2000
182: 177 00000ab9 * .text
183: 178 00022153 dd 8f00000aa8 pushl $L243
184: 179 00022159 fe 08 effffffebc callf $8,_writes
185: 180 00022160 # writed( index );
186: 181 00022160 dd effffffeb6 pushl _index
187: 182 00022166 fe 08 effffffeaf callf $8,_writed
188: 183 0002216D # writec('\n');
189: 184 0002216D dd 0a pushl $10
190: 185 0002216F fe 08 effffffea6 callf $8,_writec
191: 186 00022176 # writes(" Acc expected = ");
192: 187 00022176 .data 1
193: 188 00000ab9 * L245:
194: 189 00000ab9 * 2020202020202020202020202 .ascii " Acc expected = \0"
195: 0202020202020202020416363
196: 206578706563746564203D200
197: 0
198: 190 00000adf * .text
199: 191 00022176 dd 8f00000ab9 pushl $L245
200: 192 0002217C fe 08 effffffe99 callf $8,_writes
201: 193 00022183 # write32h( sgl_expected );
202: 194 00022183 dd effffffe93 pushl _sgl_expected
203: 195 00022189 fe 08 effffffe8c callf $8,_write32h
204: 196 00022190 # writec('\n');
205: 197 00022190 dd 0a pushl $10
206: 198 00022192 fe 08 effffffe83 callf $8,_writec
207: 199 00022199 # }
208: 200 00022199 # if ( halt_flg ) /* halt on error? */
209: 201 00022199 L236:
210: 202 00022199 5d effffffe7d tstl _halt_flg
211: 203 0002219F 31 09 jeql L247
212: 204 000221A1 # sinf_er_halt( BAD_ACC_HLT );
213: 205 000221A1 dd 01 pushl $1
214: 206 000221A3 fe 08 ef00000824 callf $8,_sinf_er_halt
215: 207 000221AA # if ( loop_on_err )
216: 208 000221AA L247:
217: 209 000221AA 5d effffffe6c tstl _loop_on_err
218: 210 000221B0 31 0d jeql L249
219: 211 000221B2 # {
220: 212 000221B2 # force_loop = TRUE; /* set the force loop flag */
221: 213 000221B2 0d 01 effffffe63 movl $1,_force_loop
222: 214 000221B9 # asm("jmp _sinf_1_lp1"); /* and loop */
223: 215 000221B9 71 effffffef6 jmp _sinf_1_lp1
224: 216 000221BF # }
225: 217 000221BF # } /* end of compare error */
226: 218 000221BF L249:
227: 219 000221BF # } while( index++ < max_sinf_1_index );
228: 220 000221BF L235:
229: 221 000221BF L232:
230: 222 000221BF 0d effffffe57 50 movl _index,r0
231: 223 000221C6 6d effffffe50 incl _index
232: 224 000221CC 1d 50 effffffe49 cmpl r0,_max_sinf_1_index
233: 225 000221D3 81 03 13 feaa jlss L233
234: 226 000221D8 L231:
235: 227 000221D8 # } /* end of subtest 1 */
236: 228 000221D8 40 ret#2
237: 229 000221D9 .set L227,0x0
238: 230 000221D9 L229:
239: 231 000221D9 13 fe93 jbr L230
240: 232 000221DC .data
241: 233 00000a5c * .text
242: 234 000221DC .align 1
243: 235 000221DC .globl _sinf_2
244: 236 000221DC _sinf_2:
245: 237 000221DC 0000 .word L250
246: 238 000221DE #
247: 239 000221DE #
248: 240 000221DE #
249: 241 000221DE # /***************************************************************************
250: 242 000221DE # *
251: 243 000221DE # * SUBTEST 2 - SINF FUNCTION
252: 244 000221DE # *
253: 245 000221DE # ***************************************************************************/
254: 246 000221DE # sinf_2()
255: 247 000221DE # {
256: 248 000221DE 13 0158 jbr L252
257: 249 000221E1 L253:
258: 250 000221E1 # force_loop = FALSE; /* clear the LOOP flag */
259: 251 000221E1 4d effffffe35 clrl _force_loop
260: 252 000221E7 # subtest = 2;
261: 253 000221E7 0d 02 effffffe2e movl $2,_subtest
262: 254 000221EE # index = 0;
263: 255 000221EE 4d effffffe28 clrl _index
264: 256 000221F4 # do
265: 257 000221F4 L256:
266: 258 000221F4 # {
267: 259 000221F4 # sgl_ld_acc = sinf_1_data[index].ld; /* get the operand */
268: 260 000221F4 0d effffffe22 50 movl _index,r0
269: 261 000221FB 48 03 50 50 shll $3,r0,r0
270: 262 000221FF 0d e000000000 effffffe12 movl _sinf_1_data(r0),_sgl_ld_acc
271: 263 0002220A # sgl_expected = sinf_1_data[index].exp; /* get expected results */
272: 264 0002220A 0d effffffe0c 50 movl _index,r0
273: 265 00022211 48 03 50 50 shll $3,r0,r0
274: 266 00022215 0d e000000004 effffffdfc movl _sinf_1_data+4(r0),_sgl_expected
275: 267 00022220 # /*
276: 268 00022220 # * If LOOP ON ERROR is set, this is the loop for this subtest.
277: 269 00022220 # * The force loop flag is set after the first error.
278: 270 00022220 # */
279: 271 00022220 # asm("_sinf_2_lp1:");
280: 272 00022220 _sinf_2_lp1:
281: 273 00022220 # asm("movl _sgl_ld_acc,r4"); /* set the data to load */
282: 274 00022220 0d effffffdf6 54 movl _sgl_ld_acc,r4
283: 275 00022227 # asm("ldf r4"); /* load the accumulator */
284: 276 00022227 06 54 ldf r4
285: 277 00022229 # asm("sinf"); /* get ACC.'s sine */
286: 278 00022229 05 sinf
287: 279 0002222A # asm("stf r5"); /* store the result */
288: 280 0002222A 26 55 stf r5
289: 281 0002222C # if( force_loop )
290: 282 0002222C 5d effffffdea tstl _force_loop
291: 283 00022232 31 02 jeql L257
292: 284 00022234 # asm("brb _sinf_2_lp1");; /* loop on the error */
293: 285 00022234 11 ea brb _sinf_2_lp1
294: 286 00022236 L257:
295: 287 00022236 # /*
296: 288 00022236 # * end error loop
297: 289 00022236 # */
298: 290 00022236 # asm("movl r5,_sgl_st_acc"); /* save the result */
299: 291 00022236 0d 55 effffffddf movl r5,_sgl_st_acc
300: 292 0002223D # if( sgl_st_acc != sgl_expected ) { /* COMPARE the values */
301: 293 0002223D 1d effffffdd9 effffffdd4 cmpl _sgl_st_acc,_sgl_expected
302: 294 00022248 21 03 13 00d2 jeql L258
303: 295 0002224D # errcnt++; /* bump the error count */
304: 296 0002224D 6d effffffdc9 incl _errcnt
305: 297 00022253 # if ( prt_error ) {
306: 298 00022253 5d effffffdc3 tstl _prt_error
307: 299 00022259 21 03 13 009b jeql L259
308: 300 0002225E # writes(" \n"); /* start a new print line */
309: 301 0002225E .data 1
310: 302 00000adf * L260:
311: 303 00000adf * 200A00 .ascii " \12\0"
312: 304 00000ae2 * .text
313: 305 0002225E dd 8f00000adf pushl $L260
314: 306 00022264 fe 08 effffffdb1 callf $8,_writes
315: 307 0002226B # writes("cycle: ");
316: 308 0002226B .data 1
317: 309 00000ae2 * L261:
318: 310 00000ae2 * 6379636C653A2000 .ascii "cycle: \0"
319: 311 00000aea * .text
320: 312 0002226B dd 8f00000ae2 pushl $L261
321: 313 00022271 fe 08 effffffda4 callf $8,_writes
322: 314 00022278 # writed( cycle );
323: 315 00022278 dd effffffd9e pushl _cycle
324: 316 0002227E fe 08 effffffd97 callf $8,_writed
325: 317 00022285 # writes(" SINF test ");
326: 318 00022285 .data 1
327: 319 00000aea * L262:
328: 320 00000aea * 20202053494E4620746573742 .ascii " SINF test \0"
329: 000
330: 321 00000af8 * .text
331: 322 00022285 dd 8f00000aea pushl $L262
332: 323 0002228B fe 08 effffffd8a callf $8,_writes
333: 324 00022292 # writed( test_no );
334: 325 00022292 dd effffffd84 pushl _test_no
335: 326 00022298 fe 08 effffffd7d callf $8,_writed
336: 327 0002229F # writes(", subtest 2 (immediate store) - BAD FINAL ACC\n");
337: 328 0002229F .data 1
338: 329 00000af8 * L263:
339: 330 00000af8 * 2C20737562746573742032202 .ascii ", subtest 2 (immediate store) - BAD FINAL ACC\12\0"
340: 8696D6D656469617465207374
341: 6F726529202D2042414420464
342: 94E414C204143430A00
343: 331 00000b27 * .text
344: 332 0002229F dd 8f00000af8 pushl $L263
345: 333 000222A5 fe 08 effffffd70 callf $8,_writes
346: 334 000222AC # print_sinf_data();
347: 335 000222AC fe 04 ef000006df callf $4,_print_sinf_data
348: 336 000222B3 # writes(", data index = ");
349: 337 000222B3 .data 1
350: 338 00000b27 * L264:
351: 339 00000b27 * 2C20206461746120696E64657 .ascii ", data index = \0"
352: 8203D2000
353: 340 00000b38 * .text
354: 341 000222B3 dd 8f00000b27 pushl $L264
355: 342 000222B9 fe 08 effffffd5c callf $8,_writes
356: 343 000222C0 # writed( index );
357: 344 000222C0 dd effffffd56 pushl _index
358: 345 000222C6 fe 08 effffffd4f callf $8,_writed
359: 346 000222CD # writec('\n');
360: 347 000222CD dd 0a pushl $10
361: 348 000222CF fe 08 effffffd46 callf $8,_writec
362: 349 000222D6 # writes(" Acc expected = ");
363: 350 000222D6 .data 1
364: 351 00000b38 * L265:
365: 352 00000b38 * 2020202020202020202020202 .ascii " Acc expected = \0"
366: 0202020202020202020416363
367: 206578706563746564203D200
368: 0
369: 353 00000b5e * .text
370: 354 000222D6 dd 8f00000b38 pushl $L265
371: 355 000222DC fe 08 effffffd39 callf $8,_writes
372: 356 000222E3 # write32h( sgl_expected );
373: 357 000222E3 dd effffffd33 pushl _sgl_expected
374: 358 000222E9 fe 08 effffffd2c callf $8,_write32h
375: 359 000222F0 # writec('\n');
376: 360 000222F0 dd 0a pushl $10
377: 361 000222F2 fe 08 effffffd23 callf $8,_writec
378: 362 000222F9 # }
379: 363 000222F9 # if ( halt_flg ) /* halt on error? */
380: 364 000222F9 L259:
381: 365 000222F9 5d effffffd1d tstl _halt_flg
382: 366 000222FF 31 09 jeql L266
383: 367 00022301 # sinf_er_halt( BAD_ACC_HLT );
384: 368 00022301 dd 01 pushl $1
385: 369 00022303 fe 08 ef000006c4 callf $8,_sinf_er_halt
386: 370 0002230A # if ( loop_on_err )
387: 371 0002230A L266:
388: 372 0002230A 5d effffffd0c tstl _loop_on_err
389: 373 00022310 31 0d jeql L267
390: 374 00022312 # {
391: 375 00022312 # force_loop = TRUE; /* set the force loop flag */
392: 376 00022312 0d 01 effffffd03 movl $1,_force_loop
393: 377 00022319 # asm("jmp _sinf_2_lp1"); /* and loop */
394: 378 00022319 71 efffffff01 jmp _sinf_2_lp1
395: 379 0002231F # }
396: 380 0002231F # } /* end of compare error */
397: 381 0002231F L267:
398: 382 0002231F # } while( index++ < max_sinf_1_index );
399: 383 0002231F L258:
400: 384 0002231F L255:
401: 385 0002231F 0d effffffcf7 50 movl _index,r0
402: 386 00022326 6d effffffcf0 incl _index
403: 387 0002232C 1d 50 effffffce9 cmpl r0,_max_sinf_1_index
404: 388 00022333 81 03 13 febc jlss L256
405: 389 00022338 L254:
406: 390 00022338 # } /* end of subtest 2 */
407: 391 00022338 40 ret#2
408: 392 00022339 .set L250,0x0
409: 393 00022339 L252:
410: 394 00022339 13 fea5 jbr L253
411: 395 0002233C .data
412: 396 00000a5c * .text
413: 397 0002233C .align 1
414: 398 0002233C .globl _sinf_3
415: 399 0002233C _sinf_3:
416: 400 0002233C 0000 .word L268
417: 401 0002233E #
418: 402 0002233E #
419: 403 0002233E #
420: 404 0002233E # /***************************************************************************
421: 405 0002233E # *
422: 406 0002233E # * SUBTEST 3 - REGISTER INTEGRITY WITH THE SINF FUNCTION
423: 407 0002233E # *
424: 408 0002233E # ***************************************************************************/
425: 409 0002233E # sinf_3()
426: 410 0002233E # {
427: 411 0002233E 13 01e1 jbr L270
428: 412 00022341 L271:
429: 413 00022341 # fill_reg_buf( load_regs ); /* set reg values to load */
430: 414 00022341 dd 8f00000000 pushl $_load_regs
431: 415 00022347 fe 08 effffffcce callf $8,_fill_reg_buf
432: 416 0002234E # force_loop = FALSE; /* clear the LOOP flag */
433: 417 0002234E 4d effffffcc8 clrl _force_loop
434: 418 00022354 # subtest = 3;
435: 419 00022354 0d 03 effffffcc1 movl $3,_subtest
436: 420 0002235B # index = 0;
437: 421 0002235B 4d effffffcbb clrl _index
438: 422 00022361 # do
439: 423 00022361 L275:
440: 424 00022361 # {
441: 425 00022361 # sgl_ld_acc = sinf_1_data[index].ld; /* get the operand */
442: 426 00022361 0d effffffcb5 50 movl _index,r0
443: 427 00022368 48 03 50 50 shll $3,r0,r0
444: 428 0002236C 0d e000000000 effffffca5 movl _sinf_1_data(r0),_sgl_ld_acc
445: 429 00022377 # sgl_expected = sinf_1_data[index].exp; /* get expected results */
446: 430 00022377 0d effffffc9f 50 movl _index,r0
447: 431 0002237E 48 03 50 50 shll $3,r0,r0
448: 432 00022382 0d e000000004 effffffc8f movl _sinf_1_data+4(r0),_sgl_expected
449: 433 0002238D # /*
450: 434 0002238D # * If LOOP ON ERROR is set, this is the loop for this subtest.
451: 435 0002238D # * The force loop flag is set after the first error.
452: 436 0002238D # */
453: 437 0002238D # asm("_sinf_3_lp1:");
454: 438 0002238D _sinf_3_lp1:
455: 439 0002238D # asm("loadr $0x1fff,_load_regs"); /* load regs 0 - 12 */
456: 440 0002238D ab 891fff effffffc86 loadr $0x1fff,_load_regs
457: 441 00022396 # asm("ldf _sgl_ld_acc"); /* load the accumulator */
458: 442 00022396 06 effffffc80 ldf _sgl_ld_acc
459: 443 0002239C # asm("sinf"); /* get ACC.'s sine */
460: 444 0002239C 05 sinf
461: 445 0002239D # asm("stf _sgl_st_acc"); /* store the result */
462: 446 0002239D 26 effffffc79 stf _sgl_st_acc
463: 447 000223A3 # asm("storer $0x1fff,_store_regs"); /* store regs 0 - 12 */
464: 448 000223A3 bb 891fff effffffc70 storer $0x1fff,_store_regs
465: 449 000223AC # if( force_loop )
466: 450 000223AC 5d effffffc6a tstl _force_loop
467: 451 000223B2 31 02 jeql L276
468: 452 000223B4 # asm("brb _sinf_3_lp1");; /* loop on the error */
469: 453 000223B4 11 d7 brb _sinf_3_lp1
470: 454 000223B6 L276:
471: 455 000223B6 # /*
472: 456 000223B6 # * end error loop
473: 457 000223B6 # */
474: 458 000223B6 # reg_no = 0;
475: 459 000223B6 4d effffffc60 clrl _reg_no
476: 460 000223BC # regs_ok = TRUE;
477: 461 000223BC 0d 01 effffffc59 movl $1,_regs_ok
478: 462 000223C3 # while( (reg_no < 13) && (regs_ok) ) /* check 1st 12 regs */
479: 463 000223C3 L277:
480: 464 000223C3 1d effffffc53 0d cmpl _reg_no,$13
481: 465 000223CA 81 35 jgeq L278
482: 466 000223CC 5d effffffc4a tstl _regs_ok
483: 467 000223D2 31 2d jeql L278
484: 468 000223D4 # if( store_regs[ reg_no ] == load_regs[ reg_no ] )
485: 469 000223D4 0d effffffc42 50 movl _reg_no,r0
486: 470 000223DB 0d effffffc3b 51 movl _reg_no,r1
487: 471 000223E2 1d 40effffffc33 cmpl _store_regs[r0],_load_regs[r1]
488: 41effffffc2d
489: 472 000223EF 21 08 jneq L279
490: 473 000223F1 # reg_no++;
491: 474 000223F1 6d effffffc25 incl _reg_no
492: 475 000223F7 # else
493: 476 000223F7 11 06 jbr L280
494: 477 000223F9 L279:
495: 478 000223F9 # regs_ok = FALSE;
496: 479 000223F9 4d effffffc1d clrl _regs_ok
497: 480 000223FF L280:
498: 481 000223FF 11 c2 jbr L277
499: 482 00022401 L278:
500: 483 00022401 # if( !regs_ok ) {
501: 484 00022401 5d effffffc15 tstl _regs_ok
502: 485 00022407 31 03 13 00fc jneq L281
503: 486 0002240C # errcnt++; /* bump the error count */
504: 487 0002240C 6d effffffc0a incl _errcnt
505: 488 00022412 # if ( prt_error ) {
506: 489 00022412 5d effffffc04 tstl _prt_error
507: 490 00022418 21 03 13 00eb jeql L282
508: 491 0002241D # writes(" \n"); /* start a new print line */
509: 492 0002241D .data 1
510: 493 00000b5e * L283:
511: 494 00000b5e * 200A00 .ascii " \12\0"
512: 495 00000b61 * .text
513: 496 0002241D dd 8f00000b5e pushl $L283
514: 497 00022423 fe 08 effffffbf2 callf $8,_writes
515: 498 0002242A # writes("cycle: ");
516: 499 0002242A .data 1
517: 500 00000b61 * L284:
518: 501 00000b61 * 6379636C653A2000 .ascii "cycle: \0"
519: 502 00000b69 * .text
520: 503 0002242A dd 8f00000b61 pushl $L284
521: 504 00022430 fe 08 effffffbe5 callf $8,_writes
522: 505 00022437 # writed( cycle );
523: 506 00022437 dd effffffbdf pushl _cycle
524: 507 0002243D fe 08 effffffbd8 callf $8,_writed
525: 508 00022444 # writes(" SINF test ");
526: 509 00022444 .data 1
527: 510 00000b69 * L285:
528: 511 00000b69 * 20202053494E4620746573742 .ascii " SINF test \0"
529: 000
530: 512 00000b77 * .text
531: 513 00022444 dd 8f00000b69 pushl $L285
532: 514 0002244A fe 08 effffffbcb callf $8,_writes
533: 515 00022451 # writed( test_no );
534: 516 00022451 dd effffffbc5 pushl _test_no
535: 517 00022457 fe 08 effffffbbe callf $8,_writed
536: 518 0002245E # writes(", subtest 3 - A REGISTER WAS MODIFIED\n"); {
537: 519 0002245E .data 1
538: 520 00000b77 * L286:
539: 521 00000b77 * 2C20737562746573742033202 .ascii ", subtest 3 - A REGISTER WAS MODIFIED\12\0"
540: D204120524547495354455220
541: 574153204D4F4449464945440
542: A00
543: 522 00000b9e * .text
544: 523 0002245E dd 8f00000b77 pushl $L286
545: 524 00022464 fe 08 effffffbb1 callf $8,_writes
546: 525 0002246B # print_sinf_data();
547: 526 0002246B fe 04 ef00000520 callf $4,_print_sinf_data
548: 527 00022472 # writec('\n');
549: 528 00022472 dd 0a pushl $10
550: 529 00022474 fe 08 effffffba1 callf $8,_writec
551: 530 0002247B # writes("register ");
552: 531 0002247B .data 1
553: 532 00000b9e * L287:
554: 533 00000b9e * 72656769737465722000 .ascii "register \0"
555: 534 00000ba8 * .text
556: 535 0002247B dd 8f00000b9e pushl $L287
557: 536 00022481 fe 08 effffffb94 callf $8,_writes
558: 537 00022488 # writed( reg_no );
559: 538 00022488 dd effffffb8e pushl _reg_no
560: 539 0002248E fe 08 effffffb87 callf $8,_writed
561: 540 00022495 # writes(" = ");
562: 541 00022495 .data 1
563: 542 00000ba8 * L288:
564: 543 00000ba8 * 203D2000 .ascii " = \0"
565: 544 00000bac * .text
566: 545 00022495 dd 8f00000ba8 pushl $L288
567: 546 0002249B fe 08 effffffb7a callf $8,_writes
568: 547 000224A2 # write32h( load_regs[reg_no] );
569: 548 000224A2 0d effffffb74 50 movl _reg_no,r0
570: 549 000224A9 dd 40effffffb6c pushl _load_regs[r0]
571: 550 000224B0 fe 08 effffffb65 callf $8,_write32h
572: 551 000224B7 # writes(", should be = ");
573: 552 000224B7 .data 1
574: 553 00000bac * L289:
575: 554 00000bac * 2C202073686F756C642062652 .ascii ", should be = \0"
576: 03D2000
577: 555 00000bbc * .text
578: 556 000224B7 dd 8f00000bac pushl $L289
579: 557 000224BD fe 08 effffffb58 callf $8,_writes
580: 558 000224C4 # write32h( store_regs[reg_no] );
581: 559 000224C4 0d effffffb52 50 movl _reg_no,r0
582: 560 000224CB dd 40effffffb4a pushl _store_regs[r0]
583: 561 000224D2 fe 08 effffffb43 callf $8,_write32h
584: 562 000224D9 # writec('\n');
585: 563 000224D9 dd 0a pushl $10
586: 564 000224DB fe 08 effffffb3a callf $8,_writec
587: 565 000224E2 # }
588: 566 000224E2 # if ( halt_flg ) /* halt on error? */
589: 567 000224E2 5d effffffb34 tstl _halt_flg
590: 568 000224E8 31 09 jeql L290
591: 569 000224EA # sinf_er_halt( BAD_REG_HLT );
592: 570 000224EA dd 02 pushl $2
593: 571 000224EC fe 08 ef000004db callf $8,_sinf_er_halt
594: 572 000224F3 # if ( loop_on_err )
595: 573 000224F3 L290:
596: 574 000224F3 5d effffffb23 tstl _loop_on_err
597: 575 000224F9 31 0d jeql L291
598: 576 000224FB # {
599: 577 000224FB # force_loop = TRUE; /* get the force loop flag */
600: 578 000224FB 0d 01 effffffb1a movl $1,_force_loop
601: 579 00022502 # asm("jmp _sinf_3_lp1"); /* and loop */
602: 580 00022502 71 effffffe85 jmp _sinf_3_lp1
603: 581 00022508 # }
604: 582 00022508 # } /* end of compare error */
605: 583 00022508 L291:
606: 584 00022508 # } /* end of while loop */
607: 585 00022508 L282:
608: 586 00022508 # } while( index++ < max_sinf_1_index );
609: 587 00022508 L281:
610: 588 00022508 L274:
611: 589 00022508 0d effffffb0e 50 movl _index,r0
612: 590 0002250F 6d effffffb07 incl _index
613: 591 00022515 1d 50 effffffb00 cmpl r0,_max_sinf_1_index
614: 592 0002251C 81 03 13 fe40 jlss L275
615: 593 00022521 L273:
616: 594 00022521 # } /* end of subtest 3 */
617: 595 00022521 40 ret#2
618: 596 00022522 .set L268,0x0
619: 597 00022522 L270:
620: 598 00022522 13 fe1c jbr L271
621: 599 00022525 .data
622: 600 00000a5c * .text
623: 601 00022525 00 .align 1
624: 602 00022526 .globl _sinf_4
625: 603 00022526 _sinf_4:
626: 604 00022526 0000 .word L293
627: 605 00022528 #
628: 606 00022528 #
629: 607 00022528 #
630: 608 00022528 # /************************************************************************
631: 609 00022528 # *
632: 610 00022528 # * SUBTEST 4 - Check for PSL corruption
633: 611 00022528 # *
634: 612 00022528 # ************************************************************************/
635: 613 00022528 # sinf_4()
636: 614 00022528 # {
637: 615 00022528 13 01ac jbr L295
638: 616 0002252B L296:
639: 617 0002252B # force_loop = FALSE; /* clear force_loop flg */
640: 618 0002252B 4d effffffaeb clrl _force_loop
641: 619 00022531 # subtest = 4;
642: 620 00022531 0d 04 effffffae4 movl $4,_subtest
643: 621 00022538 # fill_reg_buf( load_regs ); /* get patterns for regs */
644: 622 00022538 dd 8f00000000 pushl $_load_regs
645: 623 0002253E fe 08 effffffad7 callf $8,_fill_reg_buf
646: 624 00022545 # for( index = 0; index < 3; index++ ) {
647: 625 00022545 4d effffffad1 clrl _index
648: 626 0002254B L299:
649: 627 0002254B 1d effffffacb 03 cmpl _index,$3
650: 628 00022552 91 03 13 017f jgeq L298
651: 629 00022557 # sgl_ld_acc = sinf_1_data[index].ld; /* get operand 1 */
652: 630 00022557 0d effffffabf 50 movl _index,r0
653: 631 0002255E 48 03 50 50 shll $3,r0,r0
654: 632 00022562 0d e000000000 effffffaaf movl _sinf_1_data(r0),_sgl_ld_acc
655: 633 0002256D # sgl_expected = sinf_1_data[index].exp; /* get expected */
656: 634 0002256D 0d effffffaa9 50 movl _index,r0
657: 635 00022574 48 03 50 50 shll $3,r0,r0
658: 636 00022578 0d e000000004 effffffa99 movl _sinf_1_data+4(r0),_sgl_expected
659: 637 00022583 # sgl_dummy1 = status_array[status_index]; /* status = +, -, 0 */
660: 638 00022583 0d effffffa93 50 movl _status_index,r0
661: 639 0002258A 0d 40effffffa8b movl _status_array[r0],_sgl_dummy1
662: effffffa86
663: 640 00022596 # /*
664: 641 00022596 # * If LOOP ON ERROR is set, this is the loop for this subtest.
665: 642 00022596 # * The force loop flag is set after the first error.
666: 643 00022596 # */
667: 644 00022596 # asm("_sinf_4_lp1:");
668: 645 00022596 _sinf_4_lp1:
669: 646 00022596 # asm("ldf _sgl_ld_acc"); /* LOAD the accumulator */
670: 647 00022596 06 effffffa80 ldf _sgl_ld_acc
671: 648 0002259C # asm("nop");
672: 649 0002259C 10 nop
673: 650 0002259D # asm("tstl _sgl_dummy1"); /* set the PSL status */
674: 651 0002259D 5d effffffa79 tstl _sgl_dummy1
675: 652 000225A3 # asm("movpsl _init_psl"); /* save the initial PSL */
676: 653 000225A3 cd effffffa73 movpsl _init_psl
677: 654 000225A9 # asm("sinf"); /* do the sine */
678: 655 000225A9 05 sinf
679: 656 000225AA # asm("nop");
680: 657 000225AA 10 nop
681: 658 000225AB # asm("movpsl _psl_val"); /* save the final PSL */
682: 659 000225AB cd effffffa6b movpsl _psl_val
683: 660 000225B1 # asm("stf _sgl_st_acc"); /* save the accumulator */
684: 661 000225B1 26 effffffa65 stf _sgl_st_acc
685: 662 000225B7 # if( force_loop )
686: 663 000225B7 5d effffffa5f tstl _force_loop
687: 664 000225BD 31 02 jeql L300
688: 665 000225BF # asm("brb _sinf_4_lp1");; /* loop on the error */
689: 666 000225BF 11 d5 brb _sinf_4_lp1
690: 667 000225C1 L300:
691: 668 000225C1 # /*
692: 669 000225C1 # * Now compare the final PSL to the initial PSL -they should be the same
693: 670 000225C1 # */
694: 671 000225C1 # exp_psl = init_psl;
695: 672 000225C1 0d effffffa55 effffffa50 movl _init_psl,_exp_psl
696: 673 000225CC # if( psl_val != exp_psl ) {
697: 674 000225CC 1d effffffa4a effffffa45 cmpl _psl_val,_exp_psl
698: 675 000225D7 21 03 13 00f1 jeql L301
699: 676 000225DC # errcnt++; /* bump the error count */
700: 677 000225DC 6d effffffa3a incl _errcnt
701: 678 000225E2 # if( prt_error ) {
702: 679 000225E2 5d effffffa34 tstl _prt_error
703: 680 000225E8 21 03 13 00bd jeql L302
704: 681 000225ED # writes(" \n"); /* start a new print line */
705: 682 000225ED .data 1
706: 683 00000bbc * L303:
707: 684 00000bbc * 200A00 .ascii " \12\0"
708: 685 00000bbf * .text
709: 686 000225ED dd 8f00000bbc pushl $L303
710: 687 000225F3 fe 08 effffffa22 callf $8,_writes
711: 688 000225FA # writes("cycle: ");
712: 689 000225FA .data 1
713: 690 00000bbf * L304:
714: 691 00000bbf * 6379636C653A2000 .ascii "cycle: \0"
715: 692 00000bc7 * .text
716: 693 000225FA dd 8f00000bbf pushl $L304
717: 694 00022600 fe 08 effffffa15 callf $8,_writes
718: 695 00022607 # writed( cycle );
719: 696 00022607 dd effffffa0f pushl _cycle
720: 697 0002260D fe 08 effffffa08 callf $8,_writed
721: 698 00022614 # writes(" SINF test ");
722: 699 00022614 .data 1
723: 700 00000bc7 * L305:
724: 701 00000bc7 * 20202053494E4620746573742 .ascii " SINF test \0"
725: 000
726: 702 00000bd5 * .text
727: 703 00022614 dd 8f00000bc7 pushl $L305
728: 704 0002261A fe 08 effffff9fb callf $8,_writes
729: 705 00022621 # writed( test_no );
730: 706 00022621 dd effffff9f5 pushl _test_no
731: 707 00022627 fe 08 effffff9ee callf $8,_writed
732: 708 0002262E # writes(", subtest 4 - INCORRECT FINAL PSL\n");
733: 709 0002262E .data 1
734: 710 00000bd5 * L306:
735: 711 00000bd5 * 2C20737562746573742034202 .ascii ", subtest 4 - INCORRECT FINAL PSL\12\0"
736: D20494E434F52524543542046
737: 494E414C2050534C0A00
738: 712 00000bf8 * .text
739: 713 0002262E dd 8f00000bd5 pushl $L306
740: 714 00022634 fe 08 effffff9e1 callf $8,_writes
741: 715 0002263B # print_sinf_data(); /* print the operands */
742: 716 0002263B fe 04 ef00000350 callf $4,_print_sinf_data
743: 717 00022642 # writes("\n");
744: 718 00022642 .data 1
745: 719 00000bf8 * L307:
746: 720 00000bf8 * 0A00 .ascii "\12\0"
747: 721 00000bfa * .text
748: 722 00022642 dd 8f00000bf8 pushl $L307
749: 723 00022648 fe 08 effffff9cd callf $8,_writes
750: 724 0002264F # writes("initial PSL = ");
751: 725 0002264F .data 1
752: 726 00000bfa * L308:
753: 727 00000bfa * 696E697469616C2050534C203 .ascii "initial PSL = \0"
754: D2000
755: 728 00000c09 * .text
756: 729 0002264F dd 8f00000bfa pushl $L308
757: 730 00022655 fe 08 effffff9c0 callf $8,_writes
758: 731 0002265C # write32h( init_psl );
759: 732 0002265C dd effffff9ba pushl _init_psl
760: 733 00022662 fe 08 effffff9b3 callf $8,_write32h
761: 734 00022669 # writes(", final PSL = ");
762: 735 00022669 .data 1
763: 736 00000c09 * L309:
764: 737 00000c09 * 2C202066696E616C2050534C2 .ascii ", final PSL = \0"
765: 03D2000
766: 738 00000c19 * .text
767: 739 00022669 dd 8f00000c09 pushl $L309
768: 740 0002266F fe 08 effffff9a6 callf $8,_writes
769: 741 00022676 # write32h( psl_val );
770: 742 00022676 dd effffff9a0 pushl _psl_val
771: 743 0002267C fe 08 effffff999 callf $8,_write32h
772: 744 00022683 # writes(", expected PSL = ");
773: 745 00022683 .data 1
774: 746 00000c19 * L310:
775: 747 00000c19 * 2C20206578706563746564205 .ascii ", expected PSL = \0"
776: 0534C203D2000
777: 748 00000c2c * .text
778: 749 00022683 dd 8f00000c19 pushl $L310
779: 750 00022689 fe 08 effffff98c callf $8,_writes
780: 751 00022690 # write32h( exp_psl );
781: 752 00022690 dd effffff986 pushl _exp_psl
782: 753 00022696 fe 08 effffff97f callf $8,_write32h
783: 754 0002269D # writes("\n");
784: 755 0002269D .data 1
785: 756 00000c2c * L311:
786: 757 00000c2c * 0A00 .ascii "\12\0"
787: 758 00000c2e * .text
788: 759 0002269D dd 8f00000c2c pushl $L311
789: 760 000226A3 fe 08 effffff972 callf $8,_writes
790: 761 000226AA # }
791: 762 000226AA # if( halt_flg )
792: 763 000226AA L302:
793: 764 000226AA 5d effffff96c tstl _halt_flg
794: 765 000226B0 31 09 jeql L312
795: 766 000226B2 # sinf_er_halt( BAD_PSL_HLT ); /* halt on the error */
796: 767 000226B2 dd 03 pushl $3
797: 768 000226B4 fe 08 ef00000313 callf $8,_sinf_er_halt
798: 769 000226BB # if( loop_on_err ) {
799: 770 000226BB L312:
800: 771 000226BB 5d effffff95b tstl _loop_on_err
801: 772 000226C1 31 0a jeql L313
802: 773 000226C3 # force_loop = TRUE; /* set the force loop flag */
803: 774 000226C3 0d 01 effffff952 movl $1,_force_loop
804: 775 000226CA # asm("brw _sinf_4_lp1");; /* and loop on the error */
805: 776 000226CA 13 fec9 brw _sinf_4_lp1
806: 777 000226CD # } /* end of loop on error */
807: 778 000226CD # } /* end of PSL corruption error */
808: 779 000226CD L313:
809: 780 000226CD # } /* end of WHILE loop */
810: 781 000226CD L301:
811: 782 000226CD L297:
812: 783 000226CD 6d effffff949 incl _index
813: 784 000226D3 13 fe75 jbr L299
814: 785 000226D6 L298:
815: 786 000226D6 # } /* end of subtest 4 */
816: 787 000226D6 40 ret#2
817: 788 000226D7 .set L293,0x0
818: 789 000226D7 L295:
819: 790 000226D7 13 fe51 jbr L296
820: 791 000226DA .data
821: 792 00000a5c * .text
822: 793 000226DA .align 1
823: 794 000226DA .globl _sinf_5
824: 795 000226DA _sinf_5:
825: 796 000226DA 0000 .word L314
826: 797 000226DC #
827: 798 000226DC #
828: 799 000226DC #
829: 800 000226DC # /************************************************************************
830: 801 000226DC # *
831: 802 000226DC # * SUBTEST 5 - pipelined entry test
832: 803 000226DC # *
833: 804 000226DC # ************************************************************************/
834: 805 000226DC # sinf_5()
835: 806 000226DC # {
836: 807 000226DC 13 0154 jbr L316
837: 808 000226DF L317:
838: 809 000226DF # force_loop = FALSE;
839: 810 000226DF 4d effffff937 clrl _force_loop
840: 811 000226E5 # subtest = 8;
841: 812 000226E5 0d 08 effffff930 movl $8,_subtest
842: 813 000226EC # for( index = 0; index < max_sinf_1_index; index++ ) {
843: 814 000226EC 4d effffff92a clrl _index
844: 815 000226F2 L320:
845: 816 000226F2 1d effffff924 effffff91f cmpl _index,_max_sinf_1_index
846: 817 000226FD 91 03 13 0130 jgeq L319
847: 818 00022702 # sgl_ld_acc = sinf_1_data[index].ld; /* get operand 1 */
848: 819 00022702 0d effffff914 50 movl _index,r0
849: 820 00022709 48 03 50 50 shll $3,r0,r0
850: 821 0002270D 0d e000000000 effffff904 movl _sinf_1_data(r0),_sgl_ld_acc
851: 822 00022718 # sgl_expected = sinf_1_data[index].exp; /* get expected result */
852: 823 00022718 0d effffff8fe 50 movl _index,r0
853: 824 0002271F 48 03 50 50 shll $3,r0,r0
854: 825 00022723 0d e000000004 effffff8ee movl _sinf_1_data+4(r0),_sgl_expected
855: 826 0002272E # /*
856: 827 0002272E # * If LOOP ON ERROR is set, this is the loop for this subtest.
857: 828 0002272E # * The force loop flag is set after the first error.
858: 829 0002272E # */
859: 830 0002272E # asm("_sinf_5_lp1:");
860: 831 0002272E _sinf_5_lp1:
861: 832 0002272E # asm("movl $0,r0"); /* clear r0 */
862: 833 0002272E 0d 00 50 movl $0,r0
863: 834 00022731 # asm("ldf r0"); /* load the Acc. with 0.0 */
864: 835 00022731 06 50 ldf r0
865: 836 00022733 # asm("addf _sgl_ld_acc"); /* add the 1st operand */
866: 837 00022733 c6 effffff8e3 addf _sgl_ld_acc
867: 838 00022739 # asm("sinf"); /* get the sine */
868: 839 00022739 05 sinf
869: 840 0002273A # asm("stf _sgl_st_acc"); /* store the result */
870: 841 0002273A 26 effffff8dc stf _sgl_st_acc
871: 842 00022740 # if( force_loop )
872: 843 00022740 5d effffff8d6 tstl _force_loop
873: 844 00022746 31 02 jeql L321
874: 845 00022748 # asm("brb _sinf_5_lp1");; /* loop on the error */
875: 846 00022748 11 e4 brb _sinf_5_lp1
876: 847 0002274A L321:
877: 848 0002274A # /*
878: 849 0002274A # * end error loop - test the results
879: 850 0002274A # */
880: 851 0002274A # if( sgl_st_acc != sgl_expected ) { /* COMPARE the values */
881: 852 0002274A 1d effffff8cc effffff8c7 cmpl _sgl_st_acc,_sgl_expected
882: 853 00022755 21 03 13 00cf jeql L322
883: 854 0002275A # errcnt++; /* bump the error count */
884: 855 0002275A 6d effffff8bc incl _errcnt
885: 856 00022760 # if( prt_error ) {
886: 857 00022760 5d effffff8b6 tstl _prt_error
887: 858 00022766 21 03 13 009b jeql L323
888: 859 0002276B # writes(" \n"); /* start a new print line */
889: 860 0002276B .data 1
890: 861 00000c2e * L324:
891: 862 00000c2e * 200A00 .ascii " \12\0"
892: 863 00000c31 * .text
893: 864 0002276B dd 8f00000c2e pushl $L324
894: 865 00022771 fe 08 effffff8a4 callf $8,_writes
895: 866 00022778 # writes("cycle: ");
896: 867 00022778 .data 1
897: 868 00000c31 * L325:
898: 869 00000c31 * 6379636C653A2000 .ascii "cycle: \0"
899: 870 00000c39 * .text
900: 871 00022778 dd 8f00000c31 pushl $L325
901: 872 0002277E fe 08 effffff897 callf $8,_writes
902: 873 00022785 # writed( cycle );
903: 874 00022785 dd effffff891 pushl _cycle
904: 875 0002278B fe 08 effffff88a callf $8,_writed
905: 876 00022792 # writes(" SINF test ");
906: 877 00022792 .data 1
907: 878 00000c39 * L326:
908: 879 00000c39 * 20202053494E4620746573742 .ascii " SINF test \0"
909: 000
910: 880 00000c47 * .text
911: 881 00022792 dd 8f00000c39 pushl $L326
912: 882 00022798 fe 08 effffff87d callf $8,_writes
913: 883 0002279F # writed( test_no );
914: 884 0002279F dd effffff877 pushl _test_no
915: 885 000227A5 fe 08 effffff870 callf $8,_writed
916: 886 000227AC # writes(", subtest 5 (Piped Entry) - BAD FINAL ACC\n");
917: 887 000227AC .data 1
918: 888 00000c47 * L327:
919: 889 00000c47 * 2C20737562746573742035202 .ascii ", subtest 5 (Piped Entry) - BAD FINAL ACC\12\0"
920: 8506970656420456E74727929
921: 202D204241442046494E414C2
922: 04143430A00
923: 890 00000c72 * .text
924: 891 000227AC dd 8f00000c47 pushl $L327
925: 892 000227B2 fe 08 effffff863 callf $8,_writes
926: 893 000227B9 # print_sinf_data();
927: 894 000227B9 fe 04 ef000001d2 callf $4,_print_sinf_data
928: 895 000227C0 # writes(", data index = ");
929: 896 000227C0 .data 1
930: 897 00000c72 * L328:
931: 898 00000c72 * 2C20206461746120696E64657 .ascii ", data index = \0"
932: 8203D2000
933: 899 00000c83 * .text
934: 900 000227C0 dd 8f00000c72 pushl $L328
935: 901 000227C6 fe 08 effffff84f callf $8,_writes
936: 902 000227CD # writed( index );
937: 903 000227CD dd effffff849 pushl _index
938: 904 000227D3 fe 08 effffff842 callf $8,_writed
939: 905 000227DA # writec('\n');
940: 906 000227DA dd 0a pushl $10
941: 907 000227DC fe 08 effffff839 callf $8,_writec
942: 908 000227E3 # writes(" Acc expected = ");
943: 909 000227E3 .data 1
944: 910 00000c83 * L329:
945: 911 00000c83 * 2020202020202020202020202 .ascii " Acc expected = \0"
946: 0202020202020202020416363
947: 206578706563746564203D200
948: 0
949: 912 00000ca9 * .text
950: 913 000227E3 dd 8f00000c83 pushl $L329
951: 914 000227E9 fe 08 effffff82c callf $8,_writes
952: 915 000227F0 # write32h( sgl_expected );
953: 916 000227F0 dd effffff826 pushl _sgl_expected
954: 917 000227F6 fe 08 effffff81f callf $8,_write32h
955: 918 000227FD # writec('\n');
956: 919 000227FD dd 0a pushl $10
957: 920 000227FF fe 08 effffff816 callf $8,_writec
958: 921 00022806 # }
959: 922 00022806 # if( halt_flg )
960: 923 00022806 L323:
961: 924 00022806 5d effffff810 tstl _halt_flg
962: 925 0002280C 31 09 jeql L330
963: 926 0002280E # sinf_er_halt( BAD_ACC_HLT ); /* halt on the error */
964: 927 0002280E dd 01 pushl $1
965: 928 00022810 fe 08 ef000001b7 callf $8,_sinf_er_halt
966: 929 00022817 # if( loop_on_err ) {
967: 930 00022817 L330:
968: 931 00022817 5d effffff7ff tstl _loop_on_err
969: 932 0002281D 31 0a jeql L331
970: 933 0002281F # force_loop = TRUE; /* set the force loop flag */
971: 934 0002281F 0d 01 effffff7f6 movl $1,_force_loop
972: 935 00022826 # asm("brw _sinf_5_lp1");; /* and loop on the error */
973: 936 00022826 13 ff05 brw _sinf_5_lp1
974: 937 00022829 # } /* end of loop on error */
975: 938 00022829 # } /* end of compare error */
976: 939 00022829 L331:
977: 940 00022829 # } /* end of WHILE loop */
978: 941 00022829 L322:
979: 942 00022829 L318:
980: 943 00022829 6d effffff7ed incl _index
981: 944 0002282F 13 fec0 jbr L320
982: 945 00022832 L319:
983: 946 00022832 # } /* end of subtest 5 */
984: 947 00022832 40 ret#2
985: 948 00022833 .set L314,0x0
986: 949 00022833 L316:
987: 950 00022833 13 fea9 jbr L317
988: 951 00022836 .data
989: 952 00000a5c * .text
990: 953 00022836 .align 1
991: 954 00022836 .globl _sinf_6
992: 955 00022836 _sinf_6:
993: 956 00022836 0000 .word L332
994: 957 00022838 #
995: 958 00022838 #
996: 959 00022838 #
997: 960 00022838 # /************************************************************************
998: 961 00022838 # *
999: 962 00022838 # * SUBTEST 6 - pipelined exit test
1000: 963 00022838 # *
1001: 964 00022838 # ************************************************************************/
1002: 965 00022838 # sinf_6()
1003: 966 00022838 # {
1004: 967 00022838 13 0154 jbr L334
1005: 968 0002283B L335:
1006: 969 0002283B # force_loop = FALSE;
1007: 970 0002283B 4d effffff7db clrl _force_loop
1008: 971 00022841 # subtest = 8;
1009: 972 00022841 0d 08 effffff7d4 movl $8,_subtest
1010: 973 00022848 # for( index = 0; index < max_sinf_1_index; index++ ) {
1011: 974 00022848 4d effffff7ce clrl _index
1012: 975 0002284E L338:
1013: 976 0002284E 1d effffff7c8 effffff7c3 cmpl _index,_max_sinf_1_index
1014: 977 00022859 91 03 13 0130 jgeq L337
1015: 978 0002285E # sgl_ld_acc = sinf_1_data[index].ld; /* get operand 1 */
1016: 979 0002285E 0d effffff7b8 50 movl _index,r0
1017: 980 00022865 48 03 50 50 shll $3,r0,r0
1018: 981 00022869 0d e000000000 effffff7a8 movl _sinf_1_data(r0),_sgl_ld_acc
1019: 982 00022874 # sgl_expected = sinf_1_data[index].exp; /* get expected result */
1020: 983 00022874 0d effffff7a2 50 movl _index,r0
1021: 984 0002287B 48 03 50 50 shll $3,r0,r0
1022: 985 0002287F 0d e000000004 effffff792 movl _sinf_1_data+4(r0),_sgl_expected
1023: 986 0002288A # /*
1024: 987 0002288A # * If LOOP ON ERROR is set, this is the loop for this subtest.
1025: 988 0002288A # * The force loop flag is set after the first error.
1026: 989 0002288A # */
1027: 990 0002288A # asm("_sinf_6_lp1:");
1028: 991 0002288A _sinf_6_lp1:
1029: 992 0002288A # asm("movl $0,r0"); /* clear r0 */
1030: 993 0002288A 0d 00 50 movl $0,r0
1031: 994 0002288D # asm("ldf _sgl_ld_acc"); /* load the Acc. */
1032: 995 0002288D 06 effffff789 ldf _sgl_ld_acc
1033: 996 00022893 # asm("sinf"); /* get the sine */
1034: 997 00022893 05 sinf
1035: 998 00022894 # asm("addf r0"); /* add a zero to the acc */
1036: 999 00022894 c6 50 addf r0
1037: 1000 00022896 # asm("stf _sgl_st_acc"); /* store the result */
1038: 1001 00022896 26 effffff780 stf _sgl_st_acc
1039: 1002 0002289C # if( force_loop )
1040: 1003 0002289C 5d effffff77a tstl _force_loop
1041: 1004 000228A2 31 02 jeql L339
1042: 1005 000228A4 # asm("brb _sinf_6_lp1");; /* loop on the error */
1043: 1006 000228A4 11 e4 brb _sinf_6_lp1
1044: 1007 000228A6 L339:
1045: 1008 000228A6 # /*
1046: 1009 000228A6 # * end error loop - test the results
1047: 1010 000228A6 # */
1048: 1011 000228A6 # if( sgl_st_acc != sgl_expected ) { /* COMPARE the values */
1049: 1012 000228A6 1d effffff770 effffff76b cmpl _sgl_st_acc,_sgl_expected
1050: 1013 000228B1 21 03 13 00cf jeql L340
1051: 1014 000228B6 # errcnt++; /* bump the error count */
1052: 1015 000228B6 6d effffff760 incl _errcnt
1053: 1016 000228BC # if( prt_error ) {
1054: 1017 000228BC 5d effffff75a tstl _prt_error
1055: 1018 000228C2 21 03 13 009b jeql L341
1056: 1019 000228C7 # writes(" \n"); /* start a new print line */
1057: 1020 000228C7 .data 1
1058: 1021 00000ca9 * L342:
1059: 1022 00000ca9 * 200A00 .ascii " \12\0"
1060: 1023 00000cac * .text
1061: 1024 000228C7 dd 8f00000ca9 pushl $L342
1062: 1025 000228CD fe 08 effffff748 callf $8,_writes
1063: 1026 000228D4 # writes("cycle: ");
1064: 1027 000228D4 .data 1
1065: 1028 00000cac * L343:
1066: 1029 00000cac * 6379636C653A2000 .ascii "cycle: \0"
1067: 1030 00000cb4 * .text
1068: 1031 000228D4 dd 8f00000cac pushl $L343
1069: 1032 000228DA fe 08 effffff73b callf $8,_writes
1070: 1033 000228E1 # writed( cycle );
1071: 1034 000228E1 dd effffff735 pushl _cycle
1072: 1035 000228E7 fe 08 effffff72e callf $8,_writed
1073: 1036 000228EE # writes(" SINF test ");
1074: 1037 000228EE .data 1
1075: 1038 00000cb4 * L344:
1076: 1039 00000cb4 * 20202053494E4620746573742 .ascii " SINF test \0"
1077: 000
1078: 1040 00000cc2 * .text
1079: 1041 000228EE dd 8f00000cb4 pushl $L344
1080: 1042 000228F4 fe 08 effffff721 callf $8,_writes
1081: 1043 000228FB # writed( test_no );
1082: 1044 000228FB dd effffff71b pushl _test_no
1083: 1045 00022901 fe 08 effffff714 callf $8,_writed
1084: 1046 00022908 # writes(", subtest 6 (Piped Exit) - BAD FINAL ACC\n");
1085: 1047 00022908 .data 1
1086: 1048 00000cc2 * L345:
1087: 1049 00000cc2 * 2C20737562746573742036202 .ascii ", subtest 6 (Piped Exit) - BAD FINAL ACC\12\0"
1088: 8506970656420457869742920
1089: 2D204241442046494E414C204
1090: 143430A00
1091: 1050 00000cec * .text
1092: 1051 00022908 dd 8f00000cc2 pushl $L345
1093: 1052 0002290E fe 08 effffff707 callf $8,_writes
1094: 1053 00022915 # print_sinf_data();
1095: 1054 00022915 fe 04 ef00000076 callf $4,_print_sinf_data
1096: 1055 0002291C # writes(", data index = ");
1097: 1056 0002291C .data 1
1098: 1057 00000cec * L346:
1099: 1058 00000cec * 2C20206461746120696E64657 .ascii ", data index = \0"
1100: 8203D2000
1101: 1059 00000cfd * .text
1102: 1060 0002291C dd 8f00000cec pushl $L346
1103: 1061 00022922 fe 08 effffff6f3 callf $8,_writes
1104: 1062 00022929 # writed( index );
1105: 1063 00022929 dd effffff6ed pushl _index
1106: 1064 0002292F fe 08 effffff6e6 callf $8,_writed
1107: 1065 00022936 # writec('\n');
1108: 1066 00022936 dd 0a pushl $10
1109: 1067 00022938 fe 08 effffff6dd callf $8,_writec
1110: 1068 0002293F # writes(" Acc expected = ");
1111: 1069 0002293F .data 1
1112: 1070 00000cfd * L347:
1113: 1071 00000cfd * 2020202020202020202020202 .ascii " Acc expected = \0"
1114: 0202020202020202020416363
1115: 206578706563746564203D200
1116: 0
1117: 1072 00000d23 * .text
1118: 1073 0002293F dd 8f00000cfd pushl $L347
1119: 1074 00022945 fe 08 effffff6d0 callf $8,_writes
1120: 1075 0002294C # write32h( sgl_expected );
1121: 1076 0002294C dd effffff6ca pushl _sgl_expected
1122: 1077 00022952 fe 08 effffff6c3 callf $8,_write32h
1123: 1078 00022959 # writec('\n');
1124: 1079 00022959 dd 0a pushl $10
1125: 1080 0002295B fe 08 effffff6ba callf $8,_writec
1126: 1081 00022962 # }
1127: 1082 00022962 # if( halt_flg )
1128: 1083 00022962 L341:
1129: 1084 00022962 5d effffff6b4 tstl _halt_flg
1130: 1085 00022968 31 09 jeql L348
1131: 1086 0002296A # sinf_er_halt( BAD_ACC_HLT ); /* halt on the error */
1132: 1087 0002296A dd 01 pushl $1
1133: 1088 0002296C fe 08 ef0000005b callf $8,_sinf_er_halt
1134: 1089 00022973 # if( loop_on_err ) {
1135: 1090 00022973 L348:
1136: 1091 00022973 5d effffff6a3 tstl _loop_on_err
1137: 1092 00022979 31 0a jeql L349
1138: 1093 0002297B # force_loop = TRUE; /* set the force loop flag */
1139: 1094 0002297B 0d 01 effffff69a movl $1,_force_loop
1140: 1095 00022982 # asm("brw _sinf_6_lp1");; /* and loop on the error */
1141: 1096 00022982 13 ff05 brw _sinf_6_lp1
1142: 1097 00022985 # } /* end of loop on error */
1143: 1098 00022985 # } /* end of compare error */
1144: 1099 00022985 L349:
1145: 1100 00022985 # } /* end of WHILE loop */
1146: 1101 00022985 L340:
1147: 1102 00022985 L336:
1148: 1103 00022985 6d effffff691 incl _index
1149: 1104 0002298B 13 fec0 jbr L338
1150: 1105 0002298E L337:
1151: 1106 0002298E # } /* end of subtest 6 */
1152: 1107 0002298E 40 ret#2
1153: 1108 0002298F .set L332,0x0
1154: 1109 0002298F L334:
1155: 1110 0002298F 13 fea9 jbr L335
1156: 1111 00022992 .data
1157: 1112 00000a5c * .text
1158: 1113 00022992 .align 1
1159: 1114 00022992 .globl _print_sinf_data
1160: 1115 00022992 _print_sinf_data:
1161: 1116 00022992 0000 .word L350
1162: 1117 00022994 #
1163: 1118 00022994 #
1164: 1119 00022994 # /**************************************************************************
1165: 1120 00022994 # *
1166: 1121 00022994 # * PRINT THE DATA AND STORE RESULTS
1167: 1122 00022994 # *
1168: 1123 00022994 # * initial Acc = xxxxxxxx, stored = xxxxxxxx, data index = xx
1169: 1124 00022994 # * Acc expected = xxxxxxxx
1170: 1125 00022994 # **************************************************************************/
1171: 1126 00022994 # print_sinf_data()
1172: 1127 00022994 # {
1173: 1128 00022994 11 35 jbr L352
1174: 1129 00022996 L353:
1175: 1130 00022996 # writes("initial Acc = ");
1176: 1131 00022996 .data 1
1177: 1132 00000d23 * L354:
1178: 1133 00000d23 * 696E697469616C20416363203 .ascii "initial Acc = \0"
1179: D2000
1180: 1134 00000d32 * .text
1181: 1135 00022996 dd 8f00000d23 pushl $L354
1182: 1136 0002299C fe 08 effffff679 callf $8,_writes
1183: 1137 000229A3 # write32h( sgl_ld_acc );
1184: 1138 000229A3 dd effffff673 pushl _sgl_ld_acc
1185: 1139 000229A9 fe 08 effffff66c callf $8,_write32h
1186: 1140 000229B0 # writes(", final Acc = ");
1187: 1141 000229B0 .data 1
1188: 1142 00000d32 * L355:
1189: 1143 00000d32 * 2C202066696E616C204163632 .ascii ", final Acc = \0"
1190: 03D2000
1191: 1144 00000d42 * .text
1192: 1145 000229B0 dd 8f00000d32 pushl $L355
1193: 1146 000229B6 fe 08 effffff65f callf $8,_writes
1194: 1147 000229BD # write32h( sgl_st_acc );
1195: 1148 000229BD dd effffff659 pushl _sgl_st_acc
1196: 1149 000229C3 fe 08 effffff652 callf $8,_write32h
1197: 1150 000229CA # }
1198: 1151 000229CA 40 ret#2
1199: 1152 000229CB .set L350,0x0
1200: 1153 000229CB L352:
1201: 1154 000229CB 11 c9 jbr L353
1202: 1155 000229CD .data
1203: 1156 00000a5c * .text
1204: 1157 000229CD 00 .align 1
1205: 1158 000229CE .globl _sinf_er_halt
1206: 1159 000229CE _sinf_er_halt:
1207: 1160 000229CE 0000 .word L356
1208: 1161 000229D0 #
1209: 1162 000229D0 #
1210: 1163 000229D0 #
1211: 1164 000229D0 # /**************************************************************************
1212: 1165 000229D0 # *
1213: 1166 000229D0 # * HALT ON ERROR ROUTINE
1214: 1167 000229D0 # *
1215: 1168 000229D0 # **************************************************************************/
1216: 1169 000229D0 # sinf_er_halt( halt_code )
1217: 1170 000229D0 # int halt_code;
1218: 1171 000229D0 # {
1219: 1172 000229D0 13 00a0 jbr L358
1220: 1173 000229D3 L359:
1221: 1174 000229D3 # sgl_dummy1 = halt_code; /* get the error type */
1222: 1175 000229D3 0d ad04 effffff641 movl 4(fp),_sgl_dummy1
1223: 1176 000229DB # asm("movl _test_no,r0"); /* r0 = test number */
1224: 1177 000229DB 0d effffff63b 50 movl _test_no,r0
1225: 1178 000229E2 # asm("movl _subtest,r1"); /* r1 = subtest number */
1226: 1179 000229E2 0d effffff634 51 movl _subtest,r1
1227: 1180 000229E9 # asm("movl _sgl_dummy1,r2"); /* r2 = error code */
1228: 1181 000229E9 0d effffff62d 52 movl _sgl_dummy1,r2
1229: 1182 000229F0 # asm("movl _cycle,r3"); /* r3 = cycle count */
1230: 1183 000229F0 0d effffff626 53 movl _cycle,r3
1231: 1184 000229F7 # asm("movl _sgl_ld_acc,r4"); /* r4 = initial data */
1232: 1185 000229F7 0d effffff61f 54 movl _sgl_ld_acc,r4
1233: 1186 000229FE # asm("movl _sgl_st_acc,r5"); /* r5 = data stored */
1234: 1187 000229FE 0d effffff618 55 movl _sgl_st_acc,r5
1235: 1188 00022A05 # asm("movl _sgl_expected,r6"); /* r6 = data expected */
1236: 1189 00022A05 0d effffff611 56 movl _sgl_expected,r6
1237: 1190 00022A0C # asm("movl _index,r7"); /* r7 = data index */
1238: 1191 00022A0C 0d effffff60a 57 movl _index,r7
1239: 1192 00022A13 # if( halt_code == BAD_REG_HLT ) {
1240: 1193 00022A13 1d ad04 02 cmpl 4(fp),$2
1241: 1194 00022A17 21 3d jneq L360
1242: 1195 00022A19 # sgl_dummy1 = load_regs[index2];
1243: 1196 00022A19 0d effffff5fd 50 movl _index2,r0
1244: 1197 00022A20 0d 40effffff5f5 movl _load_regs[r0],_sgl_dummy1
1245: effffff5f0
1246: 1198 00022A2C # sgl_dummy2 = store_regs[index2];
1247: 1199 00022A2C 0d effffff5ea 50 movl _index2,r0
1248: 1200 00022A33 0d 40effffff5e2 movl _store_regs[r0],_sgl_dummy2
1249: effffff5dd
1250: 1201 00022A3F # asm("movl _index2,r6"); /* r6 = bad register # */
1251: 1202 00022A3F 0d effffff5d7 56 movl _index2,r6
1252: 1203 00022A46 # asm("movl _sgl_dummy2,r7"); /* r7 = actual value */
1253: 1204 00022A46 0d effffff5d0 57 movl _sgl_dummy2,r7
1254: 1205 00022A4D # asm("movl _sgl_dummy1,r8"); /* r8 = expected value */
1255: 1206 00022A4D 0d effffff5c9 58 movl _sgl_dummy1,r8
1256: 1207 00022A54 # } else
1257: 1208 00022A54 11 1b jbr L361
1258: 1209 00022A56 L360:
1259: 1210 00022A56 # if( halt_code == BAD_PSL_HLT ) {
1260: 1211 00022A56 1d ad04 03 cmpl 4(fp),$3
1261: 1212 00022A5A 21 15 jneq L362
1262: 1213 00022A5C # asm("movl _init_psl,r6"); /* r6 = initial PSL */
1263: 1214 00022A5C 0d effffff5ba 56 movl _init_psl,r6
1264: 1215 00022A63 # asm("movl _psl_val,r7"); /* r7 = final PSL */
1265: 1216 00022A63 0d effffff5b3 57 movl _psl_val,r7
1266: 1217 00022A6A # asm("movl _exp_psl,r8"); /* r8 = expected PSL */
1267: 1218 00022A6A 0d effffff5ac 58 movl _exp_psl,r8
1268: 1219 00022A71 # };
1269: 1220 00022A71 L362:
1270: 1221 00022A71 L361:
1271: 1222 00022A71 # asm("halt"); /* HALT ... */
1272: 1223 00022A71 00 halt
1273: 1224 00022A72 # }
1274: 1225 00022A72 40 ret#2
1275: 1226 00022A73 .set L356,0x0
1276: 1227 00022A73 L358:
1277: 1228 00022A73 13 ff5d jbr L359
1278: 1229 00022A76 .data
1279: 1229 00044A92 .data
This archive runs on limited infrastructure. Preserving old code on modern bandwidth. Automated agents are requested to crawl responsibly.