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Up to [Power 6/32 Unix Tahoe 4.2BSD] / cci / d / macro4|
Return to sinf.lst CVS log | Up to [Power 6/32 Unix Tahoe 4.2BSD] / cci / d / macro4 |
Power 6/32 Unix version 1.21
1 00000000 LL0:
2 00000000 .data
3 00000a5c * .text
4 00000000 .align 1
5 00000000 .globl _sinf
6 00000000 _sinf:
7 0002201C 0000 .word L215
8 0002201E # #include "fpp_defs.h"
9 0002201E #
10 0002201E #
11 0002201E #
12 0002201E # /***************************************************************************
13 0002201E # *
14 0002201E # * SINF - SINGLE PRECISION FLOATING POINT SINF FUNCTION TEST
15 0002201E # *
16 0002201E # * SINF TEST MONITOR
17 0002201E # *
18 0002201E # *****************************************************************************/
19 0002201E # sinf()
20 0002201E # {
21 0002201E 11 48 jbr L217
22 00022020 L218:
23 00022020 # asm(".globl _sinf_t");
24 00022020 .globl _sinf_t
25 00022020 # asm("_sinf_t:"); /* entry address */
26 00022020 _sinf_t:
27 00022020 # if( ( cycle == 1 ) && ( prt_hdrs ) ) /* print headers on 1st pass */
28 00022020 1d effffffff6 01 cmpl _cycle,$1
29 00022027 21 15 jneq L219
30 00022029 5d efffffffed tstl _prt_hdrs
31 0002202F 31 0d jeql L219
32 00022031 # {
33 00022031 # writes(" SINF");
34 00022031 .data 1
35 00000a5c * L221:
36 00000a5c * 2053494E4600 .ascii " SINF\0"
37 00000a62 * .text
38 00022031 dd 8f00000a5c pushl $L221
39 00022037 fe 08 efffffffde callf $8,_writes
40 0002203E # }
41 0002203E # sinf_1(); /* test square root -w/ delay */
42 0002203E L219:
43 0002203E fe 04 ef00000025 callf $4,_sinf_1
44 00022045 # sinf_2(); /* test square root */
45 00022045 fe 04 ef00000190 callf $4,_sinf_2
46 0002204C # sinf_3(); /* register corruption */
47 0002204C fe 04 ef000002e9 callf $4,_sinf_3
48 00022053 # /* sinf_4(); /* test the PSL */
49 00022053 # sinf_5(); /* pipelined entry */
50 00022053 fe 04 ef00000680 callf $4,_sinf_5
51 0002205A # sinf_6(); /* pipelined exit */
52 0002205A fe 04 ef000007d5 callf $4,_sinf_6
53 00022061 # asm("jmp *return"); /* return to the test monitor */
54 00022061 71 ffffffffb5 jmp *return
55 00022067 # }
56 00022067 40 ret#2
57 00022068 .set L215,0x0
58 00022068 L217:
59 00022068 11 b6 jbr L218
60 0002206A .data
61 00000a5c * .text
62 0002206A .align 1
63 0002206A .globl _sinf_1
64 0002206A _sinf_1:
65 0002206A 0000 .word L227
66 0002206C #
67 0002206C # /***************************************************************************
68 0002206C # *
69 0002206C # * SUBTEST 1 - SINF FUNCTION -wait till done to store
70 0002206C # *
71 0002206C # ***************************************************************************/
72 0002206C # sinf_1()
73 0002206C # {
74 0002206C 13 016a jbr L229
75 0002206F L230:
76 0002206F # #define DELAY 20 /* delay 40 ticks between SINF & STF */
77 0002206F # force_loop = FALSE; /* clear the LOOP flag */
78 0002206F 4d efffffffa7 clrl _force_loop
79 00022075 # subtest = 1;
80 00022075 0d 01 efffffffa0 movl $1,_subtest
81 0002207C # index = 0;
82 0002207C 4d efffffff9a clrl _index
83 00022082 # do
84 00022082 L233:
85 00022082 # {
86 00022082 # sgl_ld_acc = sinf_1_data[index].ld; /* get the operand */
87 00022082 0d efffffff94 50 movl _index,r0
88 00022089 48 03 50 50 shll $3,r0,r0
89 0002208D 0d e000000000 efffffff84 movl _sinf_1_data(r0),_sgl_ld_acc
90 00022098 # sgl_expected = sinf_1_data[index].exp; /* get expected results */
91 00022098 0d efffffff7e 50 movl _index,r0
92 0002209F 48 03 50 50 shll $3,r0,r0
93 000220A3 0d e000000004 efffffff6e movl _sinf_1_data+4(r0),_sgl_expected
94 000220AE # sgl_dummy1 = DELAY;
95 000220AE 0d 14 efffffff67 movl $20,_sgl_dummy1
96 000220B5 # /*
97 000220B5 # * If LOOP ON ERROR is set, this is the loop for this subtest.
98 000220B5 # * The force loop flag is set after the first error.
99 000220B5 # */
100 000220B5 # asm("_sinf_1_lp1:");
101 000220B5 _sinf_1_lp1:
102 000220B5 # asm("movl _sgl_ld_acc,r4"); /* set the data to load */
103 000220B5 0d efffffff61 54 movl _sgl_ld_acc,r4
104 000220BC # asm("ldf r4"); /* load the accumulator */
105 000220BC 06 54 ldf r4
106 000220BE # asm("movl _sgl_dummy1,r0"); /* get the delay factor */
107 000220BE 0d efffffff58 50 movl _sgl_dummy1,r0
108 000220C5 # asm("sinf"); /* get ACC.'s sine */
109 000220C5 05 sinf
110 000220C6 # asm("1:");
111 000220C6 1:
112 000220C6 # asm("decl r0"); /* delay to let the SINF */
113 000220C6 7d 50 decl r0
114 000220C8 # asm("bgtr 1b"); /* instruction finish */
115 000220C8 41 fc bgtr 1b
116 000220CA # asm("stf r5"); /* store the result */
117 000220CA 26 55 stf r5
118 000220CC # if( force_loop )
119 000220CC 5d efffffff4a tstl _force_loop
120 000220D2 31 02 jeql L234
121 000220D4 # asm("brb _sinf_1_lp1");; /* loop on the error */
122 000220D4 11 df brb _sinf_1_lp1
123 000220D6 L234:
124 000220D6 # /*
125 000220D6 # * end error loop
126 000220D6 # */
127 000220D6 # asm("movl r5,_sgl_st_acc"); /* save the result */
128 000220D6 0d 55 efffffff3f movl r5,_sgl_st_acc
129 000220DD # if( sgl_st_acc != sgl_expected ) { /* COMPARE the values */
130 000220DD 1d efffffff39 efffffff34 cmpl _sgl_st_acc,_sgl_expected
131 000220E8 21 03 13 00d2 jeql L235
132 000220ED # errcnt++; /* bump the error count */
133 000220ED 6d efffffff29 incl _errcnt
134 000220F3 # if ( prt_error ) {
135 000220F3 5d efffffff23 tstl _prt_error
136 000220F9 21 03 13 009b jeql L236
137 000220FE # writes(" \n"); /* start a new print line */
138 000220FE .data 1
139 00000a62 * L237:
140 00000a62 * 200A00 .ascii " \12\0"
141 00000a65 * .text
142 000220FE dd 8f00000a62 pushl $L237
143 00022104 fe 08 efffffff11 callf $8,_writes
144 0002210B # writes("cycle: ");
145 0002210B .data 1
146 00000a65 * L238:
147 00000a65 * 6379636C653A2000 .ascii "cycle: \0"
148 00000a6d * .text
149 0002210B dd 8f00000a65 pushl $L238
150 00022111 fe 08 efffffff04 callf $8,_writes
151 00022118 # writed( cycle );
152 00022118 dd effffffefe pushl _cycle
153 0002211E fe 08 effffffef7 callf $8,_writed
154 00022125 # writes(" SINF test ");
155 00022125 .data 1
156 00000a6d * L240:
157 00000a6d * 20202053494E4620746573742 .ascii " SINF test \0"
000
158 00000a7b * .text
159 00022125 dd 8f00000a6d pushl $L240
160 0002212B fe 08 effffffeea callf $8,_writes
161 00022132 # writed( test_no );
162 00022132 dd effffffee4 pushl _test_no
163 00022138 fe 08 effffffedd callf $8,_writed
164 0002213F # writes(", subtest 1 (delayed store) - BAD FINAL ACC\n");
165 0002213F .data 1
166 00000a7b * L241:
167 00000a7b * 2C20737562746573742031202 .ascii ", subtest 1 (delayed store) - BAD FINAL ACC\12\0"
864656C617965642073746F72
6529202D204241442046494E4
14C204143430A00
168 00000aa8 * .text
169 0002213F dd 8f00000a7b pushl $L241
170 00022145 fe 08 effffffed0 callf $8,_writes
171 0002214C # print_sinf_data();
172 0002214C fe 04 ef0000083f callf $4,_print_sinf_data
173 00022153 # writes(", data index = ");
174 00022153 .data 1
175 00000aa8 * L243:
176 00000aa8 * 2C20206461746120696E64657 .ascii ", data index = \0"
8203D2000
177 00000ab9 * .text
178 00022153 dd 8f00000aa8 pushl $L243
179 00022159 fe 08 effffffebc callf $8,_writes
180 00022160 # writed( index );
181 00022160 dd effffffeb6 pushl _index
182 00022166 fe 08 effffffeaf callf $8,_writed
183 0002216D # writec('\n');
184 0002216D dd 0a pushl $10
185 0002216F fe 08 effffffea6 callf $8,_writec
186 00022176 # writes(" Acc expected = ");
187 00022176 .data 1
188 00000ab9 * L245:
189 00000ab9 * 2020202020202020202020202 .ascii " Acc expected = \0"
0202020202020202020416363
206578706563746564203D200
0
190 00000adf * .text
191 00022176 dd 8f00000ab9 pushl $L245
192 0002217C fe 08 effffffe99 callf $8,_writes
193 00022183 # write32h( sgl_expected );
194 00022183 dd effffffe93 pushl _sgl_expected
195 00022189 fe 08 effffffe8c callf $8,_write32h
196 00022190 # writec('\n');
197 00022190 dd 0a pushl $10
198 00022192 fe 08 effffffe83 callf $8,_writec
199 00022199 # }
200 00022199 # if ( halt_flg ) /* halt on error? */
201 00022199 L236:
202 00022199 5d effffffe7d tstl _halt_flg
203 0002219F 31 09 jeql L247
204 000221A1 # sinf_er_halt( BAD_ACC_HLT );
205 000221A1 dd 01 pushl $1
206 000221A3 fe 08 ef00000824 callf $8,_sinf_er_halt
207 000221AA # if ( loop_on_err )
208 000221AA L247:
209 000221AA 5d effffffe6c tstl _loop_on_err
210 000221B0 31 0d jeql L249
211 000221B2 # {
212 000221B2 # force_loop = TRUE; /* set the force loop flag */
213 000221B2 0d 01 effffffe63 movl $1,_force_loop
214 000221B9 # asm("jmp _sinf_1_lp1"); /* and loop */
215 000221B9 71 effffffef6 jmp _sinf_1_lp1
216 000221BF # }
217 000221BF # } /* end of compare error */
218 000221BF L249:
219 000221BF # } while( index++ < max_sinf_1_index );
220 000221BF L235:
221 000221BF L232:
222 000221BF 0d effffffe57 50 movl _index,r0
223 000221C6 6d effffffe50 incl _index
224 000221CC 1d 50 effffffe49 cmpl r0,_max_sinf_1_index
225 000221D3 81 03 13 feaa jlss L233
226 000221D8 L231:
227 000221D8 # } /* end of subtest 1 */
228 000221D8 40 ret#2
229 000221D9 .set L227,0x0
230 000221D9 L229:
231 000221D9 13 fe93 jbr L230
232 000221DC .data
233 00000a5c * .text
234 000221DC .align 1
235 000221DC .globl _sinf_2
236 000221DC _sinf_2:
237 000221DC 0000 .word L250
238 000221DE #
239 000221DE #
240 000221DE #
241 000221DE # /***************************************************************************
242 000221DE # *
243 000221DE # * SUBTEST 2 - SINF FUNCTION
244 000221DE # *
245 000221DE # ***************************************************************************/
246 000221DE # sinf_2()
247 000221DE # {
248 000221DE 13 0158 jbr L252
249 000221E1 L253:
250 000221E1 # force_loop = FALSE; /* clear the LOOP flag */
251 000221E1 4d effffffe35 clrl _force_loop
252 000221E7 # subtest = 2;
253 000221E7 0d 02 effffffe2e movl $2,_subtest
254 000221EE # index = 0;
255 000221EE 4d effffffe28 clrl _index
256 000221F4 # do
257 000221F4 L256:
258 000221F4 # {
259 000221F4 # sgl_ld_acc = sinf_1_data[index].ld; /* get the operand */
260 000221F4 0d effffffe22 50 movl _index,r0
261 000221FB 48 03 50 50 shll $3,r0,r0
262 000221FF 0d e000000000 effffffe12 movl _sinf_1_data(r0),_sgl_ld_acc
263 0002220A # sgl_expected = sinf_1_data[index].exp; /* get expected results */
264 0002220A 0d effffffe0c 50 movl _index,r0
265 00022211 48 03 50 50 shll $3,r0,r0
266 00022215 0d e000000004 effffffdfc movl _sinf_1_data+4(r0),_sgl_expected
267 00022220 # /*
268 00022220 # * If LOOP ON ERROR is set, this is the loop for this subtest.
269 00022220 # * The force loop flag is set after the first error.
270 00022220 # */
271 00022220 # asm("_sinf_2_lp1:");
272 00022220 _sinf_2_lp1:
273 00022220 # asm("movl _sgl_ld_acc,r4"); /* set the data to load */
274 00022220 0d effffffdf6 54 movl _sgl_ld_acc,r4
275 00022227 # asm("ldf r4"); /* load the accumulator */
276 00022227 06 54 ldf r4
277 00022229 # asm("sinf"); /* get ACC.'s sine */
278 00022229 05 sinf
279 0002222A # asm("stf r5"); /* store the result */
280 0002222A 26 55 stf r5
281 0002222C # if( force_loop )
282 0002222C 5d effffffdea tstl _force_loop
283 00022232 31 02 jeql L257
284 00022234 # asm("brb _sinf_2_lp1");; /* loop on the error */
285 00022234 11 ea brb _sinf_2_lp1
286 00022236 L257:
287 00022236 # /*
288 00022236 # * end error loop
289 00022236 # */
290 00022236 # asm("movl r5,_sgl_st_acc"); /* save the result */
291 00022236 0d 55 effffffddf movl r5,_sgl_st_acc
292 0002223D # if( sgl_st_acc != sgl_expected ) { /* COMPARE the values */
293 0002223D 1d effffffdd9 effffffdd4 cmpl _sgl_st_acc,_sgl_expected
294 00022248 21 03 13 00d2 jeql L258
295 0002224D # errcnt++; /* bump the error count */
296 0002224D 6d effffffdc9 incl _errcnt
297 00022253 # if ( prt_error ) {
298 00022253 5d effffffdc3 tstl _prt_error
299 00022259 21 03 13 009b jeql L259
300 0002225E # writes(" \n"); /* start a new print line */
301 0002225E .data 1
302 00000adf * L260:
303 00000adf * 200A00 .ascii " \12\0"
304 00000ae2 * .text
305 0002225E dd 8f00000adf pushl $L260
306 00022264 fe 08 effffffdb1 callf $8,_writes
307 0002226B # writes("cycle: ");
308 0002226B .data 1
309 00000ae2 * L261:
310 00000ae2 * 6379636C653A2000 .ascii "cycle: \0"
311 00000aea * .text
312 0002226B dd 8f00000ae2 pushl $L261
313 00022271 fe 08 effffffda4 callf $8,_writes
314 00022278 # writed( cycle );
315 00022278 dd effffffd9e pushl _cycle
316 0002227E fe 08 effffffd97 callf $8,_writed
317 00022285 # writes(" SINF test ");
318 00022285 .data 1
319 00000aea * L262:
320 00000aea * 20202053494E4620746573742 .ascii " SINF test \0"
000
321 00000af8 * .text
322 00022285 dd 8f00000aea pushl $L262
323 0002228B fe 08 effffffd8a callf $8,_writes
324 00022292 # writed( test_no );
325 00022292 dd effffffd84 pushl _test_no
326 00022298 fe 08 effffffd7d callf $8,_writed
327 0002229F # writes(", subtest 2 (immediate store) - BAD FINAL ACC\n");
328 0002229F .data 1
329 00000af8 * L263:
330 00000af8 * 2C20737562746573742032202 .ascii ", subtest 2 (immediate store) - BAD FINAL ACC\12\0"
8696D6D656469617465207374
6F726529202D2042414420464
94E414C204143430A00
331 00000b27 * .text
332 0002229F dd 8f00000af8 pushl $L263
333 000222A5 fe 08 effffffd70 callf $8,_writes
334 000222AC # print_sinf_data();
335 000222AC fe 04 ef000006df callf $4,_print_sinf_data
336 000222B3 # writes(", data index = ");
337 000222B3 .data 1
338 00000b27 * L264:
339 00000b27 * 2C20206461746120696E64657 .ascii ", data index = \0"
8203D2000
340 00000b38 * .text
341 000222B3 dd 8f00000b27 pushl $L264
342 000222B9 fe 08 effffffd5c callf $8,_writes
343 000222C0 # writed( index );
344 000222C0 dd effffffd56 pushl _index
345 000222C6 fe 08 effffffd4f callf $8,_writed
346 000222CD # writec('\n');
347 000222CD dd 0a pushl $10
348 000222CF fe 08 effffffd46 callf $8,_writec
349 000222D6 # writes(" Acc expected = ");
350 000222D6 .data 1
351 00000b38 * L265:
352 00000b38 * 2020202020202020202020202 .ascii " Acc expected = \0"
0202020202020202020416363
206578706563746564203D200
0
353 00000b5e * .text
354 000222D6 dd 8f00000b38 pushl $L265
355 000222DC fe 08 effffffd39 callf $8,_writes
356 000222E3 # write32h( sgl_expected );
357 000222E3 dd effffffd33 pushl _sgl_expected
358 000222E9 fe 08 effffffd2c callf $8,_write32h
359 000222F0 # writec('\n');
360 000222F0 dd 0a pushl $10
361 000222F2 fe 08 effffffd23 callf $8,_writec
362 000222F9 # }
363 000222F9 # if ( halt_flg ) /* halt on error? */
364 000222F9 L259:
365 000222F9 5d effffffd1d tstl _halt_flg
366 000222FF 31 09 jeql L266
367 00022301 # sinf_er_halt( BAD_ACC_HLT );
368 00022301 dd 01 pushl $1
369 00022303 fe 08 ef000006c4 callf $8,_sinf_er_halt
370 0002230A # if ( loop_on_err )
371 0002230A L266:
372 0002230A 5d effffffd0c tstl _loop_on_err
373 00022310 31 0d jeql L267
374 00022312 # {
375 00022312 # force_loop = TRUE; /* set the force loop flag */
376 00022312 0d 01 effffffd03 movl $1,_force_loop
377 00022319 # asm("jmp _sinf_2_lp1"); /* and loop */
378 00022319 71 efffffff01 jmp _sinf_2_lp1
379 0002231F # }
380 0002231F # } /* end of compare error */
381 0002231F L267:
382 0002231F # } while( index++ < max_sinf_1_index );
383 0002231F L258:
384 0002231F L255:
385 0002231F 0d effffffcf7 50 movl _index,r0
386 00022326 6d effffffcf0 incl _index
387 0002232C 1d 50 effffffce9 cmpl r0,_max_sinf_1_index
388 00022333 81 03 13 febc jlss L256
389 00022338 L254:
390 00022338 # } /* end of subtest 2 */
391 00022338 40 ret#2
392 00022339 .set L250,0x0
393 00022339 L252:
394 00022339 13 fea5 jbr L253
395 0002233C .data
396 00000a5c * .text
397 0002233C .align 1
398 0002233C .globl _sinf_3
399 0002233C _sinf_3:
400 0002233C 0000 .word L268
401 0002233E #
402 0002233E #
403 0002233E #
404 0002233E # /***************************************************************************
405 0002233E # *
406 0002233E # * SUBTEST 3 - REGISTER INTEGRITY WITH THE SINF FUNCTION
407 0002233E # *
408 0002233E # ***************************************************************************/
409 0002233E # sinf_3()
410 0002233E # {
411 0002233E 13 01e1 jbr L270
412 00022341 L271:
413 00022341 # fill_reg_buf( load_regs ); /* set reg values to load */
414 00022341 dd 8f00000000 pushl $_load_regs
415 00022347 fe 08 effffffcce callf $8,_fill_reg_buf
416 0002234E # force_loop = FALSE; /* clear the LOOP flag */
417 0002234E 4d effffffcc8 clrl _force_loop
418 00022354 # subtest = 3;
419 00022354 0d 03 effffffcc1 movl $3,_subtest
420 0002235B # index = 0;
421 0002235B 4d effffffcbb clrl _index
422 00022361 # do
423 00022361 L275:
424 00022361 # {
425 00022361 # sgl_ld_acc = sinf_1_data[index].ld; /* get the operand */
426 00022361 0d effffffcb5 50 movl _index,r0
427 00022368 48 03 50 50 shll $3,r0,r0
428 0002236C 0d e000000000 effffffca5 movl _sinf_1_data(r0),_sgl_ld_acc
429 00022377 # sgl_expected = sinf_1_data[index].exp; /* get expected results */
430 00022377 0d effffffc9f 50 movl _index,r0
431 0002237E 48 03 50 50 shll $3,r0,r0
432 00022382 0d e000000004 effffffc8f movl _sinf_1_data+4(r0),_sgl_expected
433 0002238D # /*
434 0002238D # * If LOOP ON ERROR is set, this is the loop for this subtest.
435 0002238D # * The force loop flag is set after the first error.
436 0002238D # */
437 0002238D # asm("_sinf_3_lp1:");
438 0002238D _sinf_3_lp1:
439 0002238D # asm("loadr $0x1fff,_load_regs"); /* load regs 0 - 12 */
440 0002238D ab 891fff effffffc86 loadr $0x1fff,_load_regs
441 00022396 # asm("ldf _sgl_ld_acc"); /* load the accumulator */
442 00022396 06 effffffc80 ldf _sgl_ld_acc
443 0002239C # asm("sinf"); /* get ACC.'s sine */
444 0002239C 05 sinf
445 0002239D # asm("stf _sgl_st_acc"); /* store the result */
446 0002239D 26 effffffc79 stf _sgl_st_acc
447 000223A3 # asm("storer $0x1fff,_store_regs"); /* store regs 0 - 12 */
448 000223A3 bb 891fff effffffc70 storer $0x1fff,_store_regs
449 000223AC # if( force_loop )
450 000223AC 5d effffffc6a tstl _force_loop
451 000223B2 31 02 jeql L276
452 000223B4 # asm("brb _sinf_3_lp1");; /* loop on the error */
453 000223B4 11 d7 brb _sinf_3_lp1
454 000223B6 L276:
455 000223B6 # /*
456 000223B6 # * end error loop
457 000223B6 # */
458 000223B6 # reg_no = 0;
459 000223B6 4d effffffc60 clrl _reg_no
460 000223BC # regs_ok = TRUE;
461 000223BC 0d 01 effffffc59 movl $1,_regs_ok
462 000223C3 # while( (reg_no < 13) && (regs_ok) ) /* check 1st 12 regs */
463 000223C3 L277:
464 000223C3 1d effffffc53 0d cmpl _reg_no,$13
465 000223CA 81 35 jgeq L278
466 000223CC 5d effffffc4a tstl _regs_ok
467 000223D2 31 2d jeql L278
468 000223D4 # if( store_regs[ reg_no ] == load_regs[ reg_no ] )
469 000223D4 0d effffffc42 50 movl _reg_no,r0
470 000223DB 0d effffffc3b 51 movl _reg_no,r1
471 000223E2 1d 40effffffc33 cmpl _store_regs[r0],_load_regs[r1]
41effffffc2d
472 000223EF 21 08 jneq L279
473 000223F1 # reg_no++;
474 000223F1 6d effffffc25 incl _reg_no
475 000223F7 # else
476 000223F7 11 06 jbr L280
477 000223F9 L279:
478 000223F9 # regs_ok = FALSE;
479 000223F9 4d effffffc1d clrl _regs_ok
480 000223FF L280:
481 000223FF 11 c2 jbr L277
482 00022401 L278:
483 00022401 # if( !regs_ok ) {
484 00022401 5d effffffc15 tstl _regs_ok
485 00022407 31 03 13 00fc jneq L281
486 0002240C # errcnt++; /* bump the error count */
487 0002240C 6d effffffc0a incl _errcnt
488 00022412 # if ( prt_error ) {
489 00022412 5d effffffc04 tstl _prt_error
490 00022418 21 03 13 00eb jeql L282
491 0002241D # writes(" \n"); /* start a new print line */
492 0002241D .data 1
493 00000b5e * L283:
494 00000b5e * 200A00 .ascii " \12\0"
495 00000b61 * .text
496 0002241D dd 8f00000b5e pushl $L283
497 00022423 fe 08 effffffbf2 callf $8,_writes
498 0002242A # writes("cycle: ");
499 0002242A .data 1
500 00000b61 * L284:
501 00000b61 * 6379636C653A2000 .ascii "cycle: \0"
502 00000b69 * .text
503 0002242A dd 8f00000b61 pushl $L284
504 00022430 fe 08 effffffbe5 callf $8,_writes
505 00022437 # writed( cycle );
506 00022437 dd effffffbdf pushl _cycle
507 0002243D fe 08 effffffbd8 callf $8,_writed
508 00022444 # writes(" SINF test ");
509 00022444 .data 1
510 00000b69 * L285:
511 00000b69 * 20202053494E4620746573742 .ascii " SINF test \0"
000
512 00000b77 * .text
513 00022444 dd 8f00000b69 pushl $L285
514 0002244A fe 08 effffffbcb callf $8,_writes
515 00022451 # writed( test_no );
516 00022451 dd effffffbc5 pushl _test_no
517 00022457 fe 08 effffffbbe callf $8,_writed
518 0002245E # writes(", subtest 3 - A REGISTER WAS MODIFIED\n"); {
519 0002245E .data 1
520 00000b77 * L286:
521 00000b77 * 2C20737562746573742033202 .ascii ", subtest 3 - A REGISTER WAS MODIFIED\12\0"
D204120524547495354455220
574153204D4F4449464945440
A00
522 00000b9e * .text
523 0002245E dd 8f00000b77 pushl $L286
524 00022464 fe 08 effffffbb1 callf $8,_writes
525 0002246B # print_sinf_data();
526 0002246B fe 04 ef00000520 callf $4,_print_sinf_data
527 00022472 # writec('\n');
528 00022472 dd 0a pushl $10
529 00022474 fe 08 effffffba1 callf $8,_writec
530 0002247B # writes("register ");
531 0002247B .data 1
532 00000b9e * L287:
533 00000b9e * 72656769737465722000 .ascii "register \0"
534 00000ba8 * .text
535 0002247B dd 8f00000b9e pushl $L287
536 00022481 fe 08 effffffb94 callf $8,_writes
537 00022488 # writed( reg_no );
538 00022488 dd effffffb8e pushl _reg_no
539 0002248E fe 08 effffffb87 callf $8,_writed
540 00022495 # writes(" = ");
541 00022495 .data 1
542 00000ba8 * L288:
543 00000ba8 * 203D2000 .ascii " = \0"
544 00000bac * .text
545 00022495 dd 8f00000ba8 pushl $L288
546 0002249B fe 08 effffffb7a callf $8,_writes
547 000224A2 # write32h( load_regs[reg_no] );
548 000224A2 0d effffffb74 50 movl _reg_no,r0
549 000224A9 dd 40effffffb6c pushl _load_regs[r0]
550 000224B0 fe 08 effffffb65 callf $8,_write32h
551 000224B7 # writes(", should be = ");
552 000224B7 .data 1
553 00000bac * L289:
554 00000bac * 2C202073686F756C642062652 .ascii ", should be = \0"
03D2000
555 00000bbc * .text
556 000224B7 dd 8f00000bac pushl $L289
557 000224BD fe 08 effffffb58 callf $8,_writes
558 000224C4 # write32h( store_regs[reg_no] );
559 000224C4 0d effffffb52 50 movl _reg_no,r0
560 000224CB dd 40effffffb4a pushl _store_regs[r0]
561 000224D2 fe 08 effffffb43 callf $8,_write32h
562 000224D9 # writec('\n');
563 000224D9 dd 0a pushl $10
564 000224DB fe 08 effffffb3a callf $8,_writec
565 000224E2 # }
566 000224E2 # if ( halt_flg ) /* halt on error? */
567 000224E2 5d effffffb34 tstl _halt_flg
568 000224E8 31 09 jeql L290
569 000224EA # sinf_er_halt( BAD_REG_HLT );
570 000224EA dd 02 pushl $2
571 000224EC fe 08 ef000004db callf $8,_sinf_er_halt
572 000224F3 # if ( loop_on_err )
573 000224F3 L290:
574 000224F3 5d effffffb23 tstl _loop_on_err
575 000224F9 31 0d jeql L291
576 000224FB # {
577 000224FB # force_loop = TRUE; /* get the force loop flag */
578 000224FB 0d 01 effffffb1a movl $1,_force_loop
579 00022502 # asm("jmp _sinf_3_lp1"); /* and loop */
580 00022502 71 effffffe85 jmp _sinf_3_lp1
581 00022508 # }
582 00022508 # } /* end of compare error */
583 00022508 L291:
584 00022508 # } /* end of while loop */
585 00022508 L282:
586 00022508 # } while( index++ < max_sinf_1_index );
587 00022508 L281:
588 00022508 L274:
589 00022508 0d effffffb0e 50 movl _index,r0
590 0002250F 6d effffffb07 incl _index
591 00022515 1d 50 effffffb00 cmpl r0,_max_sinf_1_index
592 0002251C 81 03 13 fe40 jlss L275
593 00022521 L273:
594 00022521 # } /* end of subtest 3 */
595 00022521 40 ret#2
596 00022522 .set L268,0x0
597 00022522 L270:
598 00022522 13 fe1c jbr L271
599 00022525 .data
600 00000a5c * .text
601 00022525 00 .align 1
602 00022526 .globl _sinf_4
603 00022526 _sinf_4:
604 00022526 0000 .word L293
605 00022528 #
606 00022528 #
607 00022528 #
608 00022528 # /************************************************************************
609 00022528 # *
610 00022528 # * SUBTEST 4 - Check for PSL corruption
611 00022528 # *
612 00022528 # ************************************************************************/
613 00022528 # sinf_4()
614 00022528 # {
615 00022528 13 01ac jbr L295
616 0002252B L296:
617 0002252B # force_loop = FALSE; /* clear force_loop flg */
618 0002252B 4d effffffaeb clrl _force_loop
619 00022531 # subtest = 4;
620 00022531 0d 04 effffffae4 movl $4,_subtest
621 00022538 # fill_reg_buf( load_regs ); /* get patterns for regs */
622 00022538 dd 8f00000000 pushl $_load_regs
623 0002253E fe 08 effffffad7 callf $8,_fill_reg_buf
624 00022545 # for( index = 0; index < 3; index++ ) {
625 00022545 4d effffffad1 clrl _index
626 0002254B L299:
627 0002254B 1d effffffacb 03 cmpl _index,$3
628 00022552 91 03 13 017f jgeq L298
629 00022557 # sgl_ld_acc = sinf_1_data[index].ld; /* get operand 1 */
630 00022557 0d effffffabf 50 movl _index,r0
631 0002255E 48 03 50 50 shll $3,r0,r0
632 00022562 0d e000000000 effffffaaf movl _sinf_1_data(r0),_sgl_ld_acc
633 0002256D # sgl_expected = sinf_1_data[index].exp; /* get expected */
634 0002256D 0d effffffaa9 50 movl _index,r0
635 00022574 48 03 50 50 shll $3,r0,r0
636 00022578 0d e000000004 effffffa99 movl _sinf_1_data+4(r0),_sgl_expected
637 00022583 # sgl_dummy1 = status_array[status_index]; /* status = +, -, 0 */
638 00022583 0d effffffa93 50 movl _status_index,r0
639 0002258A 0d 40effffffa8b movl _status_array[r0],_sgl_dummy1
effffffa86
640 00022596 # /*
641 00022596 # * If LOOP ON ERROR is set, this is the loop for this subtest.
642 00022596 # * The force loop flag is set after the first error.
643 00022596 # */
644 00022596 # asm("_sinf_4_lp1:");
645 00022596 _sinf_4_lp1:
646 00022596 # asm("ldf _sgl_ld_acc"); /* LOAD the accumulator */
647 00022596 06 effffffa80 ldf _sgl_ld_acc
648 0002259C # asm("nop");
649 0002259C 10 nop
650 0002259D # asm("tstl _sgl_dummy1"); /* set the PSL status */
651 0002259D 5d effffffa79 tstl _sgl_dummy1
652 000225A3 # asm("movpsl _init_psl"); /* save the initial PSL */
653 000225A3 cd effffffa73 movpsl _init_psl
654 000225A9 # asm("sinf"); /* do the sine */
655 000225A9 05 sinf
656 000225AA # asm("nop");
657 000225AA 10 nop
658 000225AB # asm("movpsl _psl_val"); /* save the final PSL */
659 000225AB cd effffffa6b movpsl _psl_val
660 000225B1 # asm("stf _sgl_st_acc"); /* save the accumulator */
661 000225B1 26 effffffa65 stf _sgl_st_acc
662 000225B7 # if( force_loop )
663 000225B7 5d effffffa5f tstl _force_loop
664 000225BD 31 02 jeql L300
665 000225BF # asm("brb _sinf_4_lp1");; /* loop on the error */
666 000225BF 11 d5 brb _sinf_4_lp1
667 000225C1 L300:
668 000225C1 # /*
669 000225C1 # * Now compare the final PSL to the initial PSL -they should be the same
670 000225C1 # */
671 000225C1 # exp_psl = init_psl;
672 000225C1 0d effffffa55 effffffa50 movl _init_psl,_exp_psl
673 000225CC # if( psl_val != exp_psl ) {
674 000225CC 1d effffffa4a effffffa45 cmpl _psl_val,_exp_psl
675 000225D7 21 03 13 00f1 jeql L301
676 000225DC # errcnt++; /* bump the error count */
677 000225DC 6d effffffa3a incl _errcnt
678 000225E2 # if( prt_error ) {
679 000225E2 5d effffffa34 tstl _prt_error
680 000225E8 21 03 13 00bd jeql L302
681 000225ED # writes(" \n"); /* start a new print line */
682 000225ED .data 1
683 00000bbc * L303:
684 00000bbc * 200A00 .ascii " \12\0"
685 00000bbf * .text
686 000225ED dd 8f00000bbc pushl $L303
687 000225F3 fe 08 effffffa22 callf $8,_writes
688 000225FA # writes("cycle: ");
689 000225FA .data 1
690 00000bbf * L304:
691 00000bbf * 6379636C653A2000 .ascii "cycle: \0"
692 00000bc7 * .text
693 000225FA dd 8f00000bbf pushl $L304
694 00022600 fe 08 effffffa15 callf $8,_writes
695 00022607 # writed( cycle );
696 00022607 dd effffffa0f pushl _cycle
697 0002260D fe 08 effffffa08 callf $8,_writed
698 00022614 # writes(" SINF test ");
699 00022614 .data 1
700 00000bc7 * L305:
701 00000bc7 * 20202053494E4620746573742 .ascii " SINF test \0"
000
702 00000bd5 * .text
703 00022614 dd 8f00000bc7 pushl $L305
704 0002261A fe 08 effffff9fb callf $8,_writes
705 00022621 # writed( test_no );
706 00022621 dd effffff9f5 pushl _test_no
707 00022627 fe 08 effffff9ee callf $8,_writed
708 0002262E # writes(", subtest 4 - INCORRECT FINAL PSL\n");
709 0002262E .data 1
710 00000bd5 * L306:
711 00000bd5 * 2C20737562746573742034202 .ascii ", subtest 4 - INCORRECT FINAL PSL\12\0"
D20494E434F52524543542046
494E414C2050534C0A00
712 00000bf8 * .text
713 0002262E dd 8f00000bd5 pushl $L306
714 00022634 fe 08 effffff9e1 callf $8,_writes
715 0002263B # print_sinf_data(); /* print the operands */
716 0002263B fe 04 ef00000350 callf $4,_print_sinf_data
717 00022642 # writes("\n");
718 00022642 .data 1
719 00000bf8 * L307:
720 00000bf8 * 0A00 .ascii "\12\0"
721 00000bfa * .text
722 00022642 dd 8f00000bf8 pushl $L307
723 00022648 fe 08 effffff9cd callf $8,_writes
724 0002264F # writes("initial PSL = ");
725 0002264F .data 1
726 00000bfa * L308:
727 00000bfa * 696E697469616C2050534C203 .ascii "initial PSL = \0"
D2000
728 00000c09 * .text
729 0002264F dd 8f00000bfa pushl $L308
730 00022655 fe 08 effffff9c0 callf $8,_writes
731 0002265C # write32h( init_psl );
732 0002265C dd effffff9ba pushl _init_psl
733 00022662 fe 08 effffff9b3 callf $8,_write32h
734 00022669 # writes(", final PSL = ");
735 00022669 .data 1
736 00000c09 * L309:
737 00000c09 * 2C202066696E616C2050534C2 .ascii ", final PSL = \0"
03D2000
738 00000c19 * .text
739 00022669 dd 8f00000c09 pushl $L309
740 0002266F fe 08 effffff9a6 callf $8,_writes
741 00022676 # write32h( psl_val );
742 00022676 dd effffff9a0 pushl _psl_val
743 0002267C fe 08 effffff999 callf $8,_write32h
744 00022683 # writes(", expected PSL = ");
745 00022683 .data 1
746 00000c19 * L310:
747 00000c19 * 2C20206578706563746564205 .ascii ", expected PSL = \0"
0534C203D2000
748 00000c2c * .text
749 00022683 dd 8f00000c19 pushl $L310
750 00022689 fe 08 effffff98c callf $8,_writes
751 00022690 # write32h( exp_psl );
752 00022690 dd effffff986 pushl _exp_psl
753 00022696 fe 08 effffff97f callf $8,_write32h
754 0002269D # writes("\n");
755 0002269D .data 1
756 00000c2c * L311:
757 00000c2c * 0A00 .ascii "\12\0"
758 00000c2e * .text
759 0002269D dd 8f00000c2c pushl $L311
760 000226A3 fe 08 effffff972 callf $8,_writes
761 000226AA # }
762 000226AA # if( halt_flg )
763 000226AA L302:
764 000226AA 5d effffff96c tstl _halt_flg
765 000226B0 31 09 jeql L312
766 000226B2 # sinf_er_halt( BAD_PSL_HLT ); /* halt on the error */
767 000226B2 dd 03 pushl $3
768 000226B4 fe 08 ef00000313 callf $8,_sinf_er_halt
769 000226BB # if( loop_on_err ) {
770 000226BB L312:
771 000226BB 5d effffff95b tstl _loop_on_err
772 000226C1 31 0a jeql L313
773 000226C3 # force_loop = TRUE; /* set the force loop flag */
774 000226C3 0d 01 effffff952 movl $1,_force_loop
775 000226CA # asm("brw _sinf_4_lp1");; /* and loop on the error */
776 000226CA 13 fec9 brw _sinf_4_lp1
777 000226CD # } /* end of loop on error */
778 000226CD # } /* end of PSL corruption error */
779 000226CD L313:
780 000226CD # } /* end of WHILE loop */
781 000226CD L301:
782 000226CD L297:
783 000226CD 6d effffff949 incl _index
784 000226D3 13 fe75 jbr L299
785 000226D6 L298:
786 000226D6 # } /* end of subtest 4 */
787 000226D6 40 ret#2
788 000226D7 .set L293,0x0
789 000226D7 L295:
790 000226D7 13 fe51 jbr L296
791 000226DA .data
792 00000a5c * .text
793 000226DA .align 1
794 000226DA .globl _sinf_5
795 000226DA _sinf_5:
796 000226DA 0000 .word L314
797 000226DC #
798 000226DC #
799 000226DC #
800 000226DC # /************************************************************************
801 000226DC # *
802 000226DC # * SUBTEST 5 - pipelined entry test
803 000226DC # *
804 000226DC # ************************************************************************/
805 000226DC # sinf_5()
806 000226DC # {
807 000226DC 13 0154 jbr L316
808 000226DF L317:
809 000226DF # force_loop = FALSE;
810 000226DF 4d effffff937 clrl _force_loop
811 000226E5 # subtest = 8;
812 000226E5 0d 08 effffff930 movl $8,_subtest
813 000226EC # for( index = 0; index < max_sinf_1_index; index++ ) {
814 000226EC 4d effffff92a clrl _index
815 000226F2 L320:
816 000226F2 1d effffff924 effffff91f cmpl _index,_max_sinf_1_index
817 000226FD 91 03 13 0130 jgeq L319
818 00022702 # sgl_ld_acc = sinf_1_data[index].ld; /* get operand 1 */
819 00022702 0d effffff914 50 movl _index,r0
820 00022709 48 03 50 50 shll $3,r0,r0
821 0002270D 0d e000000000 effffff904 movl _sinf_1_data(r0),_sgl_ld_acc
822 00022718 # sgl_expected = sinf_1_data[index].exp; /* get expected result */
823 00022718 0d effffff8fe 50 movl _index,r0
824 0002271F 48 03 50 50 shll $3,r0,r0
825 00022723 0d e000000004 effffff8ee movl _sinf_1_data+4(r0),_sgl_expected
826 0002272E # /*
827 0002272E # * If LOOP ON ERROR is set, this is the loop for this subtest.
828 0002272E # * The force loop flag is set after the first error.
829 0002272E # */
830 0002272E # asm("_sinf_5_lp1:");
831 0002272E _sinf_5_lp1:
832 0002272E # asm("movl $0,r0"); /* clear r0 */
833 0002272E 0d 00 50 movl $0,r0
834 00022731 # asm("ldf r0"); /* load the Acc. with 0.0 */
835 00022731 06 50 ldf r0
836 00022733 # asm("addf _sgl_ld_acc"); /* add the 1st operand */
837 00022733 c6 effffff8e3 addf _sgl_ld_acc
838 00022739 # asm("sinf"); /* get the sine */
839 00022739 05 sinf
840 0002273A # asm("stf _sgl_st_acc"); /* store the result */
841 0002273A 26 effffff8dc stf _sgl_st_acc
842 00022740 # if( force_loop )
843 00022740 5d effffff8d6 tstl _force_loop
844 00022746 31 02 jeql L321
845 00022748 # asm("brb _sinf_5_lp1");; /* loop on the error */
846 00022748 11 e4 brb _sinf_5_lp1
847 0002274A L321:
848 0002274A # /*
849 0002274A # * end error loop - test the results
850 0002274A # */
851 0002274A # if( sgl_st_acc != sgl_expected ) { /* COMPARE the values */
852 0002274A 1d effffff8cc effffff8c7 cmpl _sgl_st_acc,_sgl_expected
853 00022755 21 03 13 00cf jeql L322
854 0002275A # errcnt++; /* bump the error count */
855 0002275A 6d effffff8bc incl _errcnt
856 00022760 # if( prt_error ) {
857 00022760 5d effffff8b6 tstl _prt_error
858 00022766 21 03 13 009b jeql L323
859 0002276B # writes(" \n"); /* start a new print line */
860 0002276B .data 1
861 00000c2e * L324:
862 00000c2e * 200A00 .ascii " \12\0"
863 00000c31 * .text
864 0002276B dd 8f00000c2e pushl $L324
865 00022771 fe 08 effffff8a4 callf $8,_writes
866 00022778 # writes("cycle: ");
867 00022778 .data 1
868 00000c31 * L325:
869 00000c31 * 6379636C653A2000 .ascii "cycle: \0"
870 00000c39 * .text
871 00022778 dd 8f00000c31 pushl $L325
872 0002277E fe 08 effffff897 callf $8,_writes
873 00022785 # writed( cycle );
874 00022785 dd effffff891 pushl _cycle
875 0002278B fe 08 effffff88a callf $8,_writed
876 00022792 # writes(" SINF test ");
877 00022792 .data 1
878 00000c39 * L326:
879 00000c39 * 20202053494E4620746573742 .ascii " SINF test \0"
000
880 00000c47 * .text
881 00022792 dd 8f00000c39 pushl $L326
882 00022798 fe 08 effffff87d callf $8,_writes
883 0002279F # writed( test_no );
884 0002279F dd effffff877 pushl _test_no
885 000227A5 fe 08 effffff870 callf $8,_writed
886 000227AC # writes(", subtest 5 (Piped Entry) - BAD FINAL ACC\n");
887 000227AC .data 1
888 00000c47 * L327:
889 00000c47 * 2C20737562746573742035202 .ascii ", subtest 5 (Piped Entry) - BAD FINAL ACC\12\0"
8506970656420456E74727929
202D204241442046494E414C2
04143430A00
890 00000c72 * .text
891 000227AC dd 8f00000c47 pushl $L327
892 000227B2 fe 08 effffff863 callf $8,_writes
893 000227B9 # print_sinf_data();
894 000227B9 fe 04 ef000001d2 callf $4,_print_sinf_data
895 000227C0 # writes(", data index = ");
896 000227C0 .data 1
897 00000c72 * L328:
898 00000c72 * 2C20206461746120696E64657 .ascii ", data index = \0"
8203D2000
899 00000c83 * .text
900 000227C0 dd 8f00000c72 pushl $L328
901 000227C6 fe 08 effffff84f callf $8,_writes
902 000227CD # writed( index );
903 000227CD dd effffff849 pushl _index
904 000227D3 fe 08 effffff842 callf $8,_writed
905 000227DA # writec('\n');
906 000227DA dd 0a pushl $10
907 000227DC fe 08 effffff839 callf $8,_writec
908 000227E3 # writes(" Acc expected = ");
909 000227E3 .data 1
910 00000c83 * L329:
911 00000c83 * 2020202020202020202020202 .ascii " Acc expected = \0"
0202020202020202020416363
206578706563746564203D200
0
912 00000ca9 * .text
913 000227E3 dd 8f00000c83 pushl $L329
914 000227E9 fe 08 effffff82c callf $8,_writes
915 000227F0 # write32h( sgl_expected );
916 000227F0 dd effffff826 pushl _sgl_expected
917 000227F6 fe 08 effffff81f callf $8,_write32h
918 000227FD # writec('\n');
919 000227FD dd 0a pushl $10
920 000227FF fe 08 effffff816 callf $8,_writec
921 00022806 # }
922 00022806 # if( halt_flg )
923 00022806 L323:
924 00022806 5d effffff810 tstl _halt_flg
925 0002280C 31 09 jeql L330
926 0002280E # sinf_er_halt( BAD_ACC_HLT ); /* halt on the error */
927 0002280E dd 01 pushl $1
928 00022810 fe 08 ef000001b7 callf $8,_sinf_er_halt
929 00022817 # if( loop_on_err ) {
930 00022817 L330:
931 00022817 5d effffff7ff tstl _loop_on_err
932 0002281D 31 0a jeql L331
933 0002281F # force_loop = TRUE; /* set the force loop flag */
934 0002281F 0d 01 effffff7f6 movl $1,_force_loop
935 00022826 # asm("brw _sinf_5_lp1");; /* and loop on the error */
936 00022826 13 ff05 brw _sinf_5_lp1
937 00022829 # } /* end of loop on error */
938 00022829 # } /* end of compare error */
939 00022829 L331:
940 00022829 # } /* end of WHILE loop */
941 00022829 L322:
942 00022829 L318:
943 00022829 6d effffff7ed incl _index
944 0002282F 13 fec0 jbr L320
945 00022832 L319:
946 00022832 # } /* end of subtest 5 */
947 00022832 40 ret#2
948 00022833 .set L314,0x0
949 00022833 L316:
950 00022833 13 fea9 jbr L317
951 00022836 .data
952 00000a5c * .text
953 00022836 .align 1
954 00022836 .globl _sinf_6
955 00022836 _sinf_6:
956 00022836 0000 .word L332
957 00022838 #
958 00022838 #
959 00022838 #
960 00022838 # /************************************************************************
961 00022838 # *
962 00022838 # * SUBTEST 6 - pipelined exit test
963 00022838 # *
964 00022838 # ************************************************************************/
965 00022838 # sinf_6()
966 00022838 # {
967 00022838 13 0154 jbr L334
968 0002283B L335:
969 0002283B # force_loop = FALSE;
970 0002283B 4d effffff7db clrl _force_loop
971 00022841 # subtest = 8;
972 00022841 0d 08 effffff7d4 movl $8,_subtest
973 00022848 # for( index = 0; index < max_sinf_1_index; index++ ) {
974 00022848 4d effffff7ce clrl _index
975 0002284E L338:
976 0002284E 1d effffff7c8 effffff7c3 cmpl _index,_max_sinf_1_index
977 00022859 91 03 13 0130 jgeq L337
978 0002285E # sgl_ld_acc = sinf_1_data[index].ld; /* get operand 1 */
979 0002285E 0d effffff7b8 50 movl _index,r0
980 00022865 48 03 50 50 shll $3,r0,r0
981 00022869 0d e000000000 effffff7a8 movl _sinf_1_data(r0),_sgl_ld_acc
982 00022874 # sgl_expected = sinf_1_data[index].exp; /* get expected result */
983 00022874 0d effffff7a2 50 movl _index,r0
984 0002287B 48 03 50 50 shll $3,r0,r0
985 0002287F 0d e000000004 effffff792 movl _sinf_1_data+4(r0),_sgl_expected
986 0002288A # /*
987 0002288A # * If LOOP ON ERROR is set, this is the loop for this subtest.
988 0002288A # * The force loop flag is set after the first error.
989 0002288A # */
990 0002288A # asm("_sinf_6_lp1:");
991 0002288A _sinf_6_lp1:
992 0002288A # asm("movl $0,r0"); /* clear r0 */
993 0002288A 0d 00 50 movl $0,r0
994 0002288D # asm("ldf _sgl_ld_acc"); /* load the Acc. */
995 0002288D 06 effffff789 ldf _sgl_ld_acc
996 00022893 # asm("sinf"); /* get the sine */
997 00022893 05 sinf
998 00022894 # asm("addf r0"); /* add a zero to the acc */
999 00022894 c6 50 addf r0
1000 00022896 # asm("stf _sgl_st_acc"); /* store the result */
1001 00022896 26 effffff780 stf _sgl_st_acc
1002 0002289C # if( force_loop )
1003 0002289C 5d effffff77a tstl _force_loop
1004 000228A2 31 02 jeql L339
1005 000228A4 # asm("brb _sinf_6_lp1");; /* loop on the error */
1006 000228A4 11 e4 brb _sinf_6_lp1
1007 000228A6 L339:
1008 000228A6 # /*
1009 000228A6 # * end error loop - test the results
1010 000228A6 # */
1011 000228A6 # if( sgl_st_acc != sgl_expected ) { /* COMPARE the values */
1012 000228A6 1d effffff770 effffff76b cmpl _sgl_st_acc,_sgl_expected
1013 000228B1 21 03 13 00cf jeql L340
1014 000228B6 # errcnt++; /* bump the error count */
1015 000228B6 6d effffff760 incl _errcnt
1016 000228BC # if( prt_error ) {
1017 000228BC 5d effffff75a tstl _prt_error
1018 000228C2 21 03 13 009b jeql L341
1019 000228C7 # writes(" \n"); /* start a new print line */
1020 000228C7 .data 1
1021 00000ca9 * L342:
1022 00000ca9 * 200A00 .ascii " \12\0"
1023 00000cac * .text
1024 000228C7 dd 8f00000ca9 pushl $L342
1025 000228CD fe 08 effffff748 callf $8,_writes
1026 000228D4 # writes("cycle: ");
1027 000228D4 .data 1
1028 00000cac * L343:
1029 00000cac * 6379636C653A2000 .ascii "cycle: \0"
1030 00000cb4 * .text
1031 000228D4 dd 8f00000cac pushl $L343
1032 000228DA fe 08 effffff73b callf $8,_writes
1033 000228E1 # writed( cycle );
1034 000228E1 dd effffff735 pushl _cycle
1035 000228E7 fe 08 effffff72e callf $8,_writed
1036 000228EE # writes(" SINF test ");
1037 000228EE .data 1
1038 00000cb4 * L344:
1039 00000cb4 * 20202053494E4620746573742 .ascii " SINF test \0"
000
1040 00000cc2 * .text
1041 000228EE dd 8f00000cb4 pushl $L344
1042 000228F4 fe 08 effffff721 callf $8,_writes
1043 000228FB # writed( test_no );
1044 000228FB dd effffff71b pushl _test_no
1045 00022901 fe 08 effffff714 callf $8,_writed
1046 00022908 # writes(", subtest 6 (Piped Exit) - BAD FINAL ACC\n");
1047 00022908 .data 1
1048 00000cc2 * L345:
1049 00000cc2 * 2C20737562746573742036202 .ascii ", subtest 6 (Piped Exit) - BAD FINAL ACC\12\0"
8506970656420457869742920
2D204241442046494E414C204
143430A00
1050 00000cec * .text
1051 00022908 dd 8f00000cc2 pushl $L345
1052 0002290E fe 08 effffff707 callf $8,_writes
1053 00022915 # print_sinf_data();
1054 00022915 fe 04 ef00000076 callf $4,_print_sinf_data
1055 0002291C # writes(", data index = ");
1056 0002291C .data 1
1057 00000cec * L346:
1058 00000cec * 2C20206461746120696E64657 .ascii ", data index = \0"
8203D2000
1059 00000cfd * .text
1060 0002291C dd 8f00000cec pushl $L346
1061 00022922 fe 08 effffff6f3 callf $8,_writes
1062 00022929 # writed( index );
1063 00022929 dd effffff6ed pushl _index
1064 0002292F fe 08 effffff6e6 callf $8,_writed
1065 00022936 # writec('\n');
1066 00022936 dd 0a pushl $10
1067 00022938 fe 08 effffff6dd callf $8,_writec
1068 0002293F # writes(" Acc expected = ");
1069 0002293F .data 1
1070 00000cfd * L347:
1071 00000cfd * 2020202020202020202020202 .ascii " Acc expected = \0"
0202020202020202020416363
206578706563746564203D200
0
1072 00000d23 * .text
1073 0002293F dd 8f00000cfd pushl $L347
1074 00022945 fe 08 effffff6d0 callf $8,_writes
1075 0002294C # write32h( sgl_expected );
1076 0002294C dd effffff6ca pushl _sgl_expected
1077 00022952 fe 08 effffff6c3 callf $8,_write32h
1078 00022959 # writec('\n');
1079 00022959 dd 0a pushl $10
1080 0002295B fe 08 effffff6ba callf $8,_writec
1081 00022962 # }
1082 00022962 # if( halt_flg )
1083 00022962 L341:
1084 00022962 5d effffff6b4 tstl _halt_flg
1085 00022968 31 09 jeql L348
1086 0002296A # sinf_er_halt( BAD_ACC_HLT ); /* halt on the error */
1087 0002296A dd 01 pushl $1
1088 0002296C fe 08 ef0000005b callf $8,_sinf_er_halt
1089 00022973 # if( loop_on_err ) {
1090 00022973 L348:
1091 00022973 5d effffff6a3 tstl _loop_on_err
1092 00022979 31 0a jeql L349
1093 0002297B # force_loop = TRUE; /* set the force loop flag */
1094 0002297B 0d 01 effffff69a movl $1,_force_loop
1095 00022982 # asm("brw _sinf_6_lp1");; /* and loop on the error */
1096 00022982 13 ff05 brw _sinf_6_lp1
1097 00022985 # } /* end of loop on error */
1098 00022985 # } /* end of compare error */
1099 00022985 L349:
1100 00022985 # } /* end of WHILE loop */
1101 00022985 L340:
1102 00022985 L336:
1103 00022985 6d effffff691 incl _index
1104 0002298B 13 fec0 jbr L338
1105 0002298E L337:
1106 0002298E # } /* end of subtest 6 */
1107 0002298E 40 ret#2
1108 0002298F .set L332,0x0
1109 0002298F L334:
1110 0002298F 13 fea9 jbr L335
1111 00022992 .data
1112 00000a5c * .text
1113 00022992 .align 1
1114 00022992 .globl _print_sinf_data
1115 00022992 _print_sinf_data:
1116 00022992 0000 .word L350
1117 00022994 #
1118 00022994 #
1119 00022994 # /**************************************************************************
1120 00022994 # *
1121 00022994 # * PRINT THE DATA AND STORE RESULTS
1122 00022994 # *
1123 00022994 # * initial Acc = xxxxxxxx, stored = xxxxxxxx, data index = xx
1124 00022994 # * Acc expected = xxxxxxxx
1125 00022994 # **************************************************************************/
1126 00022994 # print_sinf_data()
1127 00022994 # {
1128 00022994 11 35 jbr L352
1129 00022996 L353:
1130 00022996 # writes("initial Acc = ");
1131 00022996 .data 1
1132 00000d23 * L354:
1133 00000d23 * 696E697469616C20416363203 .ascii "initial Acc = \0"
D2000
1134 00000d32 * .text
1135 00022996 dd 8f00000d23 pushl $L354
1136 0002299C fe 08 effffff679 callf $8,_writes
1137 000229A3 # write32h( sgl_ld_acc );
1138 000229A3 dd effffff673 pushl _sgl_ld_acc
1139 000229A9 fe 08 effffff66c callf $8,_write32h
1140 000229B0 # writes(", final Acc = ");
1141 000229B0 .data 1
1142 00000d32 * L355:
1143 00000d32 * 2C202066696E616C204163632 .ascii ", final Acc = \0"
03D2000
1144 00000d42 * .text
1145 000229B0 dd 8f00000d32 pushl $L355
1146 000229B6 fe 08 effffff65f callf $8,_writes
1147 000229BD # write32h( sgl_st_acc );
1148 000229BD dd effffff659 pushl _sgl_st_acc
1149 000229C3 fe 08 effffff652 callf $8,_write32h
1150 000229CA # }
1151 000229CA 40 ret#2
1152 000229CB .set L350,0x0
1153 000229CB L352:
1154 000229CB 11 c9 jbr L353
1155 000229CD .data
1156 00000a5c * .text
1157 000229CD 00 .align 1
1158 000229CE .globl _sinf_er_halt
1159 000229CE _sinf_er_halt:
1160 000229CE 0000 .word L356
1161 000229D0 #
1162 000229D0 #
1163 000229D0 #
1164 000229D0 # /**************************************************************************
1165 000229D0 # *
1166 000229D0 # * HALT ON ERROR ROUTINE
1167 000229D0 # *
1168 000229D0 # **************************************************************************/
1169 000229D0 # sinf_er_halt( halt_code )
1170 000229D0 # int halt_code;
1171 000229D0 # {
1172 000229D0 13 00a0 jbr L358
1173 000229D3 L359:
1174 000229D3 # sgl_dummy1 = halt_code; /* get the error type */
1175 000229D3 0d ad04 effffff641 movl 4(fp),_sgl_dummy1
1176 000229DB # asm("movl _test_no,r0"); /* r0 = test number */
1177 000229DB 0d effffff63b 50 movl _test_no,r0
1178 000229E2 # asm("movl _subtest,r1"); /* r1 = subtest number */
1179 000229E2 0d effffff634 51 movl _subtest,r1
1180 000229E9 # asm("movl _sgl_dummy1,r2"); /* r2 = error code */
1181 000229E9 0d effffff62d 52 movl _sgl_dummy1,r2
1182 000229F0 # asm("movl _cycle,r3"); /* r3 = cycle count */
1183 000229F0 0d effffff626 53 movl _cycle,r3
1184 000229F7 # asm("movl _sgl_ld_acc,r4"); /* r4 = initial data */
1185 000229F7 0d effffff61f 54 movl _sgl_ld_acc,r4
1186 000229FE # asm("movl _sgl_st_acc,r5"); /* r5 = data stored */
1187 000229FE 0d effffff618 55 movl _sgl_st_acc,r5
1188 00022A05 # asm("movl _sgl_expected,r6"); /* r6 = data expected */
1189 00022A05 0d effffff611 56 movl _sgl_expected,r6
1190 00022A0C # asm("movl _index,r7"); /* r7 = data index */
1191 00022A0C 0d effffff60a 57 movl _index,r7
1192 00022A13 # if( halt_code == BAD_REG_HLT ) {
1193 00022A13 1d ad04 02 cmpl 4(fp),$2
1194 00022A17 21 3d jneq L360
1195 00022A19 # sgl_dummy1 = load_regs[index2];
1196 00022A19 0d effffff5fd 50 movl _index2,r0
1197 00022A20 0d 40effffff5f5 movl _load_regs[r0],_sgl_dummy1
effffff5f0
1198 00022A2C # sgl_dummy2 = store_regs[index2];
1199 00022A2C 0d effffff5ea 50 movl _index2,r0
1200 00022A33 0d 40effffff5e2 movl _store_regs[r0],_sgl_dummy2
effffff5dd
1201 00022A3F # asm("movl _index2,r6"); /* r6 = bad register # */
1202 00022A3F 0d effffff5d7 56 movl _index2,r6
1203 00022A46 # asm("movl _sgl_dummy2,r7"); /* r7 = actual value */
1204 00022A46 0d effffff5d0 57 movl _sgl_dummy2,r7
1205 00022A4D # asm("movl _sgl_dummy1,r8"); /* r8 = expected value */
1206 00022A4D 0d effffff5c9 58 movl _sgl_dummy1,r8
1207 00022A54 # } else
1208 00022A54 11 1b jbr L361
1209 00022A56 L360:
1210 00022A56 # if( halt_code == BAD_PSL_HLT ) {
1211 00022A56 1d ad04 03 cmpl 4(fp),$3
1212 00022A5A 21 15 jneq L362
1213 00022A5C # asm("movl _init_psl,r6"); /* r6 = initial PSL */
1214 00022A5C 0d effffff5ba 56 movl _init_psl,r6
1215 00022A63 # asm("movl _psl_val,r7"); /* r7 = final PSL */
1216 00022A63 0d effffff5b3 57 movl _psl_val,r7
1217 00022A6A # asm("movl _exp_psl,r8"); /* r8 = expected PSL */
1218 00022A6A 0d effffff5ac 58 movl _exp_psl,r8
1219 00022A71 # };
1220 00022A71 L362:
1221 00022A71 L361:
1222 00022A71 # asm("halt"); /* HALT ... */
1223 00022A71 00 halt
1224 00022A72 # }
1225 00022A72 40 ret#2
1226 00022A73 .set L356,0x0
1227 00022A73 L358:
1228 00022A73 13 ff5d jbr L359
1229 00022A76 .data
1229 00044A92 .data
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