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Up to [Power 6/32 Unix Tahoe 4.2BSD] / cci / d / macro4|
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1.1 root 1: 1 00000000 LL0:
2: 2 00000000 .data
3: 3 00000d28 * .text
4: 4 00000000 .align 1
5: 5 00000000 .globl _subd
6: 6 00000000 _subd:
7: 7 00017588 0000 .word L215
8: 8 0001758A #
9: 9 0001758A #
10: 10 0001758A # #include "fpp_defs.h"
11: 11 0001758A #
12: 12 0001758A #
13: 13 0001758A # /*****************************************************************************
14: 14 0001758A # *
15: 15 0001758A # * SUBD - DOUBLE PRECISION FLOATING POINT SUBTRACT TEST
16: 16 0001758A # *
17: 17 0001758A # *****************************************************************************/
18: 18 0001758A # subd()
19: 19 0001758A # {
20: 20 0001758A 11 7a jbr L217
21: 21 0001758C L218:
22: 22 0001758C # asm(".globl _subd_t");
23: 23 0001758C .globl _subd_t
24: 24 0001758C # asm("_subd_t:"); /* entry address */
25: 25 0001758C _subd_t:
26: 26 0001758C # if( (cycle == 1) && (prt_hdrs) ) /* print headers on 1st cycle */
27: 27 0001758C 1d effffffff6 01 cmpl _cycle,$1
28: 28 00017593 21 15 jneq L219
29: 29 00017595 5d efffffffed tstl _prt_hdrs
30: 30 0001759B 31 0d jeql L219
31: 31 0001759D # writes(" SUBD");
32: 32 0001759D .data 1
33: 33 00000d28 * L221:
34: 34 00000d28 * 205355424400 .ascii " SUBD\0"
35: 35 00000d2e * .text
36: 36 0001759D dd 8f00000d28 pushl $L221
37: 37 000175A3 fe 08 efffffffde callf $8,_writes
38: 38 000175AA # subd_1(); /* sub through a register */
39: 39 000175AA L219:
40: 40 000175AA fe 04 ef00000057 callf $4,_subd_1
41: 41 000175B1 # subd_2(); /* sub through the cache */
42: 42 000175B1 fe 04 ef000001b2 callf $4,_subd_2
43: 43 000175B8 # subd_3(); /* wait 1 NOP before storeing */
44: 44 000175B8 fe 04 ef000002f9 callf $4,_subd_3
45: 45 000175BF # for( nop_cnt = 3; nop_cnt > 0; nop_cnt-- )
46: 46 000175BF 0d 03 efffffffc2 movl $3,_nop_cnt
47: 47 000175C6 L227:
48: 48 000175C6 5d efffffffbc tstl _nop_cnt
49: 49 000175CC 51 15 jleq L226
50: 50 000175CE # subd_3(nop_cnt); /* wait 6 ... 2 NOPs */
51: 51 000175CE dd efffffffb4 pushl _nop_cnt
52: 52 000175D4 fe 08 ef000002dd callf $8,_subd_3
53: 53 000175DB L225:
54: 54 000175DB 7d efffffffa7 decl _nop_cnt
55: 55 000175E1 11 e3 jbr L227
56: 56 000175E3 L226:
57: 57 000175E3 # subd_4(); /* wait 3 NOPs */
58: 58 000175E3 fe 04 ef00000456 callf $4,_subd_4
59: 59 000175EA # subd_5(); /* wait 1 NOP before storing */
60: 60 000175EA fe 04 ef000005a1 callf $4,_subd_5
61: 61 000175F1 # subd_6(); /* register stability test */
62: 62 000175F1 fe 04 ef000006ea callf $4,_subd_6
63: 63 000175F8 # subd_7(); /* PSL stability test */
64: 64 000175F8 fe 04 ef000008b3 callf $4,_subd_7
65: 65 000175FF # asm("jmp *return"); /* return to the test monitor */
66: 66 000175FF 71 ffffffff83 jmp *return
67: 67 00017605 # }
68: 68 00017605 40 ret#2
69: 69 00017606 .set L215,0x0
70: 70 00017606 L217:
71: 71 00017606 11 84 jbr L218
72: 72 00017608 .data
73: 73 00000d28 * .text
74: 74 00017608 .align 1
75: 75 00017608 .globl _subd_1
76: 76 00017608 _subd_1:
77: 77 00017608 0000 .word L232
78: 78 0001760A #
79: 79 0001760A #
80: 80 0001760A #
81: 81 0001760A # /************************************************************************
82: 82 0001760A # *
83: 83 0001760A # * SUBTEST 1 - subtract through a register
84: 84 0001760A # *
85: 85 0001760A # ************************************************************************/
86: 86 0001760A # subd_1()
87: 87 0001760A # {
88: 88 0001760A 13 015a jbr L234
89: 89 0001760D L235:
90: 90 0001760D # force_loop = FALSE;
91: 91 0001760D 4d efffffff75 clrl _force_loop
92: 92 00017613 # subtest = 1;
93: 93 00017613 0d 01 efffffff6e movl $1,_subtest
94: 94 0001761A # for( index = 0; index < max_subd_1_index; index++ ) {
95: 95 0001761A 4d efffffff68 clrl _index
96: 96 00017620 L238:
97: 97 00017620 1d efffffff62 efffffff5d cmpl _index,_max_subd_1_index
98: 98 0001762B 91 03 13 0136 jgeq L237
99: 99 00017630 # dbl_ld_acc = subd_1_data[index].op_1; /* get operand 1 */
100: 100 00017630 5c 18 efffffff51 50 mull3 $24,_index,r0
101: 101 00017638 0c 8f00000000 50 addl2 $_subd_1_data,r0
102: 102 0001763F 0d a004 efffffff45 movl 4(r0),_dbl_ld_acc+4
103: 103 00017647 0d 60 efffffff3a movl (r0),_dbl_ld_acc
104: 104 0001764E # dbl_value_1 = subd_1_data[index].op_2; /* get operand 2 */
105: 105 0001764E 5c 18 efffffff33 50 mull3 $24,_index,r0
106: 106 00017656 0c 8f00000008 50 addl2 $_subd_1_data+8,r0
107: 107 0001765D 0d a004 efffffff27 movl 4(r0),_dbl_value_1+4
108: 108 00017665 0d 60 efffffff1c movl (r0),_dbl_value_1
109: 109 0001766C # dbl_expected = subd_1_data[index].exp; /* get expected result */
110: 110 0001766C 5c 18 efffffff15 50 mull3 $24,_index,r0
111: 111 00017674 0c 8f00000010 50 addl2 $_subd_1_data+16,r0
112: 112 0001767B 0d a004 efffffff09 movl 4(r0),_dbl_expected+4
113: 113 00017683 0d 60 effffffefe movl (r0),_dbl_expected
114: 114 0001768A # /*
115: 115 0001768A # * If LOOP ON ERROR is set, this is the loop for this subtest.
116: 116 0001768A # * The force loop flag is set after the first error.
117: 117 0001768A # */
118: 118 0001768A # asm("_subd_1_lp1:");
119: 119 0001768A _subd_1_lp1:
120: 120 0001768A # asm("movl _dbl_ld_acc,r2"); /* move operand 1 to r2/r3 */
121: 121 0001768A 0d effffffef8 52 movl _dbl_ld_acc,r2
122: 122 00017691 # asm("movl _dbl_ld_acc+4,r3");
123: 123 00017691 0d effffffef5 53 movl _dbl_ld_acc+4,r3
124: 124 00017698 # asm("movl _dbl_value_1,r4"); /* move operand 2 to r4/r5 */
125: 125 00017698 0d effffffeea 54 movl _dbl_value_1,r4
126: 126 0001769F # asm("movl _dbl_value_1+4,r5");
127: 127 0001769F 0d effffffee7 55 movl _dbl_value_1+4,r5
128: 128 000176A6 # asm("ldd r2"); /* load the 1st operand */
129: 129 000176A6 07 52 ldd r2
130: 130 000176A8 # asm("subd r4"); /* subtract the 2nd operand*/
131: 131 000176A8 d7 54 subd r4
132: 132 000176AA # asm("std _dbl_st_acc"); /* store the result */
133: 133 000176AA 27 effffffed8 std _dbl_st_acc
134: 134 000176B0 # if( force_loop )
135: 135 000176B0 5d effffffed2 tstl _force_loop
136: 136 000176B6 31 02 jeql L239
137: 137 000176B8 # asm("brb _subd_1_lp1");; /* loop on the error */
138: 138 000176B8 11 d0 brb _subd_1_lp1
139: 139 000176BA L239:
140: 140 000176BA # /*
141: 141 000176BA # * end error loop - test the results
142: 142 000176BA # */
143: 143 000176BA # if( (dbl_st_acc.m != dbl_expected.m) || /* verify the results */
144: 144 000176BA # (dbl_st_acc.l != dbl_expected.l) ) {
145: 145 000176BA 1d effffffec8 effffffec3 cmpl _dbl_st_acc,_dbl_expected
146: 146 000176C5 21 10 jneq L9999
147: 147 000176C7 1d effffffebf effffffeba cmpl _dbl_st_acc+4,_dbl_expected+4
148: 148 000176D2 21 03 13 0086 jeql L240
149: 149 000176D7 L9999:
150: 150 000176D7 # errcnt++; /* bump the error count */
151: 151 000176D7 6d effffffeab incl _errcnt
152: 152 000176DD # if( prt_error ) {
153: 153 000176DD 5d effffffea5 tstl _prt_error
154: 154 000176E3 31 55 jeql L241
155: 155 000176E5 # writes(" \n"); /* start a new print line */
156: 156 000176E5 .data 1
157: 157 00000d2e * L242:
158: 158 00000d2e * 200A00 .ascii " \12\0"
159: 159 00000d31 * .text
160: 160 000176E5 dd 8f00000d2e pushl $L242
161: 161 000176EB fe 08 effffffe96 callf $8,_writes
162: 162 000176F2 # writes("cycle: ");
163: 163 000176F2 .data 1
164: 164 00000d31 * L243:
165: 165 00000d31 * 6379636C653A2000 .ascii "cycle: \0"
166: 166 00000d39 * .text
167: 167 000176F2 dd 8f00000d31 pushl $L243
168: 168 000176F8 fe 08 effffffe89 callf $8,_writes
169: 169 000176FF # writed( cycle );
170: 170 000176FF dd effffffe83 pushl _cycle
171: 171 00017705 fe 08 effffffe7c callf $8,_writed
172: 172 0001770C # writes(" SUBD test ");
173: 173 0001770C .data 1
174: 174 00000d39 * L245:
175: 175 00000d39 * 2020535542442074657374200 .ascii " SUBD test \0"
176: 0
177: 176 00000d46 * .text
178: 177 0001770C dd 8f00000d39 pushl $L245
179: 178 00017712 fe 08 effffffe6f callf $8,_writes
180: 179 00017719 # writed( test_no );
181: 180 00017719 dd effffffe69 pushl _test_no
182: 181 0001771F fe 08 effffffe62 callf $8,_writed
183: 182 00017726 # writes(", subtest 1 (Reg. Data) - BAD FINAL ACC\n");
184: 183 00017726 .data 1
185: 184 00000d46 * L246:
186: 185 00000d46 * 2C20737562746573742031202 .ascii ", subtest 1 (Reg. Data) - BAD FINAL ACC\12\0"
187: 85265672E204461746129202D
188: 204241442046494E414C20414
189: 3430A00
190: 186 00000d6f * .text
191: 187 00017726 dd 8f00000d46 pushl $L246
192: 188 0001772C fe 08 effffffe55 callf $8,_writes
193: 189 00017733 # print_subd_data();
194: 190 00017733 fe 04 ef00000952 callf $4,_print_subd_data
195: 191 0001773A # }
196: 192 0001773A # if( halt_flg )
197: 193 0001773A L241:
198: 194 0001773A 5d effffffe48 tstl _halt_flg
199: 195 00017740 31 09 jeql L248
200: 196 00017742 # subd_er_halt( BAD_ACC_HLT ); /* halt on the error */
201: 197 00017742 dd 01 pushl $1
202: 198 00017744 fe 08 ef00000a37 callf $8,_subd_er_halt
203: 199 0001774B # if( loop_on_err ) {
204: 200 0001774B L248:
205: 201 0001774B 5d effffffe37 tstl _loop_on_err
206: 202 00017751 31 0a jeql L250
207: 203 00017753 # force_loop = TRUE; /* set the force loop flag */
208: 204 00017753 0d 01 effffffe2e movl $1,_force_loop
209: 205 0001775A # asm("brw _subd_1_lp1");; /* and loop on the error */
210: 206 0001775A 13 ff2d brw _subd_1_lp1
211: 207 0001775D # } /* end of loop on error */
212: 208 0001775D # } /* end of compare error */
213: 209 0001775D L250:
214: 210 0001775D # } /* end of WHILE loop */
215: 211 0001775D L240:
216: 212 0001775D L236:
217: 213 0001775D 6d effffffe25 incl _index
218: 214 00017763 13 feba jbr L238
219: 215 00017766 L237:
220: 216 00017766 # } /* end of subtest 1 */
221: 217 00017766 40 ret#2
222: 218 00017767 .set L232,0x0
223: 219 00017767 L234:
224: 220 00017767 13 fea3 jbr L235
225: 221 0001776A .data
226: 222 00000d28 * .text
227: 223 0001776A .align 1
228: 224 0001776A .globl _subd_2
229: 225 0001776A _subd_2:
230: 226 0001776A 0000 .word L251
231: 227 0001776C #
232: 228 0001776C #
233: 229 0001776C #
234: 230 0001776C # /************************************************************************
235: 231 0001776C # *
236: 232 0001776C # * SUBTEST 2 - subtract through memory
237: 233 0001776C # *
238: 234 0001776C # ************************************************************************/
239: 235 0001776C # subd_2()
240: 236 0001776C # {
241: 237 0001776C 13 0146 jbr L253
242: 238 0001776F L254:
243: 239 0001776F # force_loop = FALSE;
244: 240 0001776F 4d effffffe13 clrl _force_loop
245: 241 00017775 # subtest = 2;
246: 242 00017775 0d 02 effffffe0c movl $2,_subtest
247: 243 0001777C # for( index = 0; index < max_subd_1_index; index++ ) {
248: 244 0001777C 4d effffffe06 clrl _index
249: 245 00017782 L257:
250: 246 00017782 1d effffffe00 effffffdfb cmpl _index,_max_subd_1_index
251: 247 0001778D 91 03 13 0122 jgeq L256
252: 248 00017792 # dbl_ld_acc = subd_1_data[index].op_1; /* get operand 1 */
253: 249 00017792 5c 18 effffffdef 50 mull3 $24,_index,r0
254: 250 0001779A 0c 8f00000000 50 addl2 $_subd_1_data,r0
255: 251 000177A1 0d a004 effffffde3 movl 4(r0),_dbl_ld_acc+4
256: 252 000177A9 0d 60 effffffdd8 movl (r0),_dbl_ld_acc
257: 253 000177B0 # dbl_value_1 = subd_1_data[index].op_2; /* get operand 2 */
258: 254 000177B0 5c 18 effffffdd1 50 mull3 $24,_index,r0
259: 255 000177B8 0c 8f00000008 50 addl2 $_subd_1_data+8,r0
260: 256 000177BF 0d a004 effffffdc5 movl 4(r0),_dbl_value_1+4
261: 257 000177C7 0d 60 effffffdba movl (r0),_dbl_value_1
262: 258 000177CE # dbl_expected = subd_1_data[index].exp; /* get expected result */
263: 259 000177CE 5c 18 effffffdb3 50 mull3 $24,_index,r0
264: 260 000177D6 0c 8f00000010 50 addl2 $_subd_1_data+16,r0
265: 261 000177DD 0d a004 effffffda7 movl 4(r0),_dbl_expected+4
266: 262 000177E5 0d 60 effffffd9c movl (r0),_dbl_expected
267: 263 000177EC # /*
268: 264 000177EC # * If LOOP ON ERROR is set, this is the loop for this subtest.
269: 265 000177EC # * The force loop flag is set after the first error.
270: 266 000177EC # */
271: 267 000177EC # asm("_subd_2_lp1:");
272: 268 000177EC _subd_2_lp1:
273: 269 000177EC # asm("ldd _dbl_ld_acc"); /* load the 1st operand */
274: 270 000177EC 07 effffffd96 ldd _dbl_ld_acc
275: 271 000177F2 # asm("subd _dbl_value_1"); /* subtract the 2nd operand*/
276: 272 000177F2 d7 effffffd90 subd _dbl_value_1
277: 273 000177F8 # asm("std _dbl_st_acc"); /* store the result */
278: 274 000177F8 27 effffffd8a std _dbl_st_acc
279: 275 000177FE # if( force_loop )
280: 276 000177FE 5d effffffd84 tstl _force_loop
281: 277 00017804 31 02 jeql L258
282: 278 00017806 # asm("brb _subd_2_lp1");; /* loop on the error */
283: 279 00017806 11 e4 brb _subd_2_lp1
284: 280 00017808 L258:
285: 281 00017808 # /*
286: 282 00017808 # * end error loop - test the results
287: 283 00017808 # */
288: 284 00017808 # if( (dbl_st_acc.m != dbl_expected.m) || /* verify the results */
289: 285 00017808 # (dbl_st_acc.l != dbl_expected.l) ) {
290: 286 00017808 1d effffffd7a effffffd75 cmpl _dbl_st_acc,_dbl_expected
291: 287 00017813 21 10 jneq L9998
292: 288 00017815 1d effffffd71 effffffd6c cmpl _dbl_st_acc+4,_dbl_expected+4
293: 289 00017820 21 03 13 0086 jeql L259
294: 290 00017825 L9998:
295: 291 00017825 # errcnt++; /* bump the error count */
296: 292 00017825 6d effffffd5d incl _errcnt
297: 293 0001782B # if( prt_error ) {
298: 294 0001782B 5d effffffd57 tstl _prt_error
299: 295 00017831 31 55 jeql L260
300: 296 00017833 # writes(" \n"); /* start a new print line */
301: 297 00017833 .data 1
302: 298 00000d6f * L261:
303: 299 00000d6f * 200A00 .ascii " \12\0"
304: 300 00000d72 * .text
305: 301 00017833 dd 8f00000d6f pushl $L261
306: 302 00017839 fe 08 effffffd48 callf $8,_writes
307: 303 00017840 # writes("cycle: ");
308: 304 00017840 .data 1
309: 305 00000d72 * L262:
310: 306 00000d72 * 6379636C653A2000 .ascii "cycle: \0"
311: 307 00000d7a * .text
312: 308 00017840 dd 8f00000d72 pushl $L262
313: 309 00017846 fe 08 effffffd3b callf $8,_writes
314: 310 0001784D # writed( cycle );
315: 311 0001784D dd effffffd35 pushl _cycle
316: 312 00017853 fe 08 effffffd2e callf $8,_writed
317: 313 0001785A # writes(" SUBD test ");
318: 314 0001785A .data 1
319: 315 00000d7a * L263:
320: 316 00000d7a * 2020535542442074657374200 .ascii " SUBD test \0"
321: 0
322: 317 00000d87 * .text
323: 318 0001785A dd 8f00000d7a pushl $L263
324: 319 00017860 fe 08 effffffd21 callf $8,_writes
325: 320 00017867 # writed( test_no );
326: 321 00017867 dd effffffd1b pushl _test_no
327: 322 0001786D fe 08 effffffd14 callf $8,_writed
328: 323 00017874 # writes(", subtest 2 (Cache Data) - BAD FINAL ACC\n");
329: 324 00017874 .data 1
330: 325 00000d87 * L264:
331: 326 00000d87 * 2C20737562746573742032202 .ascii ", subtest 2 (Cache Data) - BAD FINAL ACC\12\0"
332: 8436163686520446174612920
333: 2D204241442046494E414C204
334: 143430A00
335: 327 00000db1 * .text
336: 328 00017874 dd 8f00000d87 pushl $L264
337: 329 0001787A fe 08 effffffd07 callf $8,_writes
338: 330 00017881 # print_subd_data();
339: 331 00017881 fe 04 ef00000804 callf $4,_print_subd_data
340: 332 00017888 # }
341: 333 00017888 # if( halt_flg )
342: 334 00017888 L260:
343: 335 00017888 5d effffffcfa tstl _halt_flg
344: 336 0001788E 31 09 jeql L265
345: 337 00017890 # subd_er_halt( BAD_ACC_HLT ); /* halt on the error */
346: 338 00017890 dd 01 pushl $1
347: 339 00017892 fe 08 ef000008e9 callf $8,_subd_er_halt
348: 340 00017899 # if( loop_on_err ) {
349: 341 00017899 L265:
350: 342 00017899 5d effffffce9 tstl _loop_on_err
351: 343 0001789F 31 0a jeql L266
352: 344 000178A1 # force_loop = TRUE; /* set the force loop flag */
353: 345 000178A1 0d 01 effffffce0 movl $1,_force_loop
354: 346 000178A8 # asm("brw _subd_2_lp1");; /* and loop on the error */
355: 347 000178A8 13 ff41 brw _subd_2_lp1
356: 348 000178AB # } /* end of loop on error */
357: 349 000178AB # } /* end of compare error */
358: 350 000178AB L266:
359: 351 000178AB # } /* end of WHILE loop */
360: 352 000178AB L259:
361: 353 000178AB L255:
362: 354 000178AB 6d effffffcd7 incl _index
363: 355 000178B1 13 fece jbr L257
364: 356 000178B4 L256:
365: 357 000178B4 # } /* end of subtest 2 */
366: 358 000178B4 40 ret#2
367: 359 000178B5 .set L251,0x0
368: 360 000178B5 L253:
369: 361 000178B5 13 feb7 jbr L254
370: 362 000178B8 .data
371: 363 00000d28 * .text
372: 364 000178B8 .align 1
373: 365 000178B8 .globl _subd_3
374: 366 000178B8 _subd_3:
375: 367 000178B8 0000 .word L267
376: 368 000178BA #
377: 369 000178BA #
378: 370 000178BA #
379: 371 000178BA # /****************************************************************************
380: 372 000178BA # *
381: 373 000178BA # * SUBTEST 3 - Wait 2n NOPs before storing the results
382: 374 000178BA # *
383: 375 000178BA # ****************************************************************************/
384: 376 000178BA # subd_3( count )
385: 377 000178BA # int count; /* wait "count" * 2 NOPs */
386: 378 000178BA # {
387: 379 000178BA 13 0180 jbr L269
388: 380 000178BD L270:
389: 381 000178BD # force_loop = FALSE;
390: 382 000178BD 4d effffffcc5 clrl _force_loop
391: 383 000178C3 # subtest = 3;
392: 384 000178C3 0d 03 effffffcbe movl $3,_subtest
393: 385 000178CA # sgl_dummy2 = count; /* get the NOP count */
394: 386 000178CA 0d ad04 effffffcb6 movl 4(fp),_sgl_dummy2
395: 387 000178D2 # for( index = 0; index < max_subd_1_index; index++ ) {
396: 388 000178D2 4d effffffcb0 clrl _index
397: 389 000178D8 L273:
398: 390 000178D8 1d effffffcaa effffffca5 cmpl _index,_max_subd_1_index
399: 391 000178E3 91 03 13 0154 jgeq L272
400: 392 000178E8 # dbl_ld_acc = subd_1_data[index].op_1; /* get operand 1 */
401: 393 000178E8 5c 18 effffffc99 50 mull3 $24,_index,r0
402: 394 000178F0 0c 8f00000000 50 addl2 $_subd_1_data,r0
403: 395 000178F7 0d a004 effffffc8d movl 4(r0),_dbl_ld_acc+4
404: 396 000178FF 0d 60 effffffc82 movl (r0),_dbl_ld_acc
405: 397 00017906 # dbl_value_1 = subd_1_data[index].op_2; /* get operand 2 */
406: 398 00017906 5c 18 effffffc7b 50 mull3 $24,_index,r0
407: 399 0001790E 0c 8f00000008 50 addl2 $_subd_1_data+8,r0
408: 400 00017915 0d a004 effffffc6f movl 4(r0),_dbl_value_1+4
409: 401 0001791D 0d 60 effffffc64 movl (r0),_dbl_value_1
410: 402 00017924 # dbl_expected = subd_1_data[index].exp; /* get expected result */
411: 403 00017924 5c 18 effffffc5d 50 mull3 $24,_index,r0
412: 404 0001792C 0c 8f00000010 50 addl2 $_subd_1_data+16,r0
413: 405 00017933 0d a004 effffffc51 movl 4(r0),_dbl_expected+4
414: 406 0001793B 0d 60 effffffc46 movl (r0),_dbl_expected
415: 407 00017942 # /*
416: 408 00017942 # * If LOOP ON ERROR is set, this is the loop for this subtest.
417: 409 00017942 # * The force loop flag is set after the first error.
418: 410 00017942 # */
419: 411 00017942 # asm("_subd_3_lp1:");
420: 412 00017942 _subd_3_lp1:
421: 413 00017942 # asm("movl _sgl_dummy2,r0"); /* set the NOP count */
422: 414 00017942 0d effffffc40 50 movl _sgl_dummy2,r0
423: 415 00017949 # asm("ldd _dbl_ld_acc"); /* load the 1st operand */
424: 416 00017949 07 effffffc39 ldd _dbl_ld_acc
425: 417 0001794F # asm("nop"); /* delay */
426: 418 0001794F 10 nop
427: 419 00017950 # asm("subd _dbl_value_1"); /* subtract the 2nd operand*/
428: 420 00017950 d7 effffffc32 subd _dbl_value_1
429: 421 00017956 # asm("1:");
430: 422 00017956 1:
431: 423 00017956 # asm("decl r0"); /* decrement the NOP count */
432: 424 00017956 7d 50 decl r0
433: 425 00017958 # asm("bneq 1b"); /* till the count = 0 */
434: 426 00017958 21 fc bneq 1b
435: 427 0001795A # asm("std _dbl_st_acc"); /* store the result */
436: 428 0001795A 27 effffffc28 std _dbl_st_acc
437: 429 00017960 # if( force_loop )
438: 430 00017960 5d effffffc22 tstl _force_loop
439: 431 00017966 31 02 jeql L274
440: 432 00017968 # asm("brb _subd_3_lp1");; /* loop on the error */
441: 433 00017968 11 d8 brb _subd_3_lp1
442: 434 0001796A L274:
443: 435 0001796A # /*
444: 436 0001796A # * end error loop - test the results
445: 437 0001796A # */
446: 438 0001796A # if( (dbl_st_acc.m != dbl_expected.m) || /* verify the results */
447: 439 0001796A # (dbl_st_acc.l != dbl_expected.l) ) {
448: 440 0001796A 1d effffffc18 effffffc13 cmpl _dbl_st_acc,_dbl_expected
449: 441 00017975 21 10 jneq L9997
450: 442 00017977 1d effffffc0f effffffc0a cmpl _dbl_st_acc+4,_dbl_expected+4
451: 443 00017982 21 03 13 00ac jeql L275
452: 444 00017987 L9997:
453: 445 00017987 # errcnt++; /* bump the error count */
454: 446 00017987 6d effffffbfb incl _errcnt
455: 447 0001798D # if( prt_error ) {
456: 448 0001798D 5d effffffbf5 tstl _prt_error
457: 449 00017993 31 7b jeql L276
458: 450 00017995 # writes(" \n"); /* start a new print line */
459: 451 00017995 .data 1
460: 452 00000db1 * L277:
461: 453 00000db1 * 200A00 .ascii " \12\0"
462: 454 00000db4 * .text
463: 455 00017995 dd 8f00000db1 pushl $L277
464: 456 0001799B fe 08 effffffbe6 callf $8,_writes
465: 457 000179A2 # writes("cycle: ");
466: 458 000179A2 .data 1
467: 459 00000db4 * L278:
468: 460 00000db4 * 6379636C653A2000 .ascii "cycle: \0"
469: 461 00000dbc * .text
470: 462 000179A2 dd 8f00000db4 pushl $L278
471: 463 000179A8 fe 08 effffffbd9 callf $8,_writes
472: 464 000179AF # writed( cycle );
473: 465 000179AF dd effffffbd3 pushl _cycle
474: 466 000179B5 fe 08 effffffbcc callf $8,_writed
475: 467 000179BC # writes(" SUBD test ");
476: 468 000179BC .data 1
477: 469 00000dbc * L279:
478: 470 00000dbc * 2020535542442074657374200 .ascii " SUBD test \0"
479: 0
480: 471 00000dc9 * .text
481: 472 000179BC dd 8f00000dbc pushl $L279
482: 473 000179C2 fe 08 effffffbbf callf $8,_writes
483: 474 000179C9 # writed( test_no );
484: 475 000179C9 dd effffffbb9 pushl _test_no
485: 476 000179CF fe 08 effffffbb2 callf $8,_writed
486: 477 000179D6 # writes(", subtest 3 (wait ");
487: 478 000179D6 .data 1
488: 479 00000dc9 * L280:
489: 480 00000dc9 * 2C20737562746573742033202 .ascii ", subtest 3 (wait \0"
490: 8776169742000
491: 481 00000ddc * .text
492: 482 000179D6 dd 8f00000dc9 pushl $L280
493: 483 000179DC fe 08 effffffba5 callf $8,_writes
494: 484 000179E3 # sgl_dummy1 = 2*count;
495: 485 000179E3 48 01 ad04 50 shll $1,4(fp),r0
496: 486 000179E8 0d 50 effffffb99 movl r0,_sgl_dummy1
497: 487 000179EF # writed( sgl_dummy1 ); /* write the NOP count */
498: 488 000179EF dd effffffb93 pushl _sgl_dummy1
499: 489 000179F5 fe 08 effffffb8c callf $8,_writed
500: 490 000179FC # writes(" NOPs) - BAD FINAL ACC\n");
501: 491 000179FC .data 1
502: 492 00000ddc * L281:
503: 493 00000ddc * 204E4F507329202D204241442 .ascii " NOPs) - BAD FINAL ACC\12\0"
504: 046494E414C204143430A00
505: 494 00000df4 * .text
506: 495 000179FC dd 8f00000ddc pushl $L281
507: 496 00017A02 fe 08 effffffb7f callf $8,_writes
508: 497 00017A09 # print_subd_data();
509: 498 00017A09 fe 04 ef0000067c callf $4,_print_subd_data
510: 499 00017A10 # }
511: 500 00017A10 # if( halt_flg )
512: 501 00017A10 L276:
513: 502 00017A10 5d effffffb72 tstl _halt_flg
514: 503 00017A16 31 09 jeql L282
515: 504 00017A18 # subd_er_halt( BAD_ACC_HLT ); /* halt on the error */
516: 505 00017A18 dd 01 pushl $1
517: 506 00017A1A fe 08 ef00000761 callf $8,_subd_er_halt
518: 507 00017A21 # if( loop_on_err ) {
519: 508 00017A21 L282:
520: 509 00017A21 5d effffffb61 tstl _loop_on_err
521: 510 00017A27 31 0a jeql L283
522: 511 00017A29 # force_loop = TRUE; /* set the force loop flag */
523: 512 00017A29 0d 01 effffffb58 movl $1,_force_loop
524: 513 00017A30 # asm("brw _subd_3_lp1");; /* and loop on the error */
525: 514 00017A30 13 ff0f brw _subd_3_lp1
526: 515 00017A33 # } /* end of loop on error */
527: 516 00017A33 # } /* end of compare error */
528: 517 00017A33 L283:
529: 518 00017A33 # } /* end of WHILE loop */
530: 519 00017A33 L275:
531: 520 00017A33 L271:
532: 521 00017A33 6d effffffb4f incl _index
533: 522 00017A39 13 fe9c jbr L273
534: 523 00017A3C L272:
535: 524 00017A3C # } /* end of subtest 3 */
536: 525 00017A3C 40 ret#2
537: 526 00017A3D .set L267,0x0
538: 527 00017A3D L269:
539: 528 00017A3D 13 fe7d jbr L270
540: 529 00017A40 .data
541: 530 00000d28 * .text
542: 531 00017A40 .align 1
543: 532 00017A40 .globl _subd_4
544: 533 00017A40 _subd_4:
545: 534 00017A40 0000 .word L284
546: 535 00017A42 #
547: 536 00017A42 #
548: 537 00017A42 #
549: 538 00017A42 # /************************************************************************
550: 539 00017A42 # *
551: 540 00017A42 # * SUBTEST 4 - Wait 2 NOPs before storing the results
552: 541 00017A42 # *
553: 542 00017A42 # ************************************************************************/
554: 543 00017A42 # subd_4()
555: 544 00017A42 # {
556: 545 00017A42 13 0149 jbr L286
557: 546 00017A45 L287:
558: 547 00017A45 # force_loop = FALSE;
559: 548 00017A45 4d effffffb3d clrl _force_loop
560: 549 00017A4B # subtest = 4;
561: 550 00017A4B 0d 04 effffffb36 movl $4,_subtest
562: 551 00017A52 # for( index = 0; index < max_subd_1_index; index++ ) {
563: 552 00017A52 4d effffffb30 clrl _index
564: 553 00017A58 L290:
565: 554 00017A58 1d effffffb2a effffffb25 cmpl _index,_max_subd_1_index
566: 555 00017A63 91 03 13 0125 jgeq L289
567: 556 00017A68 # dbl_ld_acc = subd_1_data[index].op_1; /* get operand 1 */
568: 557 00017A68 5c 18 effffffb19 50 mull3 $24,_index,r0
569: 558 00017A70 0c 8f00000000 50 addl2 $_subd_1_data,r0
570: 559 00017A77 0d a004 effffffb0d movl 4(r0),_dbl_ld_acc+4
571: 560 00017A7F 0d 60 effffffb02 movl (r0),_dbl_ld_acc
572: 561 00017A86 # dbl_value_1 = subd_1_data[index].op_2; /* get operand 2 */
573: 562 00017A86 5c 18 effffffafb 50 mull3 $24,_index,r0
574: 563 00017A8E 0c 8f00000008 50 addl2 $_subd_1_data+8,r0
575: 564 00017A95 0d a004 effffffaef movl 4(r0),_dbl_value_1+4
576: 565 00017A9D 0d 60 effffffae4 movl (r0),_dbl_value_1
577: 566 00017AA4 # dbl_expected = subd_1_data[index].exp; /* get expected result */
578: 567 00017AA4 5c 18 effffffadd 50 mull3 $24,_index,r0
579: 568 00017AAC 0c 8f00000010 50 addl2 $_subd_1_data+16,r0
580: 569 00017AB3 0d a004 effffffad1 movl 4(r0),_dbl_expected+4
581: 570 00017ABB 0d 60 effffffac6 movl (r0),_dbl_expected
582: 571 00017AC2 # /*
583: 572 00017AC2 # * If LOOP ON ERROR is set, this is the loop for this subtest.
584: 573 00017AC2 # * The force loop flag is set after the first error.
585: 574 00017AC2 # */
586: 575 00017AC2 # asm("_subd_4_lp1:");
587: 576 00017AC2 _subd_4_lp1:
588: 577 00017AC2 # asm("ldd _dbl_ld_acc"); /* load the 1st operand */
589: 578 00017AC2 07 effffffac0 ldd _dbl_ld_acc
590: 579 00017AC8 # asm("nop"); /* delay */
591: 580 00017AC8 10 nop
592: 581 00017AC9 # asm("subd _dbl_value_1"); /* subtract the 2nd operand*/
593: 582 00017AC9 d7 effffffab9 subd _dbl_value_1
594: 583 00017ACF # asm("nop"); /* delay before ... */
595: 584 00017ACF 10 nop
596: 585 00017AD0 # asm("nop"); /* ... storing the result */
597: 586 00017AD0 10 nop
598: 587 00017AD1 # asm("std _dbl_st_acc"); /* store the result */
599: 588 00017AD1 27 effffffab1 std _dbl_st_acc
600: 589 00017AD7 # if( force_loop )
601: 590 00017AD7 5d effffffaab tstl _force_loop
602: 591 00017ADD 31 02 jeql L291
603: 592 00017ADF # asm("brb _subd_4_lp1");; /* loop on the error */
604: 593 00017ADF 11 e1 brb _subd_4_lp1
605: 594 00017AE1 L291:
606: 595 00017AE1 # /*
607: 596 00017AE1 # * end error loop - test the results
608: 597 00017AE1 # */
609: 598 00017AE1 # if( (dbl_st_acc.m != dbl_expected.m) || /* verify the results */
610: 599 00017AE1 # (dbl_st_acc.l != dbl_expected.l) ) {
611: 600 00017AE1 1d effffffaa1 effffffa9c cmpl _dbl_st_acc,_dbl_expected
612: 601 00017AEC 21 10 jneq L9996
613: 602 00017AEE 1d effffffa98 effffffa93 cmpl _dbl_st_acc+4,_dbl_expected+4
614: 603 00017AF9 21 03 13 0086 jeql L292
615: 604 00017AFE L9996:
616: 605 00017AFE # errcnt++; /* bump the error count */
617: 606 00017AFE 6d effffffa84 incl _errcnt
618: 607 00017B04 # if( prt_error ) {
619: 608 00017B04 5d effffffa7e tstl _prt_error
620: 609 00017B0A 31 55 jeql L293
621: 610 00017B0C # writes(" \n"); /* start a new print line */
622: 611 00017B0C .data 1
623: 612 00000df4 * L294:
624: 613 00000df4 * 200A00 .ascii " \12\0"
625: 614 00000df7 * .text
626: 615 00017B0C dd 8f00000df4 pushl $L294
627: 616 00017B12 fe 08 effffffa6f callf $8,_writes
628: 617 00017B19 # writes("cycle: ");
629: 618 00017B19 .data 1
630: 619 00000df7 * L295:
631: 620 00000df7 * 6379636C653A2000 .ascii "cycle: \0"
632: 621 00000dff * .text
633: 622 00017B19 dd 8f00000df7 pushl $L295
634: 623 00017B1F fe 08 effffffa62 callf $8,_writes
635: 624 00017B26 # writed( cycle );
636: 625 00017B26 dd effffffa5c pushl _cycle
637: 626 00017B2C fe 08 effffffa55 callf $8,_writed
638: 627 00017B33 # writes(" SUBD test ");
639: 628 00017B33 .data 1
640: 629 00000dff * L296:
641: 630 00000dff * 2020535542442074657374200 .ascii " SUBD test \0"
642: 0
643: 631 00000e0c * .text
644: 632 00017B33 dd 8f00000dff pushl $L296
645: 633 00017B39 fe 08 effffffa48 callf $8,_writes
646: 634 00017B40 # writed( test_no );
647: 635 00017B40 dd effffffa42 pushl _test_no
648: 636 00017B46 fe 08 effffffa3b callf $8,_writed
649: 637 00017B4D # writes(", subtest 4 (2 NOPs) - BAD FINAL ACC\n");
650: 638 00017B4D .data 1
651: 639 00000e0c * L297:
652: 640 00000e0c * 2C20737562746573742034202 .ascii ", subtest 4 (2 NOPs) - BAD FINAL ACC\12\0"
653: 832204E4F507329202D204241
654: 442046494E414C204143430A0
655: 0
656: 641 00000e32 * .text
657: 642 00017B4D dd 8f00000e0c pushl $L297
658: 643 00017B53 fe 08 effffffa2e callf $8,_writes
659: 644 00017B5A # print_subd_data();
660: 645 00017B5A fe 04 ef0000052b callf $4,_print_subd_data
661: 646 00017B61 # }
662: 647 00017B61 # if( halt_flg )
663: 648 00017B61 L293:
664: 649 00017B61 5d effffffa21 tstl _halt_flg
665: 650 00017B67 31 09 jeql L298
666: 651 00017B69 # subd_er_halt( BAD_ACC_HLT ); /* halt on the error */
667: 652 00017B69 dd 01 pushl $1
668: 653 00017B6B fe 08 ef00000610 callf $8,_subd_er_halt
669: 654 00017B72 # if( loop_on_err ) {
670: 655 00017B72 L298:
671: 656 00017B72 5d effffffa10 tstl _loop_on_err
672: 657 00017B78 31 0a jeql L299
673: 658 00017B7A # force_loop = TRUE; /* set the force loop flag */
674: 659 00017B7A 0d 01 effffffa07 movl $1,_force_loop
675: 660 00017B81 # asm("brw _subd_4_lp1");; /* and loop on the error */
676: 661 00017B81 13 ff3e brw _subd_4_lp1
677: 662 00017B84 # } /* end of loop on error */
678: 663 00017B84 # } /* end of compare error */
679: 664 00017B84 L299:
680: 665 00017B84 # } /* end of WHILE loop */
681: 666 00017B84 L292:
682: 667 00017B84 L288:
683: 668 00017B84 6d effffff9fe incl _index
684: 669 00017B8A 13 fecb jbr L290
685: 670 00017B8D L289:
686: 671 00017B8D # } /* end of subtest 4 */
687: 672 00017B8D 40 ret#2
688: 673 00017B8E .set L284,0x0
689: 674 00017B8E L286:
690: 675 00017B8E 13 feb4 jbr L287
691: 676 00017B91 .data
692: 677 00000d28 * .text
693: 678 00017B91 00 .align 1
694: 679 00017B92 .globl _subd_5
695: 680 00017B92 _subd_5:
696: 681 00017B92 0000 .word L300
697: 682 00017B94 #
698: 683 00017B94 #
699: 684 00017B94 #
700: 685 00017B94 # /************************************************************************
701: 686 00017B94 # *
702: 687 00017B94 # * SUBTEST 5 - Wait 1 NOP before storing the results
703: 688 00017B94 # *
704: 689 00017B94 # ************************************************************************/
705: 690 00017B94 # subd_5()
706: 691 00017B94 # {
707: 692 00017B94 13 0148 jbr L302
708: 693 00017B97 L303:
709: 694 00017B97 # force_loop = FALSE;
710: 695 00017B97 4d effffff9eb clrl _force_loop
711: 696 00017B9D # subtest = 5;
712: 697 00017B9D 0d 05 effffff9e4 movl $5,_subtest
713: 698 00017BA4 # for( index = 0; index < max_subd_1_index; index++ ) {
714: 699 00017BA4 4d effffff9de clrl _index
715: 700 00017BAA L306:
716: 701 00017BAA 1d effffff9d8 effffff9d3 cmpl _index,_max_subd_1_index
717: 702 00017BB5 91 03 13 0124 jgeq L305
718: 703 00017BBA # dbl_ld_acc = subd_1_data[index].op_1; /* get operand 1 */
719: 704 00017BBA 5c 18 effffff9c7 50 mull3 $24,_index,r0
720: 705 00017BC2 0c 8f00000000 50 addl2 $_subd_1_data,r0
721: 706 00017BC9 0d a004 effffff9bb movl 4(r0),_dbl_ld_acc+4
722: 707 00017BD1 0d 60 effffff9b0 movl (r0),_dbl_ld_acc
723: 708 00017BD8 # dbl_value_1 = subd_1_data[index].op_2; /* get operand 2 */
724: 709 00017BD8 5c 18 effffff9a9 50 mull3 $24,_index,r0
725: 710 00017BE0 0c 8f00000008 50 addl2 $_subd_1_data+8,r0
726: 711 00017BE7 0d a004 effffff99d movl 4(r0),_dbl_value_1+4
727: 712 00017BEF 0d 60 effffff992 movl (r0),_dbl_value_1
728: 713 00017BF6 # dbl_expected = subd_1_data[index].exp; /* get expected result */
729: 714 00017BF6 5c 18 effffff98b 50 mull3 $24,_index,r0
730: 715 00017BFE 0c 8f00000010 50 addl2 $_subd_1_data+16,r0
731: 716 00017C05 0d a004 effffff97f movl 4(r0),_dbl_expected+4
732: 717 00017C0D 0d 60 effffff974 movl (r0),_dbl_expected
733: 718 00017C14 # /*
734: 719 00017C14 # * If LOOP ON ERROR is set, this is the loop for this subtest.
735: 720 00017C14 # * The force loop flag is set after the first error.
736: 721 00017C14 # */
737: 722 00017C14 # asm("_subd_5_lp1:");
738: 723 00017C14 _subd_5_lp1:
739: 724 00017C14 # asm("ldd _dbl_ld_acc"); /* load the 1st operand */
740: 725 00017C14 07 effffff96e ldd _dbl_ld_acc
741: 726 00017C1A # asm("nop"); /* delay */
742: 727 00017C1A 10 nop
743: 728 00017C1B # asm("subd _dbl_value_1"); /* subtract the 2nd operand*/
744: 729 00017C1B d7 effffff967 subd _dbl_value_1
745: 730 00017C21 # asm("nop"); /* delay before storing */
746: 731 00017C21 10 nop
747: 732 00017C22 # asm("std _dbl_st_acc"); /* store the result */
748: 733 00017C22 27 effffff960 std _dbl_st_acc
749: 734 00017C28 # if( force_loop )
750: 735 00017C28 5d effffff95a tstl _force_loop
751: 736 00017C2E 31 02 jeql L307
752: 737 00017C30 # asm("brb _subd_5_lp1");; /* loop on the error */
753: 738 00017C30 11 e2 brb _subd_5_lp1
754: 739 00017C32 L307:
755: 740 00017C32 # /*
756: 741 00017C32 # * end error loop - test the results
757: 742 00017C32 # */
758: 743 00017C32 # if( (dbl_st_acc.m != dbl_expected.m) || /* verify the results */
759: 744 00017C32 # (dbl_st_acc.l != dbl_expected.l) ) {
760: 745 00017C32 1d effffff950 effffff94b cmpl _dbl_st_acc,_dbl_expected
761: 746 00017C3D 21 10 jneq L9995
762: 747 00017C3F 1d effffff947 effffff942 cmpl _dbl_st_acc+4,_dbl_expected+4
763: 748 00017C4A 21 03 13 0086 jeql L308
764: 749 00017C4F L9995:
765: 750 00017C4F # errcnt++; /* bump the error count */
766: 751 00017C4F 6d effffff933 incl _errcnt
767: 752 00017C55 # if( prt_error ) {
768: 753 00017C55 5d effffff92d tstl _prt_error
769: 754 00017C5B 31 55 jeql L309
770: 755 00017C5D # writes(" \n"); /* start a new print line */
771: 756 00017C5D .data 1
772: 757 00000e32 * L310:
773: 758 00000e32 * 200A00 .ascii " \12\0"
774: 759 00000e35 * .text
775: 760 00017C5D dd 8f00000e32 pushl $L310
776: 761 00017C63 fe 08 effffff91e callf $8,_writes
777: 762 00017C6A # writes("cycle: ");
778: 763 00017C6A .data 1
779: 764 00000e35 * L311:
780: 765 00000e35 * 6379636C653A2000 .ascii "cycle: \0"
781: 766 00000e3d * .text
782: 767 00017C6A dd 8f00000e35 pushl $L311
783: 768 00017C70 fe 08 effffff911 callf $8,_writes
784: 769 00017C77 # writed( cycle );
785: 770 00017C77 dd effffff90b pushl _cycle
786: 771 00017C7D fe 08 effffff904 callf $8,_writed
787: 772 00017C84 # writes(" SUBD test ");
788: 773 00017C84 .data 1
789: 774 00000e3d * L312:
790: 775 00000e3d * 2020535542442074657374200 .ascii " SUBD test \0"
791: 0
792: 776 00000e4a * .text
793: 777 00017C84 dd 8f00000e3d pushl $L312
794: 778 00017C8A fe 08 effffff8f7 callf $8,_writes
795: 779 00017C91 # writed( test_no );
796: 780 00017C91 dd effffff8f1 pushl _test_no
797: 781 00017C97 fe 08 effffff8ea callf $8,_writed
798: 782 00017C9E # writes(", subtest 5 (1 NOP) - BAD FINAL ACC\n");
799: 783 00017C9E .data 1
800: 784 00000e4a * L313:
801: 785 00000e4a * 2C20737562746573742035202 .ascii ", subtest 5 (1 NOP) - BAD FINAL ACC\12\0"
802: 831204E4F5029202D20424144
803: 2046494E414C204143430A00
804: 786 00000e6f * .text
805: 787 00017C9E dd 8f00000e4a pushl $L313
806: 788 00017CA4 fe 08 effffff8dd callf $8,_writes
807: 789 00017CAB # print_subd_data();
808: 790 00017CAB fe 04 ef000003da callf $4,_print_subd_data
809: 791 00017CB2 # }
810: 792 00017CB2 # if( halt_flg )
811: 793 00017CB2 L309:
812: 794 00017CB2 5d effffff8d0 tstl _halt_flg
813: 795 00017CB8 31 09 jeql L314
814: 796 00017CBA # subd_er_halt( BAD_ACC_HLT ); /* halt on the error */
815: 797 00017CBA dd 01 pushl $1
816: 798 00017CBC fe 08 ef000004bf callf $8,_subd_er_halt
817: 799 00017CC3 # if( loop_on_err ) {
818: 800 00017CC3 L314:
819: 801 00017CC3 5d effffff8bf tstl _loop_on_err
820: 802 00017CC9 31 0a jeql L315
821: 803 00017CCB # force_loop = TRUE; /* set the force loop flag */
822: 804 00017CCB 0d 01 effffff8b6 movl $1,_force_loop
823: 805 00017CD2 # asm("brw _subd_5_lp1");; /* and loop on the error */
824: 806 00017CD2 13 ff3f brw _subd_5_lp1
825: 807 00017CD5 # } /* end of loop on error */
826: 808 00017CD5 # } /* end of compare error */
827: 809 00017CD5 L315:
828: 810 00017CD5 # } /* end of WHILE loop */
829: 811 00017CD5 L308:
830: 812 00017CD5 L304:
831: 813 00017CD5 6d effffff8ad incl _index
832: 814 00017CDB 13 fecc jbr L306
833: 815 00017CDE L305:
834: 816 00017CDE # } /* end of subtest 5 */
835: 817 00017CDE 40 ret#2
836: 818 00017CDF .set L300,0x0
837: 819 00017CDF L302:
838: 820 00017CDF 13 feb5 jbr L303
839: 821 00017CE2 .data
840: 822 00000d28 * .text
841: 823 00017CE2 .align 1
842: 824 00017CE2 .globl _subd_6
843: 825 00017CE2 _subd_6:
844: 826 00017CE2 0000 .word L316
845: 827 00017CE4 #
846: 828 00017CE4 #
847: 829 00017CE4 #
848: 830 00017CE4 # /************************************************************************
849: 831 00017CE4 # *
850: 832 00017CE4 # * SUBTEST 6 - Check for register corruption
851: 833 00017CE4 # *
852: 834 00017CE4 # ************************************************************************/
853: 835 00017CE4 # subd_6()
854: 836 00017CE4 # {
855: 837 00017CE4 13 01c8 jbr L318
856: 838 00017CE7 L319:
857: 839 00017CE7 # force_loop = FALSE; /* clear force_loop flg */
858: 840 00017CE7 4d effffff89b clrl _force_loop
859: 841 00017CED # subtest = 6;
860: 842 00017CED 0d 06 effffff894 movl $6,_subtest
861: 843 00017CF4 # fill_reg_buf( load_regs ); /* get patterns for regs */
862: 844 00017CF4 dd 8f00000000 pushl $_load_regs
863: 845 00017CFA fe 08 effffff887 callf $8,_fill_reg_buf
864: 846 00017D01 # index = 0;
865: 847 00017D01 4d effffff881 clrl _index
866: 848 00017D07 # dbl_ld_acc = subd_1_data[0].op_1; /* get operand 1 */
867: 849 00017D07 0d effffff87f effffff87a movl _subd_1_data+4,_dbl_ld_acc+4
868: 850 00017D12 0d effffff870 effffff86b movl _subd_1_data,_dbl_ld_acc
869: 851 00017D1D # dbl_value_1 = subd_1_data[0].op_2; /* get operand 2 */
870: 852 00017D1D 0d effffff871 effffff864 movl _subd_1_data+12,_dbl_value_1+4
871: 853 00017D28 0d effffff862 effffff855 movl _subd_1_data+8,_dbl_value_1
872: 854 00017D33 # dbl_expected = subd_1_data[0].exp; /* get expected result */
873: 855 00017D33 0d effffff863 effffff84e movl _subd_1_data+20,_dbl_expected+4
874: 856 00017D3E 0d effffff854 effffff83f movl _subd_1_data+16,_dbl_expected
875: 857 00017D49 # /*
876: 858 00017D49 # * If LOOP ON ERROR is set, this is the loop for this subtest.
877: 859 00017D49 # * The force loop flag is set after the first error.
878: 860 00017D49 # */
879: 861 00017D49 # asm("_subd_6_lp1:");
880: 862 00017D49 _subd_6_lp1:
881: 863 00017D49 # asm("ldd _dbl_ld_acc"); /* LOAD the accumulator */
882: 864 00017D49 07 effffff839 ldd _dbl_ld_acc
883: 865 00017D4F # asm("nop");
884: 866 00017D4F 10 nop
885: 867 00017D50 # asm("loadr $0x1fff,_load_regs"); /* load regs 0 - 12 */
886: 868 00017D50 ab 891fff effffff82f loadr $0x1fff,_load_regs
887: 869 00017D59 # asm("nop");
888: 870 00017D59 10 nop
889: 871 00017D5A # asm("subd _dbl_value_1"); /* do the subtract */
890: 872 00017D5A d7 effffff828 subd _dbl_value_1
891: 873 00017D60 # asm("nop");
892: 874 00017D60 10 nop
893: 875 00017D61 # asm("storer $0x1fff,_store_regs"); /* store regs 0 - 12 */
894: 876 00017D61 bb 891fff effffff81e storer $0x1fff,_store_regs
895: 877 00017D6A # asm("std _dbl_st_acc"); /* save the accumulator */
896: 878 00017D6A 27 effffff818 std _dbl_st_acc
897: 879 00017D70 # if( force_loop )
898: 880 00017D70 5d effffff812 tstl _force_loop
899: 881 00017D76 31 02 jeql L321
900: 882 00017D78 # asm("brb _subd_6_lp1");; /* loop on the error */
901: 883 00017D78 11 cf brb _subd_6_lp1
902: 884 00017D7A L321:
903: 885 00017D7A # /*
904: 886 00017D7A # * Now compare the stored register values to those that were loaded
905: 887 00017D7A # */
906: 888 00017D7A # index2 = 0;
907: 889 00017D7A 4d effffff808 clrl _index2
908: 890 00017D80 # while( (load_regs[index2] == store_regs[index2]) && (index2 < 13) )
909: 891 00017D80 L322:
910: 892 00017D80 0d effffff802 50 movl _index2,r0
911: 893 00017D87 0d effffff7fb 51 movl _index2,r1
912: 894 00017D8E 1d 40effffff7f3 cmpl _load_regs[r0],_store_regs[r1]
913: 41effffff7ed
914: 895 00017D9B 21 11 jneq L323
915: 896 00017D9D 1d effffff7e5 0d cmpl _index2,$13
916: 897 00017DA4 81 08 jgeq L323
917: 898 00017DA6 # index2++; /* check reg values */
918: 899 00017DA6 6d effffff7dc incl _index2
919: 900 00017DAC 11 d2 jbr L322
920: 901 00017DAE L323:
921: 902 00017DAE # if( index2 < 13 ) { /* error if index2 < 13 */
922: 903 00017DAE 1d effffff7d4 0d cmpl _index2,$13
923: 904 00017DB5 91 03 13 00f4 jgeq L324
924: 905 00017DBA # errcnt++; /* bump the error count */
925: 906 00017DBA 6d effffff7c8 incl _errcnt
926: 907 00017DC0 # if( prt_error ) {
927: 908 00017DC0 5d effffff7c2 tstl _prt_error
928: 909 00017DC6 21 03 13 00c0 jeql L325
929: 910 00017DCB # writes(" \n"); /* start a new print line */
930: 911 00017DCB .data 1
931: 912 00000e6f * L326:
932: 913 00000e6f * 200A00 .ascii " \12\0"
933: 914 00000e72 * .text
934: 915 00017DCB dd 8f00000e6f pushl $L326
935: 916 00017DD1 fe 08 effffff7b0 callf $8,_writes
936: 917 00017DD8 # writes("cycle: ");
937: 918 00017DD8 .data 1
938: 919 00000e72 * L327:
939: 920 00000e72 * 6379636C653A2000 .ascii "cycle: \0"
940: 921 00000e7a * .text
941: 922 00017DD8 dd 8f00000e72 pushl $L327
942: 923 00017DDE fe 08 effffff7a3 callf $8,_writes
943: 924 00017DE5 # writed( cycle );
944: 925 00017DE5 dd effffff79d pushl _cycle
945: 926 00017DEB fe 08 effffff796 callf $8,_writed
946: 927 00017DF2 # writes(" SUBD test ");
947: 928 00017DF2 .data 1
948: 929 00000e7a * L328:
949: 930 00000e7a * 2020535542442074657374200 .ascii " SUBD test \0"
950: 0
951: 931 00000e87 * .text
952: 932 00017DF2 dd 8f00000e7a pushl $L328
953: 933 00017DF8 fe 08 effffff789 callf $8,_writes
954: 934 00017DFF # writed( test_no );
955: 935 00017DFF dd effffff783 pushl _test_no
956: 936 00017E05 fe 08 effffff77c callf $8,_writed
957: 937 00017E0C # writes(", subtest 6 - A REGISTER WAS CHANGED\n");
958: 938 00017E0C .data 1
959: 939 00000e87 * L329:
960: 940 00000e87 * 2C20737562746573742036202 .ascii ", subtest 6 - A REGISTER WAS CHANGED\12\0"
961: D204120524547495354455220
962: 574153204348414E4745440A0
963: 0
964: 941 00000ead * .text
965: 942 00017E0C dd 8f00000e87 pushl $L329
966: 943 00017E12 fe 08 effffff76f callf $8,_writes
967: 944 00017E19 # print_subd_data(); /* print the operands */
968: 945 00017E19 fe 04 ef0000026c callf $4,_print_subd_data
969: 946 00017E20 # writes("register "); /* print the information */
970: 947 00017E20 .data 1
971: 948 00000ead * L330:
972: 949 00000ead * 72656769737465722000 .ascii "register \0"
973: 950 00000eb7 * .text
974: 951 00017E20 dd 8f00000ead pushl $L330
975: 952 00017E26 fe 08 effffff75b callf $8,_writes
976: 953 00017E2D # writed( index2 ); /* about the corrupted */
977: 954 00017E2D dd effffff755 pushl _index2
978: 955 00017E33 fe 08 effffff74e callf $8,_writed
979: 956 00017E3A # writes(" = "); /* register */
980: 957 00017E3A .data 1
981: 958 00000eb7 * L331:
982: 959 00000eb7 * 203D2000 .ascii " = \0"
983: 960 00000ebb * .text
984: 961 00017E3A dd 8f00000eb7 pushl $L331
985: 962 00017E40 fe 08 effffff741 callf $8,_writes
986: 963 00017E47 # write32h( store_regs[index2] );
987: 964 00017E47 0d effffff73b 50 movl _index2,r0
988: 965 00017E4E dd 40effffff733 pushl _store_regs[r0]
989: 966 00017E55 fe 08 effffff72c callf $8,_write32h
990: 967 00017E5C # writes(", should be = ");
991: 968 00017E5C .data 1
992: 969 00000ebb * L333:
993: 970 00000ebb * 2C202073686F756C642062652 .ascii ", should be = \0"
994: 03D2000
995: 971 00000ecb * .text
996: 972 00017E5C dd 8f00000ebb pushl $L333
997: 973 00017E62 fe 08 effffff71f callf $8,_writes
998: 974 00017E69 # write32h( load_regs[index2] );
999: 975 00017E69 0d effffff719 50 movl _index2,r0
1000: 976 00017E70 dd 40effffff711 pushl _load_regs[r0]
1001: 977 00017E77 fe 08 effffff70a callf $8,_write32h
1002: 978 00017E7E # writes("\n");
1003: 979 00017E7E .data 1
1004: 980 00000ecb * L334:
1005: 981 00000ecb * 0A00 .ascii "\12\0"
1006: 982 00000ecd * .text
1007: 983 00017E7E dd 8f00000ecb pushl $L334
1008: 984 00017E84 fe 08 effffff6fd callf $8,_writes
1009: 985 00017E8B # }
1010: 986 00017E8B # if( halt_flg )
1011: 987 00017E8B L325:
1012: 988 00017E8B 5d effffff6f7 tstl _halt_flg
1013: 989 00017E91 31 09 jeql L335
1014: 990 00017E93 # subd_er_halt( BAD_REG_HLT ); /* halt on the error */
1015: 991 00017E93 dd 02 pushl $2
1016: 992 00017E95 fe 08 ef000002e6 callf $8,_subd_er_halt
1017: 993 00017E9C # if( loop_on_err ) {
1018: 994 00017E9C L335:
1019: 995 00017E9C 5d effffff6e6 tstl _loop_on_err
1020: 996 00017EA2 31 0a jeql L336
1021: 997 00017EA4 # force_loop = TRUE; /* set the force loop flag */
1022: 998 00017EA4 0d 01 effffff6dd movl $1,_force_loop
1023: 999 00017EAB # asm("brw _subd_6_lp1");; /* and loop on the error */
1024: 1000 00017EAB 13 fe9b brw _subd_6_lp1
1025: 1001 00017EAE # } /* end of loop on error */
1026: 1002 00017EAE # } /* end of register corruption error */
1027: 1003 00017EAE L336:
1028: 1004 00017EAE # } /* end of subtest 6 */
1029: 1005 00017EAE L324:
1030: 1006 00017EAE 40 ret#2
1031: 1007 00017EAF .set L316,0x0
1032: 1008 00017EAF L318:
1033: 1009 00017EAF 13 fe35 jbr L319
1034: 1010 00017EB2 .data
1035: 1011 00000d28 * .text
1036: 1012 00017EB2 .align 1
1037: 1013 00017EB2 .globl _subd_7
1038: 1014 00017EB2 _subd_7:
1039: 1015 00017EB2 0000 .word L337
1040: 1016 00017EB4 #
1041: 1017 00017EB4 #
1042: 1018 00017EB4 #
1043: 1019 00017EB4 # /************************************************************************
1044: 1020 00017EB4 # *
1045: 1021 00017EB4 # * SUBTEST 7 - Check for PSL corruption
1046: 1022 00017EB4 # *
1047: 1023 00017EB4 # ************************************************************************/
1048: 1024 00017EB4 # subd_7()
1049: 1025 00017EB4 # {
1050: 1026 00017EB4 13 01d2 jbr L339
1051: 1027 00017EB7 L340:
1052: 1028 00017EB7 # force_loop = FALSE; /* clear force_loop flg */
1053: 1029 00017EB7 4d effffff6cb clrl _force_loop
1054: 1030 00017EBD # subtest = 7;
1055: 1031 00017EBD 0d 07 effffff6c4 movl $7,_subtest
1056: 1032 00017EC4 # fill_reg_buf( load_regs ); /* get patterns for regs */
1057: 1033 00017EC4 dd 8f00000000 pushl $_load_regs
1058: 1034 00017ECA fe 08 effffff6b7 callf $8,_fill_reg_buf
1059: 1035 00017ED1 # for( index = 0; index < 3; index++ ) {
1060: 1036 00017ED1 4d effffff6b1 clrl _index
1061: 1037 00017ED7 L343:
1062: 1038 00017ED7 1d effffff6ab 03 cmpl _index,$3
1063: 1039 00017EDE 91 03 13 01a5 jgeq L342
1064: 1040 00017EE3 # dbl_ld_acc = subd_1_data[index].op_1; /* get operand 1 */
1065: 1041 00017EE3 5c 18 effffff69e 50 mull3 $24,_index,r0
1066: 1042 00017EEB 0c 8f00000000 50 addl2 $_subd_1_data,r0
1067: 1043 00017EF2 0d a004 effffff692 movl 4(r0),_dbl_ld_acc+4
1068: 1044 00017EFA 0d 60 effffff687 movl (r0),_dbl_ld_acc
1069: 1045 00017F01 # dbl_value_1 = subd_1_data[index].op_2; /* get operand 2 */
1070: 1046 00017F01 5c 18 effffff680 50 mull3 $24,_index,r0
1071: 1047 00017F09 0c 8f00000008 50 addl2 $_subd_1_data+8,r0
1072: 1048 00017F10 0d a004 effffff674 movl 4(r0),_dbl_value_1+4
1073: 1049 00017F18 0d 60 effffff669 movl (r0),_dbl_value_1
1074: 1050 00017F1F # dbl_expected = subd_1_data[index].exp; /* get expected */
1075: 1051 00017F1F 5c 18 effffff662 50 mull3 $24,_index,r0
1076: 1052 00017F27 0c 8f00000010 50 addl2 $_subd_1_data+16,r0
1077: 1053 00017F2E 0d a004 effffff656 movl 4(r0),_dbl_expected+4
1078: 1054 00017F36 0d 60 effffff64b movl (r0),_dbl_expected
1079: 1055 00017F3D # sgl_dummy1 = status_array[status_index]; /* status = +, -, 0 */
1080: 1056 00017F3D 0d effffff645 50 movl _status_index,r0
1081: 1057 00017F44 0d 40effffff63d movl _status_array[r0],_sgl_dummy1
1082: effffff638
1083: 1058 00017F50 # /*
1084: 1059 00017F50 # * If LOOP ON ERROR is set, this is the loop for this subtest.
1085: 1060 00017F50 # * The force loop flag is set after the first error.
1086: 1061 00017F50 # */
1087: 1062 00017F50 # asm("_subd_7_lp1:");
1088: 1063 00017F50 _subd_7_lp1:
1089: 1064 00017F50 # asm("ldd _dbl_ld_acc"); /* LOAD the accumulator */
1090: 1065 00017F50 07 effffff632 ldd _dbl_ld_acc
1091: 1066 00017F56 # asm("nop");
1092: 1067 00017F56 10 nop
1093: 1068 00017F57 # asm("tstl _sgl_dummy1"); /* set the PSL status */
1094: 1069 00017F57 5d effffff62b tstl _sgl_dummy1
1095: 1070 00017F5D # asm("movpsl _init_psl"); /* save the initial PSL */
1096: 1071 00017F5D cd effffff625 movpsl _init_psl
1097: 1072 00017F63 # asm("subd _dbl_value_1"); /* do the subtract */
1098: 1073 00017F63 d7 effffff61f subd _dbl_value_1
1099: 1074 00017F69 # asm("nop");
1100: 1075 00017F69 10 nop
1101: 1076 00017F6A # asm("movpsl _psl_val"); /* save the final PSL */
1102: 1077 00017F6A cd effffff618 movpsl _psl_val
1103: 1078 00017F70 # asm("std _dbl_st_acc"); /* save the accumulator */
1104: 1079 00017F70 27 effffff612 std _dbl_st_acc
1105: 1080 00017F76 # if( force_loop )
1106: 1081 00017F76 5d effffff60c tstl _force_loop
1107: 1082 00017F7C 31 02 jeql L344
1108: 1083 00017F7E # asm("brb _subd_7_lp1");; /* loop on the error */
1109: 1084 00017F7E 11 d0 brb _subd_7_lp1
1110: 1085 00017F80 L344:
1111: 1086 00017F80 # /*
1112: 1087 00017F80 # * Now compare the final PSL to the initial PSL -they should be the same
1113: 1088 00017F80 # */
1114: 1089 00017F80 # exp_psl = init_psl;
1115: 1090 00017F80 0d effffff602 effffff5fd movl _init_psl,_exp_psl
1116: 1091 00017F8B # if( psl_val != exp_psl ) {
1117: 1092 00017F8B 1d effffff5f7 effffff5f2 cmpl _psl_val,_exp_psl
1118: 1093 00017F96 21 03 13 00e4 jeql L345
1119: 1094 00017F9B # errcnt++; /* bump the error count */
1120: 1095 00017F9B 6d effffff5e7 incl _errcnt
1121: 1096 00017FA1 # if( prt_error ) {
1122: 1097 00017FA1 5d effffff5e1 tstl _prt_error
1123: 1098 00017FA7 21 03 13 00b0 jeql L346
1124: 1099 00017FAC # writes(" \n"); /* start a new print line */
1125: 1100 00017FAC .data 1
1126: 1101 00000ecd * L347:
1127: 1102 00000ecd * 200A00 .ascii " \12\0"
1128: 1103 00000ed0 * .text
1129: 1104 00017FAC dd 8f00000ecd pushl $L347
1130: 1105 00017FB2 fe 08 effffff5cf callf $8,_writes
1131: 1106 00017FB9 # writes("cycle: ");
1132: 1107 00017FB9 .data 1
1133: 1108 00000ed0 * L348:
1134: 1109 00000ed0 * 6379636C653A2000 .ascii "cycle: \0"
1135: 1110 00000ed8 * .text
1136: 1111 00017FB9 dd 8f00000ed0 pushl $L348
1137: 1112 00017FBF fe 08 effffff5c2 callf $8,_writes
1138: 1113 00017FC6 # writed( cycle );
1139: 1114 00017FC6 dd effffff5bc pushl _cycle
1140: 1115 00017FCC fe 08 effffff5b5 callf $8,_writed
1141: 1116 00017FD3 # writes(" SUBD test ");
1142: 1117 00017FD3 .data 1
1143: 1118 00000ed8 * L349:
1144: 1119 00000ed8 * 2020535542442074657374200 .ascii " SUBD test \0"
1145: 0
1146: 1120 00000ee5 * .text
1147: 1121 00017FD3 dd 8f00000ed8 pushl $L349
1148: 1122 00017FD9 fe 08 effffff5a8 callf $8,_writes
1149: 1123 00017FE0 # writed( test_no );
1150: 1124 00017FE0 dd effffff5a2 pushl _test_no
1151: 1125 00017FE6 fe 08 effffff59b callf $8,_writed
1152: 1126 00017FED # writes(", subtest 7 - INCORRECT FINAL PSL\n");
1153: 1127 00017FED .data 1
1154: 1128 00000ee5 * L350:
1155: 1129 00000ee5 * 2C20737562746573742037202 .ascii ", subtest 7 - INCORRECT FINAL PSL\12\0"
1156: D20494E434F52524543542046
1157: 494E414C2050534C0A00
1158: 1130 00000f08 * .text
1159: 1131 00017FED dd 8f00000ee5 pushl $L350
1160: 1132 00017FF3 fe 08 effffff58e callf $8,_writes
1161: 1133 00017FFA # print_subd_data(); /* print the operands */
1162: 1134 00017FFA fe 04 ef0000008b callf $4,_print_subd_data
1163: 1135 00018001 # writes("initial PSL = ");
1164: 1136 00018001 .data 1
1165: 1137 00000f08 * L351:
1166: 1138 00000f08 * 696E697469616C2050534C203 .ascii "initial PSL = \0"
1167: D2000
1168: 1139 00000f17 * .text
1169: 1140 00018001 dd 8f00000f08 pushl $L351
1170: 1141 00018007 fe 08 effffff57a callf $8,_writes
1171: 1142 0001800E # write32h( init_psl );
1172: 1143 0001800E dd effffff574 pushl _init_psl
1173: 1144 00018014 fe 08 effffff56d callf $8,_write32h
1174: 1145 0001801B # writes(", final PSL = ");
1175: 1146 0001801B .data 1
1176: 1147 00000f17 * L352:
1177: 1148 00000f17 * 2C202066696E616C2050534C2 .ascii ", final PSL = \0"
1178: 03D2000
1179: 1149 00000f27 * .text
1180: 1150 0001801B dd 8f00000f17 pushl $L352
1181: 1151 00018021 fe 08 effffff560 callf $8,_writes
1182: 1152 00018028 # write32h( psl_val );
1183: 1153 00018028 dd effffff55a pushl _psl_val
1184: 1154 0001802E fe 08 effffff553 callf $8,_write32h
1185: 1155 00018035 # writes(", expected PSL = ");
1186: 1156 00018035 .data 1
1187: 1157 00000f27 * L353:
1188: 1158 00000f27 * 2C20206578706563746564205 .ascii ", expected PSL = \0"
1189: 0534C203D2000
1190: 1159 00000f3a * .text
1191: 1160 00018035 dd 8f00000f27 pushl $L353
1192: 1161 0001803B fe 08 effffff546 callf $8,_writes
1193: 1162 00018042 # write32h( exp_psl );
1194: 1163 00018042 dd effffff540 pushl _exp_psl
1195: 1164 00018048 fe 08 effffff539 callf $8,_write32h
1196: 1165 0001804F # writes("\n");
1197: 1166 0001804F .data 1
1198: 1167 00000f3a * L354:
1199: 1168 00000f3a * 0A00 .ascii "\12\0"
1200: 1169 00000f3c * .text
1201: 1170 0001804F dd 8f00000f3a pushl $L354
1202: 1171 00018055 fe 08 effffff52c callf $8,_writes
1203: 1172 0001805C # }
1204: 1173 0001805C # if( halt_flg )
1205: 1174 0001805C L346:
1206: 1175 0001805C 5d effffff526 tstl _halt_flg
1207: 1176 00018062 31 09 jeql L355
1208: 1177 00018064 # subd_er_halt( BAD_PSL_HLT ); /* halt on the error */
1209: 1178 00018064 dd 03 pushl $3
1210: 1179 00018066 fe 08 ef00000115 callf $8,_subd_er_halt
1211: 1180 0001806D # if( loop_on_err ) {
1212: 1181 0001806D L355:
1213: 1182 0001806D 5d effffff515 tstl _loop_on_err
1214: 1183 00018073 31 0a jeql L356
1215: 1184 00018075 # force_loop = TRUE; /* set the force loop flag */
1216: 1185 00018075 0d 01 effffff50c movl $1,_force_loop
1217: 1186 0001807C # asm("brw _subd_7_lp1");; /* and loop on the error */
1218: 1187 0001807C 13 fed1 brw _subd_7_lp1
1219: 1188 0001807F # } /* end of loop on error */
1220: 1189 0001807F # } /* end of PSL corruption error */
1221: 1190 0001807F L356:
1222: 1191 0001807F # } /* end of WHILE loop */
1223: 1192 0001807F L345:
1224: 1193 0001807F L341:
1225: 1194 0001807F 6d effffff503 incl _index
1226: 1195 00018085 13 fe4f jbr L343
1227: 1196 00018088 L342:
1228: 1197 00018088 # } /* end of subtest 7 */
1229: 1198 00018088 40 ret#2
1230: 1199 00018089 .set L337,0x0
1231: 1200 00018089 L339:
1232: 1201 00018089 13 fe2b jbr L340
1233: 1202 0001808C .data
1234: 1203 00000d28 * .text
1235: 1204 0001808C .align 1
1236: 1205 0001808C .globl _print_subd_data
1237: 1206 0001808C _print_subd_data:
1238: 1207 0001808C 0000 .word L357
1239: 1208 0001808E #
1240: 1209 0001808E #
1241: 1210 0001808E #
1242: 1211 0001808E # /**************************************************************************
1243: 1212 0001808E # *
1244: 1213 0001808E # * PRINT THE DATA AND STORE RESULTS
1245: 1214 0001808E # *
1246: 1215 0001808E # * initial Acc = xxxxxxxx xxxxxxxx, stored = xxxxxxxx xxxxxxxx, index = xx
1247: 1216 0001808E # * operand = xxxxxxxx xxxxxxxx, expected = xxxxxxxx xxxxxxxx
1248: 1217 0001808E # **************************************************************************/
1249: 1218 0001808E # print_subd_data()
1250: 1219 0001808E # {
1251: 1220 0001808E 13 00ed jbr L359
1252: 1221 00018091 L360:
1253: 1222 00018091 # writes("initial Acc = ");
1254: 1223 00018091 .data 1
1255: 1224 00000f3c * L361:
1256: 1225 00000f3c * 696E697469616C20416363203 .ascii "initial Acc = \0"
1257: D2000
1258: 1226 00000f4b * .text
1259: 1227 00018091 dd 8f00000f3c pushl $L361
1260: 1228 00018097 fe 08 effffff4ea callf $8,_writes
1261: 1229 0001809E # write32h( dbl_ld_acc.m );
1262: 1230 0001809E dd effffff4e4 pushl _dbl_ld_acc
1263: 1231 000180A4 fe 08 effffff4dd callf $8,_write32h
1264: 1232 000180AB # writec(' ');
1265: 1233 000180AB dd 20 pushl $32
1266: 1234 000180AD fe 08 effffff4d4 callf $8,_writec
1267: 1235 000180B4 # write32h( dbl_ld_acc.l );
1268: 1236 000180B4 dd effffff4d2 pushl _dbl_ld_acc+4
1269: 1237 000180BA fe 08 effffff4c7 callf $8,_write32h
1270: 1238 000180C1 # writes(", stored = ");
1271: 1239 000180C1 .data 1
1272: 1240 00000f4b * L363:
1273: 1241 00000f4b * 2C2020202073746F726564203 .ascii ", stored = \0"
1274: D2000
1275: 1242 00000f5a * .text
1276: 1243 000180C1 dd 8f00000f4b pushl $L363
1277: 1244 000180C7 fe 08 effffff4ba callf $8,_writes
1278: 1245 000180CE # write32h( dbl_st_acc.m );
1279: 1246 000180CE dd effffff4b4 pushl _dbl_st_acc
1280: 1247 000180D4 fe 08 effffff4ad callf $8,_write32h
1281: 1248 000180DB # writec(' ');
1282: 1249 000180DB dd 20 pushl $32
1283: 1250 000180DD fe 08 effffff4a4 callf $8,_writec
1284: 1251 000180E4 # write32h( dbl_st_acc.l );
1285: 1252 000180E4 dd effffff4a2 pushl _dbl_st_acc+4
1286: 1253 000180EA fe 08 effffff497 callf $8,_write32h
1287: 1254 000180F1 # writes(", index = ");
1288: 1255 000180F1 .data 1
1289: 1256 00000f5a * L364:
1290: 1257 00000f5a * 2C202020696E646578203D200 .ascii ", index = \0"
1291: 0
1292: 1258 00000f67 * .text
1293: 1259 000180F1 dd 8f00000f5a pushl $L364
1294: 1260 000180F7 fe 08 effffff48a callf $8,_writes
1295: 1261 000180FE # writed( index );
1296: 1262 000180FE dd effffff484 pushl _index
1297: 1263 00018104 fe 08 effffff47d callf $8,_writed
1298: 1264 0001810B # writec('\n');
1299: 1265 0001810B dd 0a pushl $10
1300: 1266 0001810D fe 08 effffff474 callf $8,_writec
1301: 1267 00018114 # writes(" operand = ");
1302: 1268 00018114 .data 1
1303: 1269 00000f67 * L365:
1304: 1270 00000f67 * 202020206F706572616E64203 .ascii " operand = \0"
1305: D2000
1306: 1271 00000f76 * .text
1307: 1272 00018114 dd 8f00000f67 pushl $L365
1308: 1273 0001811A fe 08 effffff467 callf $8,_writes
1309: 1274 00018121 # write32h( dbl_value_1.m );
1310: 1275 00018121 dd effffff461 pushl _dbl_value_1
1311: 1276 00018127 fe 08 effffff45a callf $8,_write32h
1312: 1277 0001812E # writec(' ');
1313: 1278 0001812E dd 20 pushl $32
1314: 1279 00018130 fe 08 effffff451 callf $8,_writec
1315: 1280 00018137 # write32h( dbl_value_1.l );
1316: 1281 00018137 dd effffff44f pushl _dbl_value_1+4
1317: 1282 0001813D fe 08 effffff444 callf $8,_write32h
1318: 1283 00018144 # writes(", expected = ");
1319: 1284 00018144 .data 1
1320: 1285 00000f76 * L366:
1321: 1286 00000f76 * 2C20206578706563746564203 .ascii ", expected = \0"
1322: D2000
1323: 1287 00000f85 * .text
1324: 1288 00018144 dd 8f00000f76 pushl $L366
1325: 1289 0001814A fe 08 effffff437 callf $8,_writes
1326: 1290 00018151 # write32h( dbl_expected.m );
1327: 1291 00018151 dd effffff431 pushl _dbl_expected
1328: 1292 00018157 fe 08 effffff42a callf $8,_write32h
1329: 1293 0001815E # writec(' ');
1330: 1294 0001815E dd 20 pushl $32
1331: 1295 00018160 fe 08 effffff421 callf $8,_writec
1332: 1296 00018167 # write32h( dbl_expected.l );
1333: 1297 00018167 dd effffff41f pushl _dbl_expected+4
1334: 1298 0001816D fe 08 effffff414 callf $8,_write32h
1335: 1299 00018174 # writec('\n');
1336: 1300 00018174 dd 0a pushl $10
1337: 1301 00018176 fe 08 effffff40b callf $8,_writec
1338: 1302 0001817D # }
1339: 1303 0001817D 40 ret#2
1340: 1304 0001817E .set L357,0x0
1341: 1305 0001817E L359:
1342: 1306 0001817E 13 ff10 jbr L360
1343: 1307 00018181 .data
1344: 1308 00000d28 * .text
1345: 1309 00018181 00 .align 1
1346: 1310 00018182 .globl _subd_er_halt
1347: 1311 00018182 _subd_er_halt:
1348: 1312 00018182 0000 .word L367
1349: 1313 00018184 #
1350: 1314 00018184 #
1351: 1315 00018184 #
1352: 1316 00018184 # /**************************************************************************
1353: 1317 00018184 # *
1354: 1318 00018184 # * HALT ON ERROR ROUTINE
1355: 1319 00018184 # *
1356: 1320 00018184 # **************************************************************************/
1357: 1321 00018184 # subd_er_halt( halt_code )
1358: 1322 00018184 # int halt_code;
1359: 1323 00018184 # {
1360: 1324 00018184 13 0123 jbr L369
1361: 1325 00018187 L370:
1362: 1326 00018187 # sgl_value_1 = dbl_ld_acc.m;
1363: 1327 00018187 0d effffff3fb effffff3f6 movl _dbl_ld_acc,_sgl_value_1
1364: 1328 00018192 # sgl_value_2 = dbl_ld_acc.l;
1365: 1329 00018192 0d effffff3f4 effffff3eb movl _dbl_ld_acc+4,_sgl_value_2
1366: 1330 0001819D # sgl_value_3 = dbl_value_1.m;
1367: 1331 0001819D 0d effffff3e5 effffff3e0 movl _dbl_value_1,_sgl_value_3
1368: 1332 000181A8 # sgl_value_4 = dbl_value_1.l;
1369: 1333 000181A8 0d effffff3de effffff3d5 movl _dbl_value_1+4,_sgl_value_4
1370: 1334 000181B3 # sgl_value_5 = dbl_st_acc.m;
1371: 1335 000181B3 0d effffff3cf effffff3ca movl _dbl_st_acc,_sgl_value_5
1372: 1336 000181BE # sgl_value_6 = dbl_st_acc.l;
1373: 1337 000181BE 0d effffff3c8 effffff3bf movl _dbl_st_acc+4,_sgl_value_6
1374: 1338 000181C9 # sgl_dummy1 = halt_code; /* get the error type */
1375: 1339 000181C9 0d ad04 effffff3b7 movl 4(fp),_sgl_dummy1
1376: 1340 000181D1 # asm("movl _test_no,r0"); /* r0 = test number */
1377: 1341 000181D1 0d effffff3b1 50 movl _test_no,r0
1378: 1342 000181D8 # asm("movl _subtest,r1"); /* r1 = subtest number */
1379: 1343 000181D8 0d effffff3aa 51 movl _subtest,r1
1380: 1344 000181DF # asm("movl _sgl_dummy1,r2"); /* r2 = error code */
1381: 1345 000181DF 0d effffff3a3 52 movl _sgl_dummy1,r2
1382: 1346 000181E6 # asm("movl _cycle,r3"); /* r3 = cycle count */
1383: 1347 000181E6 0d effffff39c 53 movl _cycle,r3
1384: 1348 000181ED # asm("movl _sgl_value_1,r4"); /* r4 = MS operand 1 */
1385: 1349 000181ED 0d effffff395 54 movl _sgl_value_1,r4
1386: 1350 000181F4 # asm("movl _sgl_value_2,r5"); /* r5 = LS operand 1 */
1387: 1351 000181F4 0d effffff38e 55 movl _sgl_value_2,r5
1388: 1352 000181FB # asm("movl _sgl_value_3,r6"); /* r6 = MS operand 2 */
1389: 1353 000181FB 0d effffff387 56 movl _sgl_value_3,r6
1390: 1354 00018202 # asm("movl _sgl_value_4,r7"); /* r7 = LS operand 2 */
1391: 1355 00018202 0d effffff380 57 movl _sgl_value_4,r7
1392: 1356 00018209 # asm("movl _sgl_value_5,r8"); /* r8 = MS stored */
1393: 1357 00018209 0d effffff379 58 movl _sgl_value_5,r8
1394: 1358 00018210 # asm("movl _sgl_value_6,r9"); /* r9 = LS stored */
1395: 1359 00018210 0d effffff372 59 movl _sgl_value_6,r9
1396: 1360 00018217 # if( halt_code == BAD_ACC_HLT ) {
1397: 1361 00018217 1d ad04 01 cmpl 4(fp),$1
1398: 1362 0001821B 21 2d jneq L371
1399: 1363 0001821D # sgl_value_1 = dbl_expected.m;
1400: 1364 0001821D 0d effffff365 effffff360 movl _dbl_expected,_sgl_value_1
1401: 1365 00018228 # sgl_value_2 = dbl_expected.l;
1402: 1366 00018228 0d effffff35e effffff355 movl _dbl_expected+4,_sgl_value_2
1403: 1367 00018233 # asm("movl _sgl_value_1,r10"); /* r10 = MS expected */
1404: 1368 00018233 0d effffff34f 5a movl _sgl_value_1,r10
1405: 1369 0001823A # asm("movl _sgl_value_2,r11"); /* r11 = LS expected */
1406: 1370 0001823A 0d effffff348 5b movl _sgl_value_2,r11
1407: 1371 00018241 # asm("movl _index2,r12"); /* r12 = data index */
1408: 1372 00018241 0d effffff341 5c movl _index2,r12
1409: 1373 00018248 # } else
1410: 1374 00018248 11 5e jbr L372
1411: 1375 0001824A L371:
1412: 1376 0001824A # if( halt_code == BAD_REG_HLT ) {
1413: 1377 0001824A 1d ad04 02 cmpl 4(fp),$2
1414: 1378 0001824E 21 3d jneq L373
1415: 1379 00018250 # sgl_dummy1 = load_regs[index2];
1416: 1380 00018250 0d effffff332 50 movl _index2,r0
1417: 1381 00018257 0d 40effffff32a movl _load_regs[r0],_sgl_dummy1
1418: effffff325
1419: 1382 00018263 # sgl_dummy2 = store_regs[index2];
1420: 1383 00018263 0d effffff31f 50 movl _index2,r0
1421: 1384 0001826A 0d 40effffff317 movl _store_regs[r0],_sgl_dummy2
1422: effffff312
1423: 1385 00018276 # asm("movl _index2,r10"); /* r10 = bad register # */
1424: 1386 00018276 0d effffff30c 5a movl _index2,r10
1425: 1387 0001827D # asm("movl _sgl_dummy2,r11"); /* r11 = actual value */
1426: 1388 0001827D 0d effffff305 5b movl _sgl_dummy2,r11
1427: 1389 00018284 # asm("movl _sgl_dummy1,r12"); /* r12 = expected value */
1428: 1390 00018284 0d effffff2fe 5c movl _sgl_dummy1,r12
1429: 1391 0001828B # } else
1430: 1392 0001828B 11 1b jbr L374
1431: 1393 0001828D L373:
1432: 1394 0001828D # if( halt_code == BAD_PSL_HLT ) {
1433: 1395 0001828D 1d ad04 03 cmpl 4(fp),$3
1434: 1396 00018291 21 15 jneq L375
1435: 1397 00018293 # asm("movl _init_psl,r10"); /* r10 = initial PSL */
1436: 1398 00018293 0d effffff2ef 5a movl _init_psl,r10
1437: 1399 0001829A # asm("movl _psl_val,r11"); /* r11 = final PSL */
1438: 1400 0001829A 0d effffff2e8 5b movl _psl_val,r11
1439: 1401 000182A1 # asm("movl _exp_psl,r12"); /* r12 = expected PSL */
1440: 1402 000182A1 0d effffff2e1 5c movl _exp_psl,r12
1441: 1403 000182A8 # };
1442: 1404 000182A8 L375:
1443: 1405 000182A8 L374:
1444: 1406 000182A8 L372:
1445: 1407 000182A8 # asm("halt"); /* HALT ... */
1446: 1408 000182A8 00 halt
1447: 1409 000182A9 # }
1448: 1410 000182A9 40 ret#2
1449: 1411 000182AA .set L367,0x0
1450: 1412 000182AA L369:
1451: 1413 000182AA 13 feda jbr L370
1452: 1414 000182AD .data
1453: 1414 0002F835 .data
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