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1.1 ! root 1: ! 2: #include "fpp_defs.h" ! 3: ! 4: ! 5: /***************************************************************************** ! 6: * ! 7: * TSTD - DOUBLE PRECISION FLOATING POINT TEST ACC. TEST ! 8: * ! 9: * IMPLEMENTATION NOTE: If the "no-fpp WCS" is loaded then the status bits ! 10: * set will be based on the INTEGER value of the loaded data's most significant ! 11: * longword. Ergo and towit, if we're running without an FPP and a "bad 0" is ! 12: * loaded then the PSL will show POSITIVE rather than ZERO. A "bad 0" is any ! 13: * number with a zero exponent and non zero fraction (00000001 - 007fffff). ! 14: *****************************************************************************/ ! 15: tstd() ! 16: { ! 17: asm(".globl _tstd_t"); ! 18: asm("_tstd_t:"); /* entry address */ ! 19: if( ( cycle == 1 ) && ( prt_hdrs ) ) /* print headers on 1st pass */ ! 20: writes(" TSTD"); ! 21: tstd_1(); /* PSL flags test */ ! 22: tstd_2(); /* register stability */ ! 23: tstd_3(); /* accumulator stability */ ! 24: asm("jmp *return"); /* return to the test monitor */ ! 25: } ! 26: ! 27: ! 28: ! 29: /************************************************************************ ! 30: * ! 31: * SUBTEST 1 - Check for PSL corruption ! 32: * ! 33: ************************************************************************/ ! 34: tstd_1() ! 35: { ! 36: force_loop = FALSE; /* clear force_loop flg */ ! 37: subtest = 1; ! 38: for( index = 0; index < max_tstd_1_index; index++ ) { ! 39: dbl_ld_acc = tstd_1_data[index].ld; /* get value to load */ ! 40: sgl_expected = tstd_1_data[index].exp; /* get expected flags*/ ! 41: for( status_index = 0; status_index < 3; status_index++ ) { ! 42: sgl_dummy1 = status_array[status_index]; /* status = +,-,0 */ ! 43: /* ! 44: * If LOOP ON ERROR is set, this is the loop for this subtest. ! 45: * The force loop flag is set after the first error. ! 46: */ ! 47: asm("ldd _dbl_ld_acc"); /* load the initial value */ ! 48: asm("_tstd_1_lp1:"); ! 49: asm("tstl _sgl_dummy1"); /* set the PSL status */ ! 50: asm("movpsl _init_psl"); /* save the initial PSL */ ! 51: asm("tstd"); /* test the accmulator */ ! 52: asm("nop"); ! 53: asm("movpsl _psl_val"); /* save the final PSL */ ! 54: asm("std _dbl_st_acc"); /* save the final Acc. */ ! 55: if( force_loop ) ! 56: asm("brb _tstd_1_lp1");; /* loop on the error */ ! 57: /* ! 58: * Now compare the final PSL to the initial PSL -they should be the same ! 59: */ ! 60: exp_psl = init_psl; /* get the initial PSL */ ! 61: exp_psl &= 0xfffffff3; /* clear ZERO, NEGATIVE */ ! 62: if( sgl_expected == ZERO ) { ! 63: /* if( (!no_fpp_wcs) || (!dbl_ld_acc.m) ) /* */ ! 64: exp_psl |= PSL_Z; /* expect the ZERO bit set */ ! 65: } ! 66: if( sgl_expected == NEGATIVE ) ! 67: exp_psl |= PSL_N; /* expect the NEG bit set */ ! 68: if( psl_val != exp_psl ) { ! 69: errcnt++; /* bump the error count */ ! 70: if( prt_error ) { ! 71: writes(" \n"); /* start new print line */ ! 72: writes("cycle: "); ! 73: writed( cycle ); ! 74: writes(" TSTD test "); ! 75: writed( test_no ); ! 76: writes(", subtest 1 - BAD FINAL PSL\n"); ! 77: print_tstd_data(); /* print the operands */ ! 78: writes(", index = "); ! 79: writed( index ); ! 80: writec('\n'); ! 81: writes("initial PSL = "); ! 82: write32h( init_psl ); ! 83: writes(", final PSL = "); ! 84: write32h( psl_val ); ! 85: writes(", expected PSL = "); ! 86: write32h( exp_psl ); ! 87: writes("\n"); ! 88: } ! 89: if( halt_flg ) ! 90: tstd_er_halt( BAD_PSL_HLT ); /* halt on error */ ! 91: if( loop_on_err ) { ! 92: force_loop = TRUE; /* set force loop flag */ ! 93: asm("brw _tstd_1_lp1"); /* loop on the error */ ! 94: } /* end of loop on error */ ! 95: } /* end of PSL corruption error */ ! 96: } /* end of initial status WHILE loop */ ! 97: } /* end of data pattern WHILE loop */ ! 98: } /* end of subtest 1 */ ! 99: ! 100: ! 101: ! 102: /************************************************************************ ! 103: * ! 104: * SUBTEST 2 - Check for register corruption ! 105: * ! 106: ************************************************************************/ ! 107: tstd_2() ! 108: { ! 109: force_loop = FALSE; /* clear force_loop flg */ ! 110: subtest = 2; ! 111: fill_reg_buf( load_regs ); /* get patterns for regs */ ! 112: for( index = 0; index < max_tstd_1_index; index++ ) { ! 113: dbl_ld_acc = tstd_1_data[index].ld; /* get value to load */ ! 114: sgl_expected = tstd_1_data[index].exp; /* get expected flags*/ ! 115: for( status_index = 0; status_index < 3; status_index++ ) { ! 116: sgl_dummy1 = status_array[status_index]; /* status = +,-,0 */ ! 117: /* ! 118: * If LOOP ON ERROR is set, this is the loop for this subtest. ! 119: * The force loop flag is set after the first error. ! 120: */ ! 121: asm("_tstd_2_lp1:"); ! 122: asm("ldd _dbl_ld_acc"); /* load the Acc. */ ! 123: asm("loadr $0x1fff,_load_regs"); /* load regs 0 - 12 */ ! 124: asm("nop"); ! 125: asm("tstd"); /* test the acc. */ ! 126: asm("nop"); ! 127: asm("storer $0x1fff,_store_regs"); /* store regs 0 - 12 */ ! 128: asm("std _dbl_st_acc"); /* save the acc. */ ! 129: if( force_loop ) ! 130: asm("brb _tstd_2_lp1");; /* loop on the error */ ! 131: /* ! 132: * Now compare the stored register values to those that were loaded ! 133: */ ! 134: index2 = 0; ! 135: while( (load_regs[index2] == store_regs[index2]) && ! 136: (index2 < 13) ) ! 137: index2++; /* check reg values */ ! 138: if( index2 < 13 ) { /* error if index2 < 13 */ ! 139: errcnt++; /* bump the error count */ ! 140: if( prt_error ) { ! 141: writes(" \n"); /* start a new print line */ ! 142: writes("cycle: "); ! 143: writed( cycle ); ! 144: writes(" TSTD test "); ! 145: writed( test_no ); ! 146: writes(", subtest 2 - A REGISTER WAS MODIFIED\n"); ! 147: print_tstd_data(); /* print the operands */ ! 148: writes("\n"); ! 149: writes("register "); /* print the information */ ! 150: writed( index2 ); /* about the corrupted */ ! 151: writes(" = "); /* register */ ! 152: write32h( store_regs[index2] ); ! 153: writes(", should be = "); ! 154: write32h( load_regs[index2] ); ! 155: writes("\n"); ! 156: } ! 157: if( halt_flg ) ! 158: tstd_er_halt( BAD_REG_HLT ); /* halt on error */ ! 159: if( loop_on_err ) { ! 160: force_loop = TRUE; /* set force loop flag */ ! 161: asm("brw _tstd_2_lp1"); /* loop on the error */ ! 162: } /* end of loop on error */ ! 163: } /* end of register corruption error */ ! 164: } /* end of initial PSL WHILE loop */ ! 165: } /* end of tstd data WHILE loop */ ! 166: } /* end of subtest 2 */ ! 167: ! 168: ! 169: ! 170: ! 171: /************************************************************************ ! 172: * ! 173: * SUBTEST 3 - Check for accumulator corruption ! 174: * ! 175: ************************************************************************/ ! 176: tstd_3() ! 177: { ! 178: force_loop = FALSE; /* clear force_loop flg */ ! 179: subtest = 3; ! 180: for( index = 0; index < max_tstd_1_index; index++ ) { ! 181: dbl_ld_acc = tstd_1_data[index].ld; /* get value to load */ ! 182: if( !(dbl_ld_acc.m & 0x7f800000) ) { ! 183: dbl_expected.m = 0; ! 184: dbl_expected.l = 0; /* ignore bad 0's */ ! 185: } else ! 186: dbl_expected = dbl_ld_acc; ! 187: /* ! 188: * If LOOP ON ERROR is set, this is the loop for this subtest. ! 189: * The force loop flag is set after the first error. ! 190: */ ! 191: asm("_tstd_3_lp1:"); ! 192: asm("ldd _dbl_ld_acc"); ! 193: asm("nop"); ! 194: asm("tstd"); /* test the accumulator */ ! 195: asm("nop"); ! 196: asm("std _dbl_st_acc"); /* save the accumulator */ ! 197: if( force_loop ) ! 198: asm("brb _tstd_3_lp1");; /* loop on the error */ ! 199: /* ! 200: * Now compare the stored register values to those that were loaded ! 201: */ ! 202: if( (dbl_st_acc.m != dbl_expected.m ) || /* Acc corrupted? */ ! 203: (dbl_st_acc.l != dbl_expected.l) ) { ! 204: errcnt++; /* bump error count */ ! 205: if( prt_error ) { ! 206: writes(" \n"); /* start a new line */ ! 207: writes("cycle: "); ! 208: writed( cycle ); ! 209: writes(" TSTD test "); ! 210: writed( test_no ); ! 211: writes(", subtest 3 - THE ACC WAS MODIFIED\n"); ! 212: print_tstd_data(); /* print the operands */ ! 213: writes(", index = "); ! 214: writed( index ); ! 215: writec('\n'); ! 216: writes(" expected Acc = "); ! 217: write32h( dbl_expected.m ); ! 218: writec(' '); ! 219: write32h( dbl_expected.l ); ! 220: writes("\n"); ! 221: } ! 222: if( halt_flg ) ! 223: tstd_er_halt( BAD_ACC_HLT ); /* halt on error */ ! 224: if( loop_on_err ) { ! 225: force_loop = TRUE; /* set force loop flag */ ! 226: asm("brw _tstd_3_lp1"); /* loop on the error */ ! 227: } /* end of loop on error */ ! 228: } /* end of register corruption error */ ! 229: } /* end of tstd data WHILE loop */ ! 230: } /* end of subtest 3 */ ! 231: ! 232: ! 233: ! 234: /************************************************************************** ! 235: * ! 236: * PRINT THE DATA AND STORE RESULTS ! 237: * ! 238: * initial Acc = xxxxxxxx xxxxxxxx, final Acc = xxxxxxxx xxxxxxxx, index = xx ! 239: **************************************************************************/ ! 240: print_tstd_data() ! 241: { ! 242: writes("initial Acc = "); ! 243: write32h( dbl_ld_acc.m ); ! 244: writec(' '); ! 245: write32h( dbl_ld_acc.l ); ! 246: writes(", final Acc = "); ! 247: write32h( dbl_st_acc.m ); ! 248: writec(' '); ! 249: write32h( dbl_st_acc.l ); ! 250: } ! 251: ! 252: ! 253: ! 254: /************************************************************************** ! 255: * ! 256: * HALT ON ERROR ROUTINE ! 257: * ! 258: **************************************************************************/ ! 259: tstd_er_halt( halt_code ) ! 260: int halt_code; ! 261: { ! 262: sgl_dummy1 = halt_code; /* get the error type */ ! 263: asm("movl _test_no,r0"); /* r0 = test number */ ! 264: asm("movl _subtest,r1"); /* r1 = subtest number */ ! 265: asm("movl _sgl_dummy1,r2"); /* r2 = error code */ ! 266: asm("movl _cycle,r3"); /* r3 = cycle count */ ! 267: asm("movl _dbl_ld_acc,r4"); /* r4 = MS of init Acc */ ! 268: asm("movl _dbl_ld_acc+4,r5"); /* r5 = LS of init Acc */ ! 269: asm("movl _psl_val,r6"); /* r6 = final PSL */ ! 270: if( halt_code == BAD_ACC_HLT ) { ! 271: asm("movl _dbl_st_acc,r7"); /* r7 = MS of final Acc */ ! 272: asm("movl _dbl_st_acc+4,r8"); /* r8 = LS of final Acc */ ! 273: asm("movl _dbl_expected,r9"); /* r9 = MS of expected */ ! 274: asm("movl _dbl_expected+4,r10"); /* r10 = LS of expected */ ! 275: } else ! 276: if( halt_code == BAD_REG_HLT ) { ! 277: sgl_dummy1 = load_regs[index2]; ! 278: sgl_dummy2 = store_regs[index2]; ! 279: asm("movl _index2,r7"); /* r7 = bad register # */ ! 280: asm("movl _sgl_dummy2,r8"); /* r8 = actual value */ ! 281: asm("movl _sgl_dummy1,r9"); /* r9 = expected value */ ! 282: } else ! 283: if( halt_code == BAD_PSL_HLT ) { ! 284: asm("movl _exp_psl,r7"); /* r7 = expected PSL */ ! 285: asm("movl _index,r8"); /* r8 = data index */ ! 286: }; ! 287: asm("halt"); /* HALT ... */ ! 288: }
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