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Up to [Power 6/32 Unix Tahoe 4.2BSD] / cci / d / macro4|
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1.1 root 1: 1 00000000 LL0:
2: 2 00000000 .data
3: 3 00000720 * .text
4: 4 00000000 .align 1
5: 5 00000000 .globl _tstd
6: 6 00000000 _tstd:
7: 7 0001AC38 0000 .word L215
8: 8 0001AC3A #
9: 9 0001AC3A # #include "fpp_defs.h"
10: 10 0001AC3A #
11: 11 0001AC3A #
12: 12 0001AC3A # /*****************************************************************************
13: 13 0001AC3A # *
14: 14 0001AC3A # * TSTD - DOUBLE PRECISION FLOATING POINT TEST ACC. TEST
15: 15 0001AC3A # *
16: 16 0001AC3A # * IMPLEMENTATION NOTE: If the "no-fpp WCS" is loaded then the status bits
17: 17 0001AC3A # * set will be based on the INTEGER value of the loaded data's most significant
18: 18 0001AC3A # * longword. Ergo and towit, if we're running without an FPP and a "bad 0" is
19: 19 0001AC3A # * loaded then the PSL will show POSITIVE rather than ZERO. A "bad 0" is any
20: 20 0001AC3A # * number with a zero exponent and non zero fraction (00000001 - 007fffff).
21: 21 0001AC3A # *****************************************************************************/
22: 22 0001AC3A # tstd()
23: 23 0001AC3A # {
24: 24 0001AC3A 11 3a jbr L217
25: 25 0001AC3C L218:
26: 26 0001AC3C # asm(".globl _tstd_t");
27: 27 0001AC3C .globl _tstd_t
28: 28 0001AC3C # asm("_tstd_t:"); /* entry address */
29: 29 0001AC3C _tstd_t:
30: 30 0001AC3C # if( ( cycle == 1 ) && ( prt_hdrs ) ) /* print headers on 1st pass */
31: 31 0001AC3C 1d effffffff6 01 cmpl _cycle,$1
32: 32 0001AC43 21 15 jneq L219
33: 33 0001AC45 5d efffffffed tstl _prt_hdrs
34: 34 0001AC4B 31 0d jeql L219
35: 35 0001AC4D # writes(" TSTD");
36: 36 0001AC4D .data 1
37: 37 00000720 * L221:
38: 38 00000720 * 205453544400 .ascii " TSTD\0"
39: 39 00000726 * .text
40: 40 0001AC4D dd 8f00000720 pushl $L221
41: 41 0001AC53 fe 08 efffffffde callf $8,_writes
42: 42 0001AC5A # tstd_1(); /* PSL flags test */
43: 43 0001AC5A L219:
44: 44 0001AC5A fe 04 ef00000017 callf $4,_tstd_1
45: 45 0001AC61 # tstd_2(); /* register stability */
46: 46 0001AC61 fe 04 ef00000218 callf $4,_tstd_2
47: 47 0001AC68 # tstd_3(); /* accumulator stability */
48: 48 0001AC68 fe 04 ef0000041f callf $4,_tstd_3
49: 49 0001AC6F # asm("jmp *return"); /* return to the test monitor */
50: 50 0001AC6F 71 ffffffffc3 jmp *return
51: 51 0001AC75 # }
52: 52 0001AC75 40 ret#2
53: 53 0001AC76 .set L215,0x0
54: 54 0001AC76 L217:
55: 55 0001AC76 11 c4 jbr L218
56: 56 0001AC78 .data
57: 57 00000720 * .text
58: 58 0001AC78 .align 1
59: 59 0001AC78 .globl _tstd_1
60: 60 0001AC78 _tstd_1:
61: 61 0001AC78 0000 .word L225
62: 62 0001AC7A #
63: 63 0001AC7A #
64: 64 0001AC7A #
65: 65 0001AC7A # /************************************************************************
66: 66 0001AC7A # *
67: 67 0001AC7A # * SUBTEST 1 - Check for PSL corruption
68: 68 0001AC7A # *
69: 69 0001AC7A # ************************************************************************/
70: 70 0001AC7A # tstd_1()
71: 71 0001AC7A # {
72: 72 0001AC7A 13 0200 jbr L227
73: 73 0001AC7D L228:
74: 74 0001AC7D # force_loop = FALSE; /* clear force_loop flg */
75: 75 0001AC7D 4d efffffffb5 clrl _force_loop
76: 76 0001AC83 # subtest = 1;
77: 77 0001AC83 0d 01 efffffffae movl $1,_subtest
78: 78 0001AC8A # for( index = 0; index < max_tstd_1_index; index++ ) {
79: 79 0001AC8A 4d efffffffa8 clrl _index
80: 80 0001AC90 L231:
81: 81 0001AC90 1d efffffffa2 efffffff9d cmpl _index,_max_tstd_1_index
82: 82 0001AC9B 91 03 13 01dc jgeq L230
83: 83 0001ACA0 # dbl_ld_acc = tstd_1_data[index].ld; /* get value to load */
84: 84 0001ACA0 5c 0c efffffff91 50 mull3 $12,_index,r0
85: 85 0001ACA8 0c 8f00000000 50 addl2 $_tstd_1_data,r0
86: 86 0001ACAF 0d a004 efffffff85 movl 4(r0),_dbl_ld_acc+4
87: 87 0001ACB7 0d 60 efffffff7a movl (r0),_dbl_ld_acc
88: 88 0001ACBE # sgl_expected = tstd_1_data[index].exp; /* get expected flags*/
89: 89 0001ACBE 5c 0c efffffff73 50 mull3 $12,_index,r0
90: 90 0001ACC6 0d e000000008 efffffff67 movl _tstd_1_data+8(r0),_sgl_expected
91: 91 0001ACD1 # for( status_index = 0; status_index < 3; status_index++ ) {
92: 92 0001ACD1 4d efffffff61 clrl _status_index
93: 93 0001ACD7 L234:
94: 94 0001ACD7 1d efffffff5b 03 cmpl _status_index,$3
95: 95 0001ACDE 91 03 13 0190 jgeq L233
96: 96 0001ACE3 # sgl_dummy1 = status_array[status_index]; /* status = +,-,0 */
97: 97 0001ACE3 0d efffffff4f 50 movl _status_index,r0
98: 98 0001ACEA 0d 40efffffff47 movl _status_array[r0],_sgl_dummy1
99: efffffff42
100: 99 0001ACF6 # /*
101: 100 0001ACF6 # * If LOOP ON ERROR is set, this is the loop for this subtest.
102: 101 0001ACF6 # * The force loop flag is set after the first error.
103: 102 0001ACF6 # */
104: 103 0001ACF6 # asm("ldd _dbl_ld_acc"); /* load the initial value */
105: 104 0001ACF6 07 efffffff3c ldd _dbl_ld_acc
106: 105 0001ACFC # asm("_tstd_1_lp1:");
107: 106 0001ACFC _tstd_1_lp1:
108: 107 0001ACFC # asm("tstl _sgl_dummy1"); /* set the PSL status */
109: 108 0001ACFC 5d efffffff36 tstl _sgl_dummy1
110: 109 0001AD02 # asm("movpsl _init_psl"); /* save the initial PSL */
111: 110 0001AD02 cd efffffff30 movpsl _init_psl
112: 111 0001AD08 # asm("tstd"); /* test the accmulator */
113: 112 0001AD08 57 tstd
114: 113 0001AD09 # asm("nop");
115: 114 0001AD09 10 nop
116: 115 0001AD0A # asm("movpsl _psl_val"); /* save the final PSL */
117: 116 0001AD0A cd efffffff28 movpsl _psl_val
118: 117 0001AD10 # asm("std _dbl_st_acc"); /* save the final Acc. */
119: 118 0001AD10 27 efffffff22 std _dbl_st_acc
120: 119 0001AD16 # if( force_loop )
121: 120 0001AD16 5d efffffff1c tstl _force_loop
122: 121 0001AD1C 31 02 jeql L235
123: 122 0001AD1E # asm("brb _tstd_1_lp1");; /* loop on the error */
124: 123 0001AD1E 11 dc brb _tstd_1_lp1
125: 124 0001AD20 L235:
126: 125 0001AD20 # /*
127: 126 0001AD20 # * Now compare the final PSL to the initial PSL -they should be the same
128: 127 0001AD20 # */
129: 128 0001AD20 # exp_psl = init_psl; /* get the initial PSL */
130: 129 0001AD20 0d efffffff12 efffffff0d movl _init_psl,_exp_psl
131: 130 0001AD2B # exp_psl &= 0xfffffff3; /* clear ZERO, NEGATIVE */
132: 131 0001AD2B ac 88f3 efffffff05 andl2 $-13,_exp_psl
133: 132 0001AD33 # if( sgl_expected == ZERO ) {
134: 133 0001AD33 1d effffffeff 04 cmpl _sgl_expected,$4
135: 134 0001AD3A 21 07 jneq L236
136: 135 0001AD3C # /* if( (!no_fpp_wcs) || (!dbl_ld_acc.m) ) /* */
137: 136 0001AD3C # exp_psl |= PSL_Z; /* expect the ZERO bit set */
138: 137 0001AD3C 8c 04 effffffef5 orl2 $4,_exp_psl
139: 138 0001AD43 # }
140: 139 0001AD43 # if( sgl_expected == NEGATIVE )
141: 140 0001AD43 L236:
142: 141 0001AD43 1d effffffeef 08 cmpl _sgl_expected,$8
143: 142 0001AD4A 21 07 jneq L237
144: 143 0001AD4C # exp_psl |= PSL_N; /* expect the NEG bit set */
145: 144 0001AD4C 8c 08 effffffee5 orl2 $8,_exp_psl
146: 145 0001AD53 # if( psl_val != exp_psl ) {
147: 146 0001AD53 L237:
148: 147 0001AD53 1d effffffedf effffffeda cmpl _psl_val,_exp_psl
149: 148 0001AD5E 21 03 13 0107 jeql L238
150: 149 0001AD63 # errcnt++; /* bump the error count */
151: 150 0001AD63 6d effffffecf incl _errcnt
152: 151 0001AD69 # if( prt_error ) {
153: 152 0001AD69 5d effffffec9 tstl _prt_error
154: 153 0001AD6F 21 03 13 00d3 jeql L239
155: 154 0001AD74 # writes(" \n"); /* start new print line */
156: 155 0001AD74 .data 1
157: 156 00000726 * L240:
158: 157 00000726 * 200A00 .ascii " \12\0"
159: 158 00000729 * .text
160: 159 0001AD74 dd 8f00000726 pushl $L240
161: 160 0001AD7A fe 08 effffffeb7 callf $8,_writes
162: 161 0001AD81 # writes("cycle: ");
163: 162 0001AD81 .data 1
164: 163 00000729 * L241:
165: 164 00000729 * 6379636C653A2000 .ascii "cycle: \0"
166: 165 00000731 * .text
167: 166 0001AD81 dd 8f00000729 pushl $L241
168: 167 0001AD87 fe 08 effffffeaa callf $8,_writes
169: 168 0001AD8E # writed( cycle );
170: 169 0001AD8E dd effffffea4 pushl _cycle
171: 170 0001AD94 fe 08 effffffe9d callf $8,_writed
172: 171 0001AD9B # writes(" TSTD test ");
173: 172 0001AD9B .data 1
174: 173 00000731 * L243:
175: 174 00000731 * 2020545354442074657374200 .ascii " TSTD test \0"
176: 0
177: 175 0000073e * .text
178: 176 0001AD9B dd 8f00000731 pushl $L243
179: 177 0001ADA1 fe 08 effffffe90 callf $8,_writes
180: 178 0001ADA8 # writed( test_no );
181: 179 0001ADA8 dd effffffe8a pushl _test_no
182: 180 0001ADAE fe 08 effffffe83 callf $8,_writed
183: 181 0001ADB5 # writes(", subtest 1 - BAD FINAL PSL\n");
184: 182 0001ADB5 .data 1
185: 183 0000073e * L244:
186: 184 0000073e * 2C20737562746573742031202 .ascii ", subtest 1 - BAD FINAL PSL\12\0"
187: D204241442046494E414C2050
188: 534C0A00
189: 185 0000075b * .text
190: 186 0001ADB5 dd 8f0000073e pushl $L244
191: 187 0001ADBB fe 08 effffffe76 callf $8,_writes
192: 188 0001ADC2 # print_tstd_data(); /* print the operands */
193: 189 0001ADC2 fe 04 ef00000469 callf $4,_print_tstd_data
194: 190 0001ADC9 # writes(", index = ");
195: 191 0001ADC9 .data 1
196: 192 0000075b * L246:
197: 193 0000075b * 2C2020696E646578203D2000 .ascii ", index = \0"
198: 194 00000767 * .text
199: 195 0001ADC9 dd 8f0000075b pushl $L246
200: 196 0001ADCF fe 08 effffffe62 callf $8,_writes
201: 197 0001ADD6 # writed( index );
202: 198 0001ADD6 dd effffffe5c pushl _index
203: 199 0001ADDC fe 08 effffffe55 callf $8,_writed
204: 200 0001ADE3 # writec('\n');
205: 201 0001ADE3 dd 0a pushl $10
206: 202 0001ADE5 fe 08 effffffe4c callf $8,_writec
207: 203 0001ADEC # writes("initial PSL = ");
208: 204 0001ADEC .data 1
209: 205 00000767 * L248:
210: 206 00000767 * 696E697469616C2050534C203 .ascii "initial PSL = \0"
211: D2000
212: 207 00000776 * .text
213: 208 0001ADEC dd 8f00000767 pushl $L248
214: 209 0001ADF2 fe 08 effffffe3f callf $8,_writes
215: 210 0001ADF9 # write32h( init_psl );
216: 211 0001ADF9 dd effffffe39 pushl _init_psl
217: 212 0001ADFF fe 08 effffffe32 callf $8,_write32h
218: 213 0001AE06 # writes(", final PSL = ");
219: 214 0001AE06 .data 1
220: 215 00000776 * L250:
221: 216 00000776 * 2C202066696E616C2050534C2 .ascii ", final PSL = \0"
222: 03D2000
223: 217 00000786 * .text
224: 218 0001AE06 dd 8f00000776 pushl $L250
225: 219 0001AE0C fe 08 effffffe25 callf $8,_writes
226: 220 0001AE13 # write32h( psl_val );
227: 221 0001AE13 dd effffffe1f pushl _psl_val
228: 222 0001AE19 fe 08 effffffe18 callf $8,_write32h
229: 223 0001AE20 # writes(", expected PSL = ");
230: 224 0001AE20 .data 1
231: 225 00000786 * L251:
232: 226 00000786 * 2C20206578706563746564205 .ascii ", expected PSL = \0"
233: 0534C203D2000
234: 227 00000799 * .text
235: 228 0001AE20 dd 8f00000786 pushl $L251
236: 229 0001AE26 fe 08 effffffe0b callf $8,_writes
237: 230 0001AE2D # write32h( exp_psl );
238: 231 0001AE2D dd effffffe05 pushl _exp_psl
239: 232 0001AE33 fe 08 effffffdfe callf $8,_write32h
240: 233 0001AE3A # writes("\n");
241: 234 0001AE3A .data 1
242: 235 00000799 * L252:
243: 236 00000799 * 0A00 .ascii "\12\0"
244: 237 0000079b * .text
245: 238 0001AE3A dd 8f00000799 pushl $L252
246: 239 0001AE40 fe 08 effffffdf1 callf $8,_writes
247: 240 0001AE47 # }
248: 241 0001AE47 # if( halt_flg )
249: 242 0001AE47 L239:
250: 243 0001AE47 5d effffffdeb tstl _halt_flg
251: 244 0001AE4D 31 09 jeql L253
252: 245 0001AE4F # tstd_er_halt( BAD_PSL_HLT ); /* halt on error */
253: 246 0001AE4F dd 03 pushl $3
254: 247 0001AE51 fe 08 ef00000442 callf $8,_tstd_er_halt
255: 248 0001AE58 # if( loop_on_err ) {
256: 249 0001AE58 L253:
257: 250 0001AE58 5d effffffdda tstl _loop_on_err
258: 251 0001AE5E 31 0a jeql L255
259: 252 0001AE60 # force_loop = TRUE; /* set force loop flag */
260: 253 0001AE60 0d 01 effffffdd1 movl $1,_force_loop
261: 254 0001AE67 # asm("brw _tstd_1_lp1"); /* loop on the error */
262: 255 0001AE67 13 fe92 brw _tstd_1_lp1
263: 256 0001AE6A # } /* end of loop on error */
264: 257 0001AE6A # } /* end of PSL corruption error */
265: 258 0001AE6A L255:
266: 259 0001AE6A # } /* end of initial status WHILE loop */
267: 260 0001AE6A L238:
268: 261 0001AE6A L232:
269: 262 0001AE6A 6d effffffdc8 incl _status_index
270: 263 0001AE70 13 fe64 jbr L234
271: 264 0001AE73 L233:
272: 265 0001AE73 # } /* end of data pattern WHILE loop */
273: 266 0001AE73 L229:
274: 267 0001AE73 6d effffffdbf incl _index
275: 268 0001AE79 13 fe14 jbr L231
276: 269 0001AE7C L230:
277: 270 0001AE7C # } /* end of subtest 1 */
278: 271 0001AE7C 40 ret#2
279: 272 0001AE7D .set L225,0x0
280: 273 0001AE7D L227:
281: 274 0001AE7D 13 fdfd jbr L228
282: 275 0001AE80 .data
283: 276 00000720 * .text
284: 277 0001AE80 .align 1
285: 278 0001AE80 .globl _tstd_2
286: 279 0001AE80 _tstd_2:
287: 280 0001AE80 0000 .word L256
288: 281 0001AE82 #
289: 282 0001AE82 #
290: 283 0001AE82 #
291: 284 0001AE82 # /************************************************************************
292: 285 0001AE82 # *
293: 286 0001AE82 # * SUBTEST 2 - Check for register corruption
294: 287 0001AE82 # *
295: 288 0001AE82 # ************************************************************************/
296: 289 0001AE82 # tstd_2()
297: 290 0001AE82 # {
298: 291 0001AE82 13 0205 jbr L258
299: 292 0001AE85 L259:
300: 293 0001AE85 # force_loop = FALSE; /* clear force_loop flg */
301: 294 0001AE85 4d effffffdad clrl _force_loop
302: 295 0001AE8B # subtest = 2;
303: 296 0001AE8B 0d 02 effffffda6 movl $2,_subtest
304: 297 0001AE92 # fill_reg_buf( load_regs ); /* get patterns for regs */
305: 298 0001AE92 dd 8f00000000 pushl $_load_regs
306: 299 0001AE98 fe 08 effffffd99 callf $8,_fill_reg_buf
307: 300 0001AE9F # for( index = 0; index < max_tstd_1_index; index++ ) {
308: 301 0001AE9F 4d effffffd93 clrl _index
309: 302 0001AEA5 L263:
310: 303 0001AEA5 1d effffffd8d effffffd88 cmpl _index,_max_tstd_1_index
311: 304 0001AEB0 91 03 13 01d4 jgeq L262
312: 305 0001AEB5 # dbl_ld_acc = tstd_1_data[index].ld; /* get value to load */
313: 306 0001AEB5 5c 0c effffffd7c 50 mull3 $12,_index,r0
314: 307 0001AEBD 0c 8f00000000 50 addl2 $_tstd_1_data,r0
315: 308 0001AEC4 0d a004 effffffd70 movl 4(r0),_dbl_ld_acc+4
316: 309 0001AECC 0d 60 effffffd65 movl (r0),_dbl_ld_acc
317: 310 0001AED3 # sgl_expected = tstd_1_data[index].exp; /* get expected flags*/
318: 311 0001AED3 5c 0c effffffd5e 50 mull3 $12,_index,r0
319: 312 0001AEDB 0d e000000008 effffffd52 movl _tstd_1_data+8(r0),_sgl_expected
320: 313 0001AEE6 # for( status_index = 0; status_index < 3; status_index++ ) {
321: 314 0001AEE6 4d effffffd4c clrl _status_index
322: 315 0001AEEC L266:
323: 316 0001AEEC 1d effffffd46 03 cmpl _status_index,$3
324: 317 0001AEF3 91 03 13 0188 jgeq L265
325: 318 0001AEF8 # sgl_dummy1 = status_array[status_index]; /* status = +,-,0 */
326: 319 0001AEF8 0d effffffd3a 50 movl _status_index,r0
327: 320 0001AEFF 0d 40effffffd32 movl _status_array[r0],_sgl_dummy1
328: effffffd2d
329: 321 0001AF0B # /*
330: 322 0001AF0B # * If LOOP ON ERROR is set, this is the loop for this subtest.
331: 323 0001AF0B # * The force loop flag is set after the first error.
332: 324 0001AF0B # */
333: 325 0001AF0B # asm("_tstd_2_lp1:");
334: 326 0001AF0B _tstd_2_lp1:
335: 327 0001AF0B # asm("ldd _dbl_ld_acc"); /* load the Acc. */
336: 328 0001AF0B 07 effffffd27 ldd _dbl_ld_acc
337: 329 0001AF11 # asm("loadr $0x1fff,_load_regs"); /* load regs 0 - 12 */
338: 330 0001AF11 ab 891fff effffffd1e loadr $0x1fff,_load_regs
339: 331 0001AF1A # asm("nop");
340: 332 0001AF1A 10 nop
341: 333 0001AF1B # asm("tstd"); /* test the acc. */
342: 334 0001AF1B 57 tstd
343: 335 0001AF1C # asm("nop");
344: 336 0001AF1C 10 nop
345: 337 0001AF1D # asm("storer $0x1fff,_store_regs"); /* store regs 0 - 12 */
346: 338 0001AF1D bb 891fff effffffd12 storer $0x1fff,_store_regs
347: 339 0001AF26 # asm("std _dbl_st_acc"); /* save the acc. */
348: 340 0001AF26 27 effffffd0c std _dbl_st_acc
349: 341 0001AF2C # if( force_loop )
350: 342 0001AF2C 5d effffffd06 tstl _force_loop
351: 343 0001AF32 31 02 jeql L267
352: 344 0001AF34 # asm("brb _tstd_2_lp1");; /* loop on the error */
353: 345 0001AF34 11 d5 brb _tstd_2_lp1
354: 346 0001AF36 L267:
355: 347 0001AF36 # /*
356: 348 0001AF36 # * Now compare the stored register values to those that were loaded
357: 349 0001AF36 # */
358: 350 0001AF36 # index2 = 0;
359: 351 0001AF36 4d effffffcfc clrl _index2
360: 352 0001AF3C # while( (load_regs[index2] == store_regs[index2]) &&
361: 353 0001AF3C # (index2 < 13) )
362: 354 0001AF3C L268:
363: 355 0001AF3C 0d effffffcf6 50 movl _index2,r0
364: 356 0001AF43 0d effffffcef 51 movl _index2,r1
365: 357 0001AF4A 1d 40effffffce7 cmpl _load_regs[r0],_store_regs[r1]
366: 41effffffce1
367: 358 0001AF57 21 11 jneq L269
368: 359 0001AF59 1d effffffcd9 0d cmpl _index2,$13
369: 360 0001AF60 81 08 jgeq L269
370: 361 0001AF62 # index2++; /* check reg values */
371: 362 0001AF62 6d effffffcd0 incl _index2
372: 363 0001AF68 11 d2 jbr L268
373: 364 0001AF6A L269:
374: 365 0001AF6A # if( index2 < 13 ) { /* error if index2 < 13 */
375: 366 0001AF6A 1d effffffcc8 0d cmpl _index2,$13
376: 367 0001AF71 91 03 13 0101 jgeq L270
377: 368 0001AF76 # errcnt++; /* bump the error count */
378: 369 0001AF76 6d effffffcbc incl _errcnt
379: 370 0001AF7C # if( prt_error ) {
380: 371 0001AF7C 5d effffffcb6 tstl _prt_error
381: 372 0001AF82 21 03 13 00cd jeql L271
382: 373 0001AF87 # writes(" \n"); /* start a new print line */
383: 374 0001AF87 .data 1
384: 375 0000079b * L272:
385: 376 0000079b * 200A00 .ascii " \12\0"
386: 377 0000079e * .text
387: 378 0001AF87 dd 8f0000079b pushl $L272
388: 379 0001AF8D fe 08 effffffca4 callf $8,_writes
389: 380 0001AF94 # writes("cycle: ");
390: 381 0001AF94 .data 1
391: 382 0000079e * L273:
392: 383 0000079e * 6379636C653A2000 .ascii "cycle: \0"
393: 384 000007a6 * .text
394: 385 0001AF94 dd 8f0000079e pushl $L273
395: 386 0001AF9A fe 08 effffffc97 callf $8,_writes
396: 387 0001AFA1 # writed( cycle );
397: 388 0001AFA1 dd effffffc91 pushl _cycle
398: 389 0001AFA7 fe 08 effffffc8a callf $8,_writed
399: 390 0001AFAE # writes(" TSTD test ");
400: 391 0001AFAE .data 1
401: 392 000007a6 * L274:
402: 393 000007a6 * 2020545354442074657374200 .ascii " TSTD test \0"
403: 0
404: 394 000007b3 * .text
405: 395 0001AFAE dd 8f000007a6 pushl $L274
406: 396 0001AFB4 fe 08 effffffc7d callf $8,_writes
407: 397 0001AFBB # writed( test_no );
408: 398 0001AFBB dd effffffc77 pushl _test_no
409: 399 0001AFC1 fe 08 effffffc70 callf $8,_writed
410: 400 0001AFC8 # writes(", subtest 2 - A REGISTER WAS MODIFIED\n");
411: 401 0001AFC8 .data 1
412: 402 000007b3 * L275:
413: 403 000007b3 * 2C20737562746573742032202 .ascii ", subtest 2 - A REGISTER WAS MODIFIED\12\0"
414: D204120524547495354455220
415: 574153204D4F4449464945440
416: A00
417: 404 000007da * .text
418: 405 0001AFC8 dd 8f000007b3 pushl $L275
419: 406 0001AFCE fe 08 effffffc63 callf $8,_writes
420: 407 0001AFD5 # print_tstd_data(); /* print the operands */
421: 408 0001AFD5 fe 04 ef00000256 callf $4,_print_tstd_data
422: 409 0001AFDC # writes("\n");
423: 410 0001AFDC .data 1
424: 411 000007da * L276:
425: 412 000007da * 0A00 .ascii "\12\0"
426: 413 000007dc * .text
427: 414 0001AFDC dd 8f000007da pushl $L276
428: 415 0001AFE2 fe 08 effffffc4f callf $8,_writes
429: 416 0001AFE9 # writes("register "); /* print the information */
430: 417 0001AFE9 .data 1
431: 418 000007dc * L277:
432: 419 000007dc * 72656769737465722000 .ascii "register \0"
433: 420 000007e6 * .text
434: 421 0001AFE9 dd 8f000007dc pushl $L277
435: 422 0001AFEF fe 08 effffffc42 callf $8,_writes
436: 423 0001AFF6 # writed( index2 ); /* about the corrupted */
437: 424 0001AFF6 dd effffffc3c pushl _index2
438: 425 0001AFFC fe 08 effffffc35 callf $8,_writed
439: 426 0001B003 # writes(" = "); /* register */
440: 427 0001B003 .data 1
441: 428 000007e6 * L278:
442: 429 000007e6 * 203D2000 .ascii " = \0"
443: 430 000007ea * .text
444: 431 0001B003 dd 8f000007e6 pushl $L278
445: 432 0001B009 fe 08 effffffc28 callf $8,_writes
446: 433 0001B010 # write32h( store_regs[index2] );
447: 434 0001B010 0d effffffc22 50 movl _index2,r0
448: 435 0001B017 dd 40effffffc1a pushl _store_regs[r0]
449: 436 0001B01E fe 08 effffffc13 callf $8,_write32h
450: 437 0001B025 # writes(", should be = ");
451: 438 0001B025 .data 1
452: 439 000007ea * L279:
453: 440 000007ea * 2C202073686F756C642062652 .ascii ", should be = \0"
454: 03D2000
455: 441 000007fa * .text
456: 442 0001B025 dd 8f000007ea pushl $L279
457: 443 0001B02B fe 08 effffffc06 callf $8,_writes
458: 444 0001B032 # write32h( load_regs[index2] );
459: 445 0001B032 0d effffffc00 50 movl _index2,r0
460: 446 0001B039 dd 40effffffbf8 pushl _load_regs[r0]
461: 447 0001B040 fe 08 effffffbf1 callf $8,_write32h
462: 448 0001B047 # writes("\n");
463: 449 0001B047 .data 1
464: 450 000007fa * L280:
465: 451 000007fa * 0A00 .ascii "\12\0"
466: 452 000007fc * .text
467: 453 0001B047 dd 8f000007fa pushl $L280
468: 454 0001B04D fe 08 effffffbe4 callf $8,_writes
469: 455 0001B054 # }
470: 456 0001B054 # if( halt_flg )
471: 457 0001B054 L271:
472: 458 0001B054 5d effffffbde tstl _halt_flg
473: 459 0001B05A 31 09 jeql L281
474: 460 0001B05C # tstd_er_halt( BAD_REG_HLT ); /* halt on error */
475: 461 0001B05C dd 02 pushl $2
476: 462 0001B05E fe 08 ef00000235 callf $8,_tstd_er_halt
477: 463 0001B065 # if( loop_on_err ) {
478: 464 0001B065 L281:
479: 465 0001B065 5d effffffbcd tstl _loop_on_err
480: 466 0001B06B 31 0a jeql L282
481: 467 0001B06D # force_loop = TRUE; /* set force loop flag */
482: 468 0001B06D 0d 01 effffffbc4 movl $1,_force_loop
483: 469 0001B074 # asm("brw _tstd_2_lp1"); /* loop on the error */
484: 470 0001B074 13 fe94 brw _tstd_2_lp1
485: 471 0001B077 # } /* end of loop on error */
486: 472 0001B077 # } /* end of register corruption error */
487: 473 0001B077 L282:
488: 474 0001B077 # } /* end of initial PSL WHILE loop */
489: 475 0001B077 L270:
490: 476 0001B077 L264:
491: 477 0001B077 6d effffffbbb incl _status_index
492: 478 0001B07D 13 fe6c jbr L266
493: 479 0001B080 L265:
494: 480 0001B080 # } /* end of tstd data WHILE loop */
495: 481 0001B080 L261:
496: 482 0001B080 6d effffffbb2 incl _index
497: 483 0001B086 13 fe1c jbr L263
498: 484 0001B089 L262:
499: 485 0001B089 # } /* end of subtest 2 */
500: 486 0001B089 40 ret#2
501: 487 0001B08A .set L256,0x0
502: 488 0001B08A L258:
503: 489 0001B08A 13 fdf8 jbr L259
504: 490 0001B08D .data
505: 491 00000720 * .text
506: 492 0001B08D 00 .align 1
507: 493 0001B08E .globl _tstd_3
508: 494 0001B08E _tstd_3:
509: 495 0001B08E 0000 .word L283
510: 496 0001B090 #
511: 497 0001B090 #
512: 498 0001B090 #
513: 499 0001B090 #
514: 500 0001B090 # /************************************************************************
515: 501 0001B090 # *
516: 502 0001B090 # * SUBTEST 3 - Check for accumulator corruption
517: 503 0001B090 # *
518: 504 0001B090 # ************************************************************************/
519: 505 0001B090 # tstd_3()
520: 506 0001B090 # {
521: 507 0001B090 13 019b jbr L285
522: 508 0001B093 L286:
523: 509 0001B093 # force_loop = FALSE; /* clear force_loop flg */
524: 510 0001B093 4d effffffb9f clrl _force_loop
525: 511 0001B099 # subtest = 3;
526: 512 0001B099 0d 03 effffffb98 movl $3,_subtest
527: 513 0001B0A0 # for( index = 0; index < max_tstd_1_index; index++ ) {
528: 514 0001B0A0 4d effffffb92 clrl _index
529: 515 0001B0A6 L289:
530: 516 0001B0A6 1d effffffb8c effffffb87 cmpl _index,_max_tstd_1_index
531: 517 0001B0B1 91 03 13 0177 jgeq L288
532: 518 0001B0B6 # dbl_ld_acc = tstd_1_data[index].ld; /* get value to load */
533: 519 0001B0B6 5c 0c effffffb7b 50 mull3 $12,_index,r0
534: 520 0001B0BE 0c 8f00000000 50 addl2 $_tstd_1_data,r0
535: 521 0001B0C5 0d a004 effffffb6f movl 4(r0),_dbl_ld_acc+4
536: 522 0001B0CD 0d 60 effffffb64 movl (r0),_dbl_ld_acc
537: 523 0001B0D4 # if( !(dbl_ld_acc.m & 0x7f800000) ) {
538: 524 0001B0D4 3d 8f7f800000 effffffb59 bitl $2139095040,_dbl_ld_acc
539: 525 0001B0DF 21 0e jneq L290
540: 526 0001B0E1 # dbl_expected.m = 0;
541: 527 0001B0E1 4d effffffb51 clrl _dbl_expected
542: 528 0001B0E7 # dbl_expected.l = 0; /* ignore bad 0's */
543: 529 0001B0E7 4d effffffb4f clrl _dbl_expected+4
544: 530 0001B0ED # } else
545: 531 0001B0ED 11 16 jbr L291
546: 532 0001B0EF L290:
547: 533 0001B0EF # dbl_expected = dbl_ld_acc;
548: 534 0001B0EF 0d effffffb47 effffffb42 movl _dbl_ld_acc+4,_dbl_expected+4
549: 535 0001B0FA 0d effffffb38 effffffb33 movl _dbl_ld_acc,_dbl_expected
550: 536 0001B105 L291:
551: 537 0001B105 # /*
552: 538 0001B105 # * If LOOP ON ERROR is set, this is the loop for this subtest.
553: 539 0001B105 # * The force loop flag is set after the first error.
554: 540 0001B105 # */
555: 541 0001B105 # asm("_tstd_3_lp1:");
556: 542 0001B105 _tstd_3_lp1:
557: 543 0001B105 # asm("ldd _dbl_ld_acc");
558: 544 0001B105 07 effffffb2d ldd _dbl_ld_acc
559: 545 0001B10B # asm("nop");
560: 546 0001B10B 10 nop
561: 547 0001B10C # asm("tstd"); /* test the accumulator */
562: 548 0001B10C 57 tstd
563: 549 0001B10D # asm("nop");
564: 550 0001B10D 10 nop
565: 551 0001B10E # asm("std _dbl_st_acc"); /* save the accumulator */
566: 552 0001B10E 27 effffffb24 std _dbl_st_acc
567: 553 0001B114 # if( force_loop )
568: 554 0001B114 5d effffffb1e tstl _force_loop
569: 555 0001B11A 31 02 jeql L292
570: 556 0001B11C # asm("brb _tstd_3_lp1");; /* loop on the error */
571: 557 0001B11C 11 e7 brb _tstd_3_lp1
572: 558 0001B11E L292:
573: 559 0001B11E # /*
574: 560 0001B11E # * Now compare the stored register values to those that were loaded
575: 561 0001B11E # */
576: 562 0001B11E # if( (dbl_st_acc.m != dbl_expected.m ) || /* Acc corrupted? */
577: 563 0001B11E # (dbl_st_acc.l != dbl_expected.l) ) {
578: 564 0001B11E 1d effffffb14 effffffb0f cmpl _dbl_st_acc,_dbl_expected
579: 565 0001B129 21 10 jneq L9999
580: 566 0001B12B 1d effffffb0b effffffb06 cmpl _dbl_st_acc+4,_dbl_expected+4
581: 567 0001B136 21 03 13 00e9 jeql L293
582: 568 0001B13B L9999:
583: 569 0001B13B # errcnt++; /* bump error count */
584: 570 0001B13B 6d effffffaf7 incl _errcnt
585: 571 0001B141 # if( prt_error ) {
586: 572 0001B141 5d effffffaf1 tstl _prt_error
587: 573 0001B147 21 03 13 00b5 jeql L294
588: 574 0001B14C # writes(" \n"); /* start a new line */
589: 575 0001B14C .data 1
590: 576 000007fc * L295:
591: 577 000007fc * 200A00 .ascii " \12\0"
592: 578 000007ff * .text
593: 579 0001B14C dd 8f000007fc pushl $L295
594: 580 0001B152 fe 08 effffffadf callf $8,_writes
595: 581 0001B159 # writes("cycle: ");
596: 582 0001B159 .data 1
597: 583 000007ff * L296:
598: 584 000007ff * 6379636C653A2000 .ascii "cycle: \0"
599: 585 00000807 * .text
600: 586 0001B159 dd 8f000007ff pushl $L296
601: 587 0001B15F fe 08 effffffad2 callf $8,_writes
602: 588 0001B166 # writed( cycle );
603: 589 0001B166 dd effffffacc pushl _cycle
604: 590 0001B16C fe 08 effffffac5 callf $8,_writed
605: 591 0001B173 # writes(" TSTD test ");
606: 592 0001B173 .data 1
607: 593 00000807 * L297:
608: 594 00000807 * 2020545354442074657374200 .ascii " TSTD test \0"
609: 0
610: 595 00000814 * .text
611: 596 0001B173 dd 8f00000807 pushl $L297
612: 597 0001B179 fe 08 effffffab8 callf $8,_writes
613: 598 0001B180 # writed( test_no );
614: 599 0001B180 dd effffffab2 pushl _test_no
615: 600 0001B186 fe 08 effffffaab callf $8,_writed
616: 601 0001B18D # writes(", subtest 3 - THE ACC WAS MODIFIED\n");
617: 602 0001B18D .data 1
618: 603 00000814 * L298:
619: 604 00000814 * 2C20737562746573742033202 .ascii ", subtest 3 - THE ACC WAS MODIFIED\12\0"
620: D205448452041434320574153
621: 204D4F4449464945440A00
622: 605 00000838 * .text
623: 606 0001B18D dd 8f00000814 pushl $L298
624: 607 0001B193 fe 08 effffffa9e callf $8,_writes
625: 608 0001B19A # print_tstd_data(); /* print the operands */
626: 609 0001B19A fe 04 ef00000091 callf $4,_print_tstd_data
627: 610 0001B1A1 # writes(", index = ");
628: 611 0001B1A1 .data 1
629: 612 00000838 * L299:
630: 613 00000838 * 2C2020696E646578203D2000 .ascii ", index = \0"
631: 614 00000844 * .text
632: 615 0001B1A1 dd 8f00000838 pushl $L299
633: 616 0001B1A7 fe 08 effffffa8a callf $8,_writes
634: 617 0001B1AE # writed( index );
635: 618 0001B1AE dd effffffa84 pushl _index
636: 619 0001B1B4 fe 08 effffffa7d callf $8,_writed
637: 620 0001B1BB # writec('\n');
638: 621 0001B1BB dd 0a pushl $10
639: 622 0001B1BD fe 08 effffffa74 callf $8,_writec
640: 623 0001B1C4 # writes(" expected Acc = ");
641: 624 0001B1C4 .data 1
642: 625 00000844 * L300:
643: 626 00000844 * 2020202020202020202020202 .ascii " expected Acc = \0"
644: 0202020202020202020202020
645: 2020202020206578706563746
646: 56420416363203D2000
647: 627 00000873 * .text
648: 628 0001B1C4 dd 8f00000844 pushl $L300
649: 629 0001B1CA fe 08 effffffa67 callf $8,_writes
650: 630 0001B1D1 # write32h( dbl_expected.m );
651: 631 0001B1D1 dd effffffa61 pushl _dbl_expected
652: 632 0001B1D7 fe 08 effffffa5a callf $8,_write32h
653: 633 0001B1DE # writec(' ');
654: 634 0001B1DE dd 20 pushl $32
655: 635 0001B1E0 fe 08 effffffa51 callf $8,_writec
656: 636 0001B1E7 # write32h( dbl_expected.l );
657: 637 0001B1E7 dd effffffa4f pushl _dbl_expected+4
658: 638 0001B1ED fe 08 effffffa44 callf $8,_write32h
659: 639 0001B1F4 # writes("\n");
660: 640 0001B1F4 .data 1
661: 641 00000873 * L301:
662: 642 00000873 * 0A00 .ascii "\12\0"
663: 643 00000875 * .text
664: 644 0001B1F4 dd 8f00000873 pushl $L301
665: 645 0001B1FA fe 08 effffffa37 callf $8,_writes
666: 646 0001B201 # }
667: 647 0001B201 # if( halt_flg )
668: 648 0001B201 L294:
669: 649 0001B201 5d effffffa31 tstl _halt_flg
670: 650 0001B207 31 09 jeql L302
671: 651 0001B209 # tstd_er_halt( BAD_ACC_HLT ); /* halt on error */
672: 652 0001B209 dd 01 pushl $1
673: 653 0001B20B fe 08 ef00000088 callf $8,_tstd_er_halt
674: 654 0001B212 # if( loop_on_err ) {
675: 655 0001B212 L302:
676: 656 0001B212 5d effffffa20 tstl _loop_on_err
677: 657 0001B218 31 0a jeql L303
678: 658 0001B21A # force_loop = TRUE; /* set force loop flag */
679: 659 0001B21A 0d 01 effffffa17 movl $1,_force_loop
680: 660 0001B221 # asm("brw _tstd_3_lp1"); /* loop on the error */
681: 661 0001B221 13 fee1 brw _tstd_3_lp1
682: 662 0001B224 # } /* end of loop on error */
683: 663 0001B224 # } /* end of register corruption error */
684: 664 0001B224 L303:
685: 665 0001B224 # } /* end of tstd data WHILE loop */
686: 666 0001B224 L293:
687: 667 0001B224 L287:
688: 668 0001B224 6d effffffa0e incl _index
689: 669 0001B22A 13 fe79 jbr L289
690: 670 0001B22D L288:
691: 671 0001B22D # } /* end of subtest 3 */
692: 672 0001B22D 40 ret#2
693: 673 0001B22E .set L283,0x0
694: 674 0001B22E L285:
695: 675 0001B22E 13 fe62 jbr L286
696: 676 0001B231 .data
697: 677 00000720 * .text
698: 678 0001B231 00 .align 1
699: 679 0001B232 .globl _print_tstd_data
700: 680 0001B232 _print_tstd_data:
701: 681 0001B232 0000 .word L304
702: 682 0001B234 #
703: 683 0001B234 #
704: 684 0001B234 #
705: 685 0001B234 # /**************************************************************************
706: 686 0001B234 # *
707: 687 0001B234 # * PRINT THE DATA AND STORE RESULTS
708: 688 0001B234 # *
709: 689 0001B234 # * initial Acc = xxxxxxxx xxxxxxxx, final Acc = xxxxxxxx xxxxxxxx, index = xx
710: 690 0001B234 # **************************************************************************/
711: 691 0001B234 # print_tstd_data()
712: 692 0001B234 # {
713: 693 0001B234 11 61 jbr L306
714: 694 0001B236 L307:
715: 695 0001B236 # writes("initial Acc = ");
716: 696 0001B236 .data 1
717: 697 00000875 * L308:
718: 698 00000875 * 696E697469616C20416363203 .ascii "initial Acc = \0"
719: D2000
720: 699 00000884 * .text
721: 700 0001B236 dd 8f00000875 pushl $L308
722: 701 0001B23C fe 08 effffff9f5 callf $8,_writes
723: 702 0001B243 # write32h( dbl_ld_acc.m );
724: 703 0001B243 dd effffff9ef pushl _dbl_ld_acc
725: 704 0001B249 fe 08 effffff9e8 callf $8,_write32h
726: 705 0001B250 # writec(' ');
727: 706 0001B250 dd 20 pushl $32
728: 707 0001B252 fe 08 effffff9df callf $8,_writec
729: 708 0001B259 # write32h( dbl_ld_acc.l );
730: 709 0001B259 dd effffff9dd pushl _dbl_ld_acc+4
731: 710 0001B25F fe 08 effffff9d2 callf $8,_write32h
732: 711 0001B266 # writes(", final Acc = ");
733: 712 0001B266 .data 1
734: 713 00000884 * L309:
735: 714 00000884 * 2C202066696E616C204163632 .ascii ", final Acc = \0"
736: 03D2000
737: 715 00000894 * .text
738: 716 0001B266 dd 8f00000884 pushl $L309
739: 717 0001B26C fe 08 effffff9c5 callf $8,_writes
740: 718 0001B273 # write32h( dbl_st_acc.m );
741: 719 0001B273 dd effffff9bf pushl _dbl_st_acc
742: 720 0001B279 fe 08 effffff9b8 callf $8,_write32h
743: 721 0001B280 # writec(' ');
744: 722 0001B280 dd 20 pushl $32
745: 723 0001B282 fe 08 effffff9af callf $8,_writec
746: 724 0001B289 # write32h( dbl_st_acc.l );
747: 725 0001B289 dd effffff9ad pushl _dbl_st_acc+4
748: 726 0001B28F fe 08 effffff9a2 callf $8,_write32h
749: 727 0001B296 # }
750: 728 0001B296 40 ret#2
751: 729 0001B297 .set L304,0x0
752: 730 0001B297 L306:
753: 731 0001B297 11 9d jbr L307
754: 732 0001B299 .data
755: 733 00000720 * .text
756: 734 0001B299 00 .align 1
757: 735 0001B29A .globl _tstd_er_halt
758: 736 0001B29A _tstd_er_halt:
759: 737 0001B29A 0000 .word L310
760: 738 0001B29C #
761: 739 0001B29C #
762: 740 0001B29C #
763: 741 0001B29C # /**************************************************************************
764: 742 0001B29C # *
765: 743 0001B29C # * HALT ON ERROR ROUTINE
766: 744 0001B29C # *
767: 745 0001B29C # **************************************************************************/
768: 746 0001B29C # tstd_er_halt( halt_code )
769: 747 0001B29C # int halt_code;
770: 748 0001B29C # {
771: 749 0001B29C 13 00b6 jbr L312
772: 750 0001B29F L313:
773: 751 0001B29F # sgl_dummy1 = halt_code; /* get the error type */
774: 752 0001B29F 0d ad04 effffff991 movl 4(fp),_sgl_dummy1
775: 753 0001B2A7 # asm("movl _test_no,r0"); /* r0 = test number */
776: 754 0001B2A7 0d effffff98b 50 movl _test_no,r0
777: 755 0001B2AE # asm("movl _subtest,r1"); /* r1 = subtest number */
778: 756 0001B2AE 0d effffff984 51 movl _subtest,r1
779: 757 0001B2B5 # asm("movl _sgl_dummy1,r2"); /* r2 = error code */
780: 758 0001B2B5 0d effffff97d 52 movl _sgl_dummy1,r2
781: 759 0001B2BC # asm("movl _cycle,r3"); /* r3 = cycle count */
782: 760 0001B2BC 0d effffff976 53 movl _cycle,r3
783: 761 0001B2C3 # asm("movl _dbl_ld_acc,r4"); /* r4 = MS of init Acc */
784: 762 0001B2C3 0d effffff96f 54 movl _dbl_ld_acc,r4
785: 763 0001B2CA # asm("movl _dbl_ld_acc+4,r5"); /* r5 = LS of init Acc */
786: 764 0001B2CA 0d effffff96c 55 movl _dbl_ld_acc+4,r5
787: 765 0001B2D1 # asm("movl _psl_val,r6"); /* r6 = final PSL */
788: 766 0001B2D1 0d effffff961 56 movl _psl_val,r6
789: 767 0001B2D8 # if( halt_code == BAD_ACC_HLT ) {
790: 768 0001B2D8 1d ad04 01 cmpl 4(fp),$1
791: 769 0001B2DC 21 1e jneq L314
792: 770 0001B2DE # asm("movl _dbl_st_acc,r7"); /* r7 = MS of final Acc */
793: 771 0001B2DE 0d effffff954 57 movl _dbl_st_acc,r7
794: 772 0001B2E5 # asm("movl _dbl_st_acc+4,r8"); /* r8 = LS of final Acc */
795: 773 0001B2E5 0d effffff951 58 movl _dbl_st_acc+4,r8
796: 774 0001B2EC # asm("movl _dbl_expected,r9"); /* r9 = MS of expected */
797: 775 0001B2EC 0d effffff946 59 movl _dbl_expected,r9
798: 776 0001B2F3 # asm("movl _dbl_expected+4,r10"); /* r10 = LS of expected */
799: 777 0001B2F3 0d effffff943 5a movl _dbl_expected+4,r10
800: 778 0001B2FA # } else
801: 779 0001B2FA 11 57 jbr L315
802: 780 0001B2FC L314:
803: 781 0001B2FC # if( halt_code == BAD_REG_HLT ) {
804: 782 0001B2FC 1d ad04 02 cmpl 4(fp),$2
805: 783 0001B300 21 3d jneq L316
806: 784 0001B302 # sgl_dummy1 = load_regs[index2];
807: 785 0001B302 0d effffff930 50 movl _index2,r0
808: 786 0001B309 0d 40effffff928 movl _load_regs[r0],_sgl_dummy1
809: effffff923
810: 787 0001B315 # sgl_dummy2 = store_regs[index2];
811: 788 0001B315 0d effffff91d 50 movl _index2,r0
812: 789 0001B31C 0d 40effffff915 movl _store_regs[r0],_sgl_dummy2
813: effffff910
814: 790 0001B328 # asm("movl _index2,r7"); /* r7 = bad register # */
815: 791 0001B328 0d effffff90a 57 movl _index2,r7
816: 792 0001B32F # asm("movl _sgl_dummy2,r8"); /* r8 = actual value */
817: 793 0001B32F 0d effffff903 58 movl _sgl_dummy2,r8
818: 794 0001B336 # asm("movl _sgl_dummy1,r9"); /* r9 = expected value */
819: 795 0001B336 0d effffff8fc 59 movl _sgl_dummy1,r9
820: 796 0001B33D # } else
821: 797 0001B33D 11 14 jbr L317
822: 798 0001B33F L316:
823: 799 0001B33F # if( halt_code == BAD_PSL_HLT ) {
824: 800 0001B33F 1d ad04 03 cmpl 4(fp),$3
825: 801 0001B343 21 0e jneq L318
826: 802 0001B345 # asm("movl _exp_psl,r7"); /* r7 = expected PSL */
827: 803 0001B345 0d effffff8ed 57 movl _exp_psl,r7
828: 804 0001B34C # asm("movl _index,r8"); /* r8 = data index */
829: 805 0001B34C 0d effffff8e6 58 movl _index,r8
830: 806 0001B353 # };
831: 807 0001B353 L318:
832: 808 0001B353 L317:
833: 809 0001B353 L315:
834: 810 0001B353 # asm("halt"); /* HALT ... */
835: 811 0001B353 00 halt
836: 812 0001B354 # }
837: 813 0001B354 40 ret#2
838: 814 0001B355 .set L310,0x0
839: 815 0001B355 L312:
840: 816 0001B355 13 ff47 jbr L313
841: 817 00000720 * .data
842: 817 00000720 * .data
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