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Up to [Power 6/32 Unix Tahoe 4.2BSD] / cci / d / macro4|
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Power 6/32 Unix version 1.21
1 00000000 LL0:
2 00000000 .data
3 00000720 * .text
4 00000000 .align 1
5 00000000 .globl _tstd
6 00000000 _tstd:
7 0001AC38 0000 .word L215
8 0001AC3A #
9 0001AC3A # #include "fpp_defs.h"
10 0001AC3A #
11 0001AC3A #
12 0001AC3A # /*****************************************************************************
13 0001AC3A # *
14 0001AC3A # * TSTD - DOUBLE PRECISION FLOATING POINT TEST ACC. TEST
15 0001AC3A # *
16 0001AC3A # * IMPLEMENTATION NOTE: If the "no-fpp WCS" is loaded then the status bits
17 0001AC3A # * set will be based on the INTEGER value of the loaded data's most significant
18 0001AC3A # * longword. Ergo and towit, if we're running without an FPP and a "bad 0" is
19 0001AC3A # * loaded then the PSL will show POSITIVE rather than ZERO. A "bad 0" is any
20 0001AC3A # * number with a zero exponent and non zero fraction (00000001 - 007fffff).
21 0001AC3A # *****************************************************************************/
22 0001AC3A # tstd()
23 0001AC3A # {
24 0001AC3A 11 3a jbr L217
25 0001AC3C L218:
26 0001AC3C # asm(".globl _tstd_t");
27 0001AC3C .globl _tstd_t
28 0001AC3C # asm("_tstd_t:"); /* entry address */
29 0001AC3C _tstd_t:
30 0001AC3C # if( ( cycle == 1 ) && ( prt_hdrs ) ) /* print headers on 1st pass */
31 0001AC3C 1d effffffff6 01 cmpl _cycle,$1
32 0001AC43 21 15 jneq L219
33 0001AC45 5d efffffffed tstl _prt_hdrs
34 0001AC4B 31 0d jeql L219
35 0001AC4D # writes(" TSTD");
36 0001AC4D .data 1
37 00000720 * L221:
38 00000720 * 205453544400 .ascii " TSTD\0"
39 00000726 * .text
40 0001AC4D dd 8f00000720 pushl $L221
41 0001AC53 fe 08 efffffffde callf $8,_writes
42 0001AC5A # tstd_1(); /* PSL flags test */
43 0001AC5A L219:
44 0001AC5A fe 04 ef00000017 callf $4,_tstd_1
45 0001AC61 # tstd_2(); /* register stability */
46 0001AC61 fe 04 ef00000218 callf $4,_tstd_2
47 0001AC68 # tstd_3(); /* accumulator stability */
48 0001AC68 fe 04 ef0000041f callf $4,_tstd_3
49 0001AC6F # asm("jmp *return"); /* return to the test monitor */
50 0001AC6F 71 ffffffffc3 jmp *return
51 0001AC75 # }
52 0001AC75 40 ret#2
53 0001AC76 .set L215,0x0
54 0001AC76 L217:
55 0001AC76 11 c4 jbr L218
56 0001AC78 .data
57 00000720 * .text
58 0001AC78 .align 1
59 0001AC78 .globl _tstd_1
60 0001AC78 _tstd_1:
61 0001AC78 0000 .word L225
62 0001AC7A #
63 0001AC7A #
64 0001AC7A #
65 0001AC7A # /************************************************************************
66 0001AC7A # *
67 0001AC7A # * SUBTEST 1 - Check for PSL corruption
68 0001AC7A # *
69 0001AC7A # ************************************************************************/
70 0001AC7A # tstd_1()
71 0001AC7A # {
72 0001AC7A 13 0200 jbr L227
73 0001AC7D L228:
74 0001AC7D # force_loop = FALSE; /* clear force_loop flg */
75 0001AC7D 4d efffffffb5 clrl _force_loop
76 0001AC83 # subtest = 1;
77 0001AC83 0d 01 efffffffae movl $1,_subtest
78 0001AC8A # for( index = 0; index < max_tstd_1_index; index++ ) {
79 0001AC8A 4d efffffffa8 clrl _index
80 0001AC90 L231:
81 0001AC90 1d efffffffa2 efffffff9d cmpl _index,_max_tstd_1_index
82 0001AC9B 91 03 13 01dc jgeq L230
83 0001ACA0 # dbl_ld_acc = tstd_1_data[index].ld; /* get value to load */
84 0001ACA0 5c 0c efffffff91 50 mull3 $12,_index,r0
85 0001ACA8 0c 8f00000000 50 addl2 $_tstd_1_data,r0
86 0001ACAF 0d a004 efffffff85 movl 4(r0),_dbl_ld_acc+4
87 0001ACB7 0d 60 efffffff7a movl (r0),_dbl_ld_acc
88 0001ACBE # sgl_expected = tstd_1_data[index].exp; /* get expected flags*/
89 0001ACBE 5c 0c efffffff73 50 mull3 $12,_index,r0
90 0001ACC6 0d e000000008 efffffff67 movl _tstd_1_data+8(r0),_sgl_expected
91 0001ACD1 # for( status_index = 0; status_index < 3; status_index++ ) {
92 0001ACD1 4d efffffff61 clrl _status_index
93 0001ACD7 L234:
94 0001ACD7 1d efffffff5b 03 cmpl _status_index,$3
95 0001ACDE 91 03 13 0190 jgeq L233
96 0001ACE3 # sgl_dummy1 = status_array[status_index]; /* status = +,-,0 */
97 0001ACE3 0d efffffff4f 50 movl _status_index,r0
98 0001ACEA 0d 40efffffff47 movl _status_array[r0],_sgl_dummy1
efffffff42
99 0001ACF6 # /*
100 0001ACF6 # * If LOOP ON ERROR is set, this is the loop for this subtest.
101 0001ACF6 # * The force loop flag is set after the first error.
102 0001ACF6 # */
103 0001ACF6 # asm("ldd _dbl_ld_acc"); /* load the initial value */
104 0001ACF6 07 efffffff3c ldd _dbl_ld_acc
105 0001ACFC # asm("_tstd_1_lp1:");
106 0001ACFC _tstd_1_lp1:
107 0001ACFC # asm("tstl _sgl_dummy1"); /* set the PSL status */
108 0001ACFC 5d efffffff36 tstl _sgl_dummy1
109 0001AD02 # asm("movpsl _init_psl"); /* save the initial PSL */
110 0001AD02 cd efffffff30 movpsl _init_psl
111 0001AD08 # asm("tstd"); /* test the accmulator */
112 0001AD08 57 tstd
113 0001AD09 # asm("nop");
114 0001AD09 10 nop
115 0001AD0A # asm("movpsl _psl_val"); /* save the final PSL */
116 0001AD0A cd efffffff28 movpsl _psl_val
117 0001AD10 # asm("std _dbl_st_acc"); /* save the final Acc. */
118 0001AD10 27 efffffff22 std _dbl_st_acc
119 0001AD16 # if( force_loop )
120 0001AD16 5d efffffff1c tstl _force_loop
121 0001AD1C 31 02 jeql L235
122 0001AD1E # asm("brb _tstd_1_lp1");; /* loop on the error */
123 0001AD1E 11 dc brb _tstd_1_lp1
124 0001AD20 L235:
125 0001AD20 # /*
126 0001AD20 # * Now compare the final PSL to the initial PSL -they should be the same
127 0001AD20 # */
128 0001AD20 # exp_psl = init_psl; /* get the initial PSL */
129 0001AD20 0d efffffff12 efffffff0d movl _init_psl,_exp_psl
130 0001AD2B # exp_psl &= 0xfffffff3; /* clear ZERO, NEGATIVE */
131 0001AD2B ac 88f3 efffffff05 andl2 $-13,_exp_psl
132 0001AD33 # if( sgl_expected == ZERO ) {
133 0001AD33 1d effffffeff 04 cmpl _sgl_expected,$4
134 0001AD3A 21 07 jneq L236
135 0001AD3C # /* if( (!no_fpp_wcs) || (!dbl_ld_acc.m) ) /* */
136 0001AD3C # exp_psl |= PSL_Z; /* expect the ZERO bit set */
137 0001AD3C 8c 04 effffffef5 orl2 $4,_exp_psl
138 0001AD43 # }
139 0001AD43 # if( sgl_expected == NEGATIVE )
140 0001AD43 L236:
141 0001AD43 1d effffffeef 08 cmpl _sgl_expected,$8
142 0001AD4A 21 07 jneq L237
143 0001AD4C # exp_psl |= PSL_N; /* expect the NEG bit set */
144 0001AD4C 8c 08 effffffee5 orl2 $8,_exp_psl
145 0001AD53 # if( psl_val != exp_psl ) {
146 0001AD53 L237:
147 0001AD53 1d effffffedf effffffeda cmpl _psl_val,_exp_psl
148 0001AD5E 21 03 13 0107 jeql L238
149 0001AD63 # errcnt++; /* bump the error count */
150 0001AD63 6d effffffecf incl _errcnt
151 0001AD69 # if( prt_error ) {
152 0001AD69 5d effffffec9 tstl _prt_error
153 0001AD6F 21 03 13 00d3 jeql L239
154 0001AD74 # writes(" \n"); /* start new print line */
155 0001AD74 .data 1
156 00000726 * L240:
157 00000726 * 200A00 .ascii " \12\0"
158 00000729 * .text
159 0001AD74 dd 8f00000726 pushl $L240
160 0001AD7A fe 08 effffffeb7 callf $8,_writes
161 0001AD81 # writes("cycle: ");
162 0001AD81 .data 1
163 00000729 * L241:
164 00000729 * 6379636C653A2000 .ascii "cycle: \0"
165 00000731 * .text
166 0001AD81 dd 8f00000729 pushl $L241
167 0001AD87 fe 08 effffffeaa callf $8,_writes
168 0001AD8E # writed( cycle );
169 0001AD8E dd effffffea4 pushl _cycle
170 0001AD94 fe 08 effffffe9d callf $8,_writed
171 0001AD9B # writes(" TSTD test ");
172 0001AD9B .data 1
173 00000731 * L243:
174 00000731 * 2020545354442074657374200 .ascii " TSTD test \0"
0
175 0000073e * .text
176 0001AD9B dd 8f00000731 pushl $L243
177 0001ADA1 fe 08 effffffe90 callf $8,_writes
178 0001ADA8 # writed( test_no );
179 0001ADA8 dd effffffe8a pushl _test_no
180 0001ADAE fe 08 effffffe83 callf $8,_writed
181 0001ADB5 # writes(", subtest 1 - BAD FINAL PSL\n");
182 0001ADB5 .data 1
183 0000073e * L244:
184 0000073e * 2C20737562746573742031202 .ascii ", subtest 1 - BAD FINAL PSL\12\0"
D204241442046494E414C2050
534C0A00
185 0000075b * .text
186 0001ADB5 dd 8f0000073e pushl $L244
187 0001ADBB fe 08 effffffe76 callf $8,_writes
188 0001ADC2 # print_tstd_data(); /* print the operands */
189 0001ADC2 fe 04 ef00000469 callf $4,_print_tstd_data
190 0001ADC9 # writes(", index = ");
191 0001ADC9 .data 1
192 0000075b * L246:
193 0000075b * 2C2020696E646578203D2000 .ascii ", index = \0"
194 00000767 * .text
195 0001ADC9 dd 8f0000075b pushl $L246
196 0001ADCF fe 08 effffffe62 callf $8,_writes
197 0001ADD6 # writed( index );
198 0001ADD6 dd effffffe5c pushl _index
199 0001ADDC fe 08 effffffe55 callf $8,_writed
200 0001ADE3 # writec('\n');
201 0001ADE3 dd 0a pushl $10
202 0001ADE5 fe 08 effffffe4c callf $8,_writec
203 0001ADEC # writes("initial PSL = ");
204 0001ADEC .data 1
205 00000767 * L248:
206 00000767 * 696E697469616C2050534C203 .ascii "initial PSL = \0"
D2000
207 00000776 * .text
208 0001ADEC dd 8f00000767 pushl $L248
209 0001ADF2 fe 08 effffffe3f callf $8,_writes
210 0001ADF9 # write32h( init_psl );
211 0001ADF9 dd effffffe39 pushl _init_psl
212 0001ADFF fe 08 effffffe32 callf $8,_write32h
213 0001AE06 # writes(", final PSL = ");
214 0001AE06 .data 1
215 00000776 * L250:
216 00000776 * 2C202066696E616C2050534C2 .ascii ", final PSL = \0"
03D2000
217 00000786 * .text
218 0001AE06 dd 8f00000776 pushl $L250
219 0001AE0C fe 08 effffffe25 callf $8,_writes
220 0001AE13 # write32h( psl_val );
221 0001AE13 dd effffffe1f pushl _psl_val
222 0001AE19 fe 08 effffffe18 callf $8,_write32h
223 0001AE20 # writes(", expected PSL = ");
224 0001AE20 .data 1
225 00000786 * L251:
226 00000786 * 2C20206578706563746564205 .ascii ", expected PSL = \0"
0534C203D2000
227 00000799 * .text
228 0001AE20 dd 8f00000786 pushl $L251
229 0001AE26 fe 08 effffffe0b callf $8,_writes
230 0001AE2D # write32h( exp_psl );
231 0001AE2D dd effffffe05 pushl _exp_psl
232 0001AE33 fe 08 effffffdfe callf $8,_write32h
233 0001AE3A # writes("\n");
234 0001AE3A .data 1
235 00000799 * L252:
236 00000799 * 0A00 .ascii "\12\0"
237 0000079b * .text
238 0001AE3A dd 8f00000799 pushl $L252
239 0001AE40 fe 08 effffffdf1 callf $8,_writes
240 0001AE47 # }
241 0001AE47 # if( halt_flg )
242 0001AE47 L239:
243 0001AE47 5d effffffdeb tstl _halt_flg
244 0001AE4D 31 09 jeql L253
245 0001AE4F # tstd_er_halt( BAD_PSL_HLT ); /* halt on error */
246 0001AE4F dd 03 pushl $3
247 0001AE51 fe 08 ef00000442 callf $8,_tstd_er_halt
248 0001AE58 # if( loop_on_err ) {
249 0001AE58 L253:
250 0001AE58 5d effffffdda tstl _loop_on_err
251 0001AE5E 31 0a jeql L255
252 0001AE60 # force_loop = TRUE; /* set force loop flag */
253 0001AE60 0d 01 effffffdd1 movl $1,_force_loop
254 0001AE67 # asm("brw _tstd_1_lp1"); /* loop on the error */
255 0001AE67 13 fe92 brw _tstd_1_lp1
256 0001AE6A # } /* end of loop on error */
257 0001AE6A # } /* end of PSL corruption error */
258 0001AE6A L255:
259 0001AE6A # } /* end of initial status WHILE loop */
260 0001AE6A L238:
261 0001AE6A L232:
262 0001AE6A 6d effffffdc8 incl _status_index
263 0001AE70 13 fe64 jbr L234
264 0001AE73 L233:
265 0001AE73 # } /* end of data pattern WHILE loop */
266 0001AE73 L229:
267 0001AE73 6d effffffdbf incl _index
268 0001AE79 13 fe14 jbr L231
269 0001AE7C L230:
270 0001AE7C # } /* end of subtest 1 */
271 0001AE7C 40 ret#2
272 0001AE7D .set L225,0x0
273 0001AE7D L227:
274 0001AE7D 13 fdfd jbr L228
275 0001AE80 .data
276 00000720 * .text
277 0001AE80 .align 1
278 0001AE80 .globl _tstd_2
279 0001AE80 _tstd_2:
280 0001AE80 0000 .word L256
281 0001AE82 #
282 0001AE82 #
283 0001AE82 #
284 0001AE82 # /************************************************************************
285 0001AE82 # *
286 0001AE82 # * SUBTEST 2 - Check for register corruption
287 0001AE82 # *
288 0001AE82 # ************************************************************************/
289 0001AE82 # tstd_2()
290 0001AE82 # {
291 0001AE82 13 0205 jbr L258
292 0001AE85 L259:
293 0001AE85 # force_loop = FALSE; /* clear force_loop flg */
294 0001AE85 4d effffffdad clrl _force_loop
295 0001AE8B # subtest = 2;
296 0001AE8B 0d 02 effffffda6 movl $2,_subtest
297 0001AE92 # fill_reg_buf( load_regs ); /* get patterns for regs */
298 0001AE92 dd 8f00000000 pushl $_load_regs
299 0001AE98 fe 08 effffffd99 callf $8,_fill_reg_buf
300 0001AE9F # for( index = 0; index < max_tstd_1_index; index++ ) {
301 0001AE9F 4d effffffd93 clrl _index
302 0001AEA5 L263:
303 0001AEA5 1d effffffd8d effffffd88 cmpl _index,_max_tstd_1_index
304 0001AEB0 91 03 13 01d4 jgeq L262
305 0001AEB5 # dbl_ld_acc = tstd_1_data[index].ld; /* get value to load */
306 0001AEB5 5c 0c effffffd7c 50 mull3 $12,_index,r0
307 0001AEBD 0c 8f00000000 50 addl2 $_tstd_1_data,r0
308 0001AEC4 0d a004 effffffd70 movl 4(r0),_dbl_ld_acc+4
309 0001AECC 0d 60 effffffd65 movl (r0),_dbl_ld_acc
310 0001AED3 # sgl_expected = tstd_1_data[index].exp; /* get expected flags*/
311 0001AED3 5c 0c effffffd5e 50 mull3 $12,_index,r0
312 0001AEDB 0d e000000008 effffffd52 movl _tstd_1_data+8(r0),_sgl_expected
313 0001AEE6 # for( status_index = 0; status_index < 3; status_index++ ) {
314 0001AEE6 4d effffffd4c clrl _status_index
315 0001AEEC L266:
316 0001AEEC 1d effffffd46 03 cmpl _status_index,$3
317 0001AEF3 91 03 13 0188 jgeq L265
318 0001AEF8 # sgl_dummy1 = status_array[status_index]; /* status = +,-,0 */
319 0001AEF8 0d effffffd3a 50 movl _status_index,r0
320 0001AEFF 0d 40effffffd32 movl _status_array[r0],_sgl_dummy1
effffffd2d
321 0001AF0B # /*
322 0001AF0B # * If LOOP ON ERROR is set, this is the loop for this subtest.
323 0001AF0B # * The force loop flag is set after the first error.
324 0001AF0B # */
325 0001AF0B # asm("_tstd_2_lp1:");
326 0001AF0B _tstd_2_lp1:
327 0001AF0B # asm("ldd _dbl_ld_acc"); /* load the Acc. */
328 0001AF0B 07 effffffd27 ldd _dbl_ld_acc
329 0001AF11 # asm("loadr $0x1fff,_load_regs"); /* load regs 0 - 12 */
330 0001AF11 ab 891fff effffffd1e loadr $0x1fff,_load_regs
331 0001AF1A # asm("nop");
332 0001AF1A 10 nop
333 0001AF1B # asm("tstd"); /* test the acc. */
334 0001AF1B 57 tstd
335 0001AF1C # asm("nop");
336 0001AF1C 10 nop
337 0001AF1D # asm("storer $0x1fff,_store_regs"); /* store regs 0 - 12 */
338 0001AF1D bb 891fff effffffd12 storer $0x1fff,_store_regs
339 0001AF26 # asm("std _dbl_st_acc"); /* save the acc. */
340 0001AF26 27 effffffd0c std _dbl_st_acc
341 0001AF2C # if( force_loop )
342 0001AF2C 5d effffffd06 tstl _force_loop
343 0001AF32 31 02 jeql L267
344 0001AF34 # asm("brb _tstd_2_lp1");; /* loop on the error */
345 0001AF34 11 d5 brb _tstd_2_lp1
346 0001AF36 L267:
347 0001AF36 # /*
348 0001AF36 # * Now compare the stored register values to those that were loaded
349 0001AF36 # */
350 0001AF36 # index2 = 0;
351 0001AF36 4d effffffcfc clrl _index2
352 0001AF3C # while( (load_regs[index2] == store_regs[index2]) &&
353 0001AF3C # (index2 < 13) )
354 0001AF3C L268:
355 0001AF3C 0d effffffcf6 50 movl _index2,r0
356 0001AF43 0d effffffcef 51 movl _index2,r1
357 0001AF4A 1d 40effffffce7 cmpl _load_regs[r0],_store_regs[r1]
41effffffce1
358 0001AF57 21 11 jneq L269
359 0001AF59 1d effffffcd9 0d cmpl _index2,$13
360 0001AF60 81 08 jgeq L269
361 0001AF62 # index2++; /* check reg values */
362 0001AF62 6d effffffcd0 incl _index2
363 0001AF68 11 d2 jbr L268
364 0001AF6A L269:
365 0001AF6A # if( index2 < 13 ) { /* error if index2 < 13 */
366 0001AF6A 1d effffffcc8 0d cmpl _index2,$13
367 0001AF71 91 03 13 0101 jgeq L270
368 0001AF76 # errcnt++; /* bump the error count */
369 0001AF76 6d effffffcbc incl _errcnt
370 0001AF7C # if( prt_error ) {
371 0001AF7C 5d effffffcb6 tstl _prt_error
372 0001AF82 21 03 13 00cd jeql L271
373 0001AF87 # writes(" \n"); /* start a new print line */
374 0001AF87 .data 1
375 0000079b * L272:
376 0000079b * 200A00 .ascii " \12\0"
377 0000079e * .text
378 0001AF87 dd 8f0000079b pushl $L272
379 0001AF8D fe 08 effffffca4 callf $8,_writes
380 0001AF94 # writes("cycle: ");
381 0001AF94 .data 1
382 0000079e * L273:
383 0000079e * 6379636C653A2000 .ascii "cycle: \0"
384 000007a6 * .text
385 0001AF94 dd 8f0000079e pushl $L273
386 0001AF9A fe 08 effffffc97 callf $8,_writes
387 0001AFA1 # writed( cycle );
388 0001AFA1 dd effffffc91 pushl _cycle
389 0001AFA7 fe 08 effffffc8a callf $8,_writed
390 0001AFAE # writes(" TSTD test ");
391 0001AFAE .data 1
392 000007a6 * L274:
393 000007a6 * 2020545354442074657374200 .ascii " TSTD test \0"
0
394 000007b3 * .text
395 0001AFAE dd 8f000007a6 pushl $L274
396 0001AFB4 fe 08 effffffc7d callf $8,_writes
397 0001AFBB # writed( test_no );
398 0001AFBB dd effffffc77 pushl _test_no
399 0001AFC1 fe 08 effffffc70 callf $8,_writed
400 0001AFC8 # writes(", subtest 2 - A REGISTER WAS MODIFIED\n");
401 0001AFC8 .data 1
402 000007b3 * L275:
403 000007b3 * 2C20737562746573742032202 .ascii ", subtest 2 - A REGISTER WAS MODIFIED\12\0"
D204120524547495354455220
574153204D4F4449464945440
A00
404 000007da * .text
405 0001AFC8 dd 8f000007b3 pushl $L275
406 0001AFCE fe 08 effffffc63 callf $8,_writes
407 0001AFD5 # print_tstd_data(); /* print the operands */
408 0001AFD5 fe 04 ef00000256 callf $4,_print_tstd_data
409 0001AFDC # writes("\n");
410 0001AFDC .data 1
411 000007da * L276:
412 000007da * 0A00 .ascii "\12\0"
413 000007dc * .text
414 0001AFDC dd 8f000007da pushl $L276
415 0001AFE2 fe 08 effffffc4f callf $8,_writes
416 0001AFE9 # writes("register "); /* print the information */
417 0001AFE9 .data 1
418 000007dc * L277:
419 000007dc * 72656769737465722000 .ascii "register \0"
420 000007e6 * .text
421 0001AFE9 dd 8f000007dc pushl $L277
422 0001AFEF fe 08 effffffc42 callf $8,_writes
423 0001AFF6 # writed( index2 ); /* about the corrupted */
424 0001AFF6 dd effffffc3c pushl _index2
425 0001AFFC fe 08 effffffc35 callf $8,_writed
426 0001B003 # writes(" = "); /* register */
427 0001B003 .data 1
428 000007e6 * L278:
429 000007e6 * 203D2000 .ascii " = \0"
430 000007ea * .text
431 0001B003 dd 8f000007e6 pushl $L278
432 0001B009 fe 08 effffffc28 callf $8,_writes
433 0001B010 # write32h( store_regs[index2] );
434 0001B010 0d effffffc22 50 movl _index2,r0
435 0001B017 dd 40effffffc1a pushl _store_regs[r0]
436 0001B01E fe 08 effffffc13 callf $8,_write32h
437 0001B025 # writes(", should be = ");
438 0001B025 .data 1
439 000007ea * L279:
440 000007ea * 2C202073686F756C642062652 .ascii ", should be = \0"
03D2000
441 000007fa * .text
442 0001B025 dd 8f000007ea pushl $L279
443 0001B02B fe 08 effffffc06 callf $8,_writes
444 0001B032 # write32h( load_regs[index2] );
445 0001B032 0d effffffc00 50 movl _index2,r0
446 0001B039 dd 40effffffbf8 pushl _load_regs[r0]
447 0001B040 fe 08 effffffbf1 callf $8,_write32h
448 0001B047 # writes("\n");
449 0001B047 .data 1
450 000007fa * L280:
451 000007fa * 0A00 .ascii "\12\0"
452 000007fc * .text
453 0001B047 dd 8f000007fa pushl $L280
454 0001B04D fe 08 effffffbe4 callf $8,_writes
455 0001B054 # }
456 0001B054 # if( halt_flg )
457 0001B054 L271:
458 0001B054 5d effffffbde tstl _halt_flg
459 0001B05A 31 09 jeql L281
460 0001B05C # tstd_er_halt( BAD_REG_HLT ); /* halt on error */
461 0001B05C dd 02 pushl $2
462 0001B05E fe 08 ef00000235 callf $8,_tstd_er_halt
463 0001B065 # if( loop_on_err ) {
464 0001B065 L281:
465 0001B065 5d effffffbcd tstl _loop_on_err
466 0001B06B 31 0a jeql L282
467 0001B06D # force_loop = TRUE; /* set force loop flag */
468 0001B06D 0d 01 effffffbc4 movl $1,_force_loop
469 0001B074 # asm("brw _tstd_2_lp1"); /* loop on the error */
470 0001B074 13 fe94 brw _tstd_2_lp1
471 0001B077 # } /* end of loop on error */
472 0001B077 # } /* end of register corruption error */
473 0001B077 L282:
474 0001B077 # } /* end of initial PSL WHILE loop */
475 0001B077 L270:
476 0001B077 L264:
477 0001B077 6d effffffbbb incl _status_index
478 0001B07D 13 fe6c jbr L266
479 0001B080 L265:
480 0001B080 # } /* end of tstd data WHILE loop */
481 0001B080 L261:
482 0001B080 6d effffffbb2 incl _index
483 0001B086 13 fe1c jbr L263
484 0001B089 L262:
485 0001B089 # } /* end of subtest 2 */
486 0001B089 40 ret#2
487 0001B08A .set L256,0x0
488 0001B08A L258:
489 0001B08A 13 fdf8 jbr L259
490 0001B08D .data
491 00000720 * .text
492 0001B08D 00 .align 1
493 0001B08E .globl _tstd_3
494 0001B08E _tstd_3:
495 0001B08E 0000 .word L283
496 0001B090 #
497 0001B090 #
498 0001B090 #
499 0001B090 #
500 0001B090 # /************************************************************************
501 0001B090 # *
502 0001B090 # * SUBTEST 3 - Check for accumulator corruption
503 0001B090 # *
504 0001B090 # ************************************************************************/
505 0001B090 # tstd_3()
506 0001B090 # {
507 0001B090 13 019b jbr L285
508 0001B093 L286:
509 0001B093 # force_loop = FALSE; /* clear force_loop flg */
510 0001B093 4d effffffb9f clrl _force_loop
511 0001B099 # subtest = 3;
512 0001B099 0d 03 effffffb98 movl $3,_subtest
513 0001B0A0 # for( index = 0; index < max_tstd_1_index; index++ ) {
514 0001B0A0 4d effffffb92 clrl _index
515 0001B0A6 L289:
516 0001B0A6 1d effffffb8c effffffb87 cmpl _index,_max_tstd_1_index
517 0001B0B1 91 03 13 0177 jgeq L288
518 0001B0B6 # dbl_ld_acc = tstd_1_data[index].ld; /* get value to load */
519 0001B0B6 5c 0c effffffb7b 50 mull3 $12,_index,r0
520 0001B0BE 0c 8f00000000 50 addl2 $_tstd_1_data,r0
521 0001B0C5 0d a004 effffffb6f movl 4(r0),_dbl_ld_acc+4
522 0001B0CD 0d 60 effffffb64 movl (r0),_dbl_ld_acc
523 0001B0D4 # if( !(dbl_ld_acc.m & 0x7f800000) ) {
524 0001B0D4 3d 8f7f800000 effffffb59 bitl $2139095040,_dbl_ld_acc
525 0001B0DF 21 0e jneq L290
526 0001B0E1 # dbl_expected.m = 0;
527 0001B0E1 4d effffffb51 clrl _dbl_expected
528 0001B0E7 # dbl_expected.l = 0; /* ignore bad 0's */
529 0001B0E7 4d effffffb4f clrl _dbl_expected+4
530 0001B0ED # } else
531 0001B0ED 11 16 jbr L291
532 0001B0EF L290:
533 0001B0EF # dbl_expected = dbl_ld_acc;
534 0001B0EF 0d effffffb47 effffffb42 movl _dbl_ld_acc+4,_dbl_expected+4
535 0001B0FA 0d effffffb38 effffffb33 movl _dbl_ld_acc,_dbl_expected
536 0001B105 L291:
537 0001B105 # /*
538 0001B105 # * If LOOP ON ERROR is set, this is the loop for this subtest.
539 0001B105 # * The force loop flag is set after the first error.
540 0001B105 # */
541 0001B105 # asm("_tstd_3_lp1:");
542 0001B105 _tstd_3_lp1:
543 0001B105 # asm("ldd _dbl_ld_acc");
544 0001B105 07 effffffb2d ldd _dbl_ld_acc
545 0001B10B # asm("nop");
546 0001B10B 10 nop
547 0001B10C # asm("tstd"); /* test the accumulator */
548 0001B10C 57 tstd
549 0001B10D # asm("nop");
550 0001B10D 10 nop
551 0001B10E # asm("std _dbl_st_acc"); /* save the accumulator */
552 0001B10E 27 effffffb24 std _dbl_st_acc
553 0001B114 # if( force_loop )
554 0001B114 5d effffffb1e tstl _force_loop
555 0001B11A 31 02 jeql L292
556 0001B11C # asm("brb _tstd_3_lp1");; /* loop on the error */
557 0001B11C 11 e7 brb _tstd_3_lp1
558 0001B11E L292:
559 0001B11E # /*
560 0001B11E # * Now compare the stored register values to those that were loaded
561 0001B11E # */
562 0001B11E # if( (dbl_st_acc.m != dbl_expected.m ) || /* Acc corrupted? */
563 0001B11E # (dbl_st_acc.l != dbl_expected.l) ) {
564 0001B11E 1d effffffb14 effffffb0f cmpl _dbl_st_acc,_dbl_expected
565 0001B129 21 10 jneq L9999
566 0001B12B 1d effffffb0b effffffb06 cmpl _dbl_st_acc+4,_dbl_expected+4
567 0001B136 21 03 13 00e9 jeql L293
568 0001B13B L9999:
569 0001B13B # errcnt++; /* bump error count */
570 0001B13B 6d effffffaf7 incl _errcnt
571 0001B141 # if( prt_error ) {
572 0001B141 5d effffffaf1 tstl _prt_error
573 0001B147 21 03 13 00b5 jeql L294
574 0001B14C # writes(" \n"); /* start a new line */
575 0001B14C .data 1
576 000007fc * L295:
577 000007fc * 200A00 .ascii " \12\0"
578 000007ff * .text
579 0001B14C dd 8f000007fc pushl $L295
580 0001B152 fe 08 effffffadf callf $8,_writes
581 0001B159 # writes("cycle: ");
582 0001B159 .data 1
583 000007ff * L296:
584 000007ff * 6379636C653A2000 .ascii "cycle: \0"
585 00000807 * .text
586 0001B159 dd 8f000007ff pushl $L296
587 0001B15F fe 08 effffffad2 callf $8,_writes
588 0001B166 # writed( cycle );
589 0001B166 dd effffffacc pushl _cycle
590 0001B16C fe 08 effffffac5 callf $8,_writed
591 0001B173 # writes(" TSTD test ");
592 0001B173 .data 1
593 00000807 * L297:
594 00000807 * 2020545354442074657374200 .ascii " TSTD test \0"
0
595 00000814 * .text
596 0001B173 dd 8f00000807 pushl $L297
597 0001B179 fe 08 effffffab8 callf $8,_writes
598 0001B180 # writed( test_no );
599 0001B180 dd effffffab2 pushl _test_no
600 0001B186 fe 08 effffffaab callf $8,_writed
601 0001B18D # writes(", subtest 3 - THE ACC WAS MODIFIED\n");
602 0001B18D .data 1
603 00000814 * L298:
604 00000814 * 2C20737562746573742033202 .ascii ", subtest 3 - THE ACC WAS MODIFIED\12\0"
D205448452041434320574153
204D4F4449464945440A00
605 00000838 * .text
606 0001B18D dd 8f00000814 pushl $L298
607 0001B193 fe 08 effffffa9e callf $8,_writes
608 0001B19A # print_tstd_data(); /* print the operands */
609 0001B19A fe 04 ef00000091 callf $4,_print_tstd_data
610 0001B1A1 # writes(", index = ");
611 0001B1A1 .data 1
612 00000838 * L299:
613 00000838 * 2C2020696E646578203D2000 .ascii ", index = \0"
614 00000844 * .text
615 0001B1A1 dd 8f00000838 pushl $L299
616 0001B1A7 fe 08 effffffa8a callf $8,_writes
617 0001B1AE # writed( index );
618 0001B1AE dd effffffa84 pushl _index
619 0001B1B4 fe 08 effffffa7d callf $8,_writed
620 0001B1BB # writec('\n');
621 0001B1BB dd 0a pushl $10
622 0001B1BD fe 08 effffffa74 callf $8,_writec
623 0001B1C4 # writes(" expected Acc = ");
624 0001B1C4 .data 1
625 00000844 * L300:
626 00000844 * 2020202020202020202020202 .ascii " expected Acc = \0"
0202020202020202020202020
2020202020206578706563746
56420416363203D2000
627 00000873 * .text
628 0001B1C4 dd 8f00000844 pushl $L300
629 0001B1CA fe 08 effffffa67 callf $8,_writes
630 0001B1D1 # write32h( dbl_expected.m );
631 0001B1D1 dd effffffa61 pushl _dbl_expected
632 0001B1D7 fe 08 effffffa5a callf $8,_write32h
633 0001B1DE # writec(' ');
634 0001B1DE dd 20 pushl $32
635 0001B1E0 fe 08 effffffa51 callf $8,_writec
636 0001B1E7 # write32h( dbl_expected.l );
637 0001B1E7 dd effffffa4f pushl _dbl_expected+4
638 0001B1ED fe 08 effffffa44 callf $8,_write32h
639 0001B1F4 # writes("\n");
640 0001B1F4 .data 1
641 00000873 * L301:
642 00000873 * 0A00 .ascii "\12\0"
643 00000875 * .text
644 0001B1F4 dd 8f00000873 pushl $L301
645 0001B1FA fe 08 effffffa37 callf $8,_writes
646 0001B201 # }
647 0001B201 # if( halt_flg )
648 0001B201 L294:
649 0001B201 5d effffffa31 tstl _halt_flg
650 0001B207 31 09 jeql L302
651 0001B209 # tstd_er_halt( BAD_ACC_HLT ); /* halt on error */
652 0001B209 dd 01 pushl $1
653 0001B20B fe 08 ef00000088 callf $8,_tstd_er_halt
654 0001B212 # if( loop_on_err ) {
655 0001B212 L302:
656 0001B212 5d effffffa20 tstl _loop_on_err
657 0001B218 31 0a jeql L303
658 0001B21A # force_loop = TRUE; /* set force loop flag */
659 0001B21A 0d 01 effffffa17 movl $1,_force_loop
660 0001B221 # asm("brw _tstd_3_lp1"); /* loop on the error */
661 0001B221 13 fee1 brw _tstd_3_lp1
662 0001B224 # } /* end of loop on error */
663 0001B224 # } /* end of register corruption error */
664 0001B224 L303:
665 0001B224 # } /* end of tstd data WHILE loop */
666 0001B224 L293:
667 0001B224 L287:
668 0001B224 6d effffffa0e incl _index
669 0001B22A 13 fe79 jbr L289
670 0001B22D L288:
671 0001B22D # } /* end of subtest 3 */
672 0001B22D 40 ret#2
673 0001B22E .set L283,0x0
674 0001B22E L285:
675 0001B22E 13 fe62 jbr L286
676 0001B231 .data
677 00000720 * .text
678 0001B231 00 .align 1
679 0001B232 .globl _print_tstd_data
680 0001B232 _print_tstd_data:
681 0001B232 0000 .word L304
682 0001B234 #
683 0001B234 #
684 0001B234 #
685 0001B234 # /**************************************************************************
686 0001B234 # *
687 0001B234 # * PRINT THE DATA AND STORE RESULTS
688 0001B234 # *
689 0001B234 # * initial Acc = xxxxxxxx xxxxxxxx, final Acc = xxxxxxxx xxxxxxxx, index = xx
690 0001B234 # **************************************************************************/
691 0001B234 # print_tstd_data()
692 0001B234 # {
693 0001B234 11 61 jbr L306
694 0001B236 L307:
695 0001B236 # writes("initial Acc = ");
696 0001B236 .data 1
697 00000875 * L308:
698 00000875 * 696E697469616C20416363203 .ascii "initial Acc = \0"
D2000
699 00000884 * .text
700 0001B236 dd 8f00000875 pushl $L308
701 0001B23C fe 08 effffff9f5 callf $8,_writes
702 0001B243 # write32h( dbl_ld_acc.m );
703 0001B243 dd effffff9ef pushl _dbl_ld_acc
704 0001B249 fe 08 effffff9e8 callf $8,_write32h
705 0001B250 # writec(' ');
706 0001B250 dd 20 pushl $32
707 0001B252 fe 08 effffff9df callf $8,_writec
708 0001B259 # write32h( dbl_ld_acc.l );
709 0001B259 dd effffff9dd pushl _dbl_ld_acc+4
710 0001B25F fe 08 effffff9d2 callf $8,_write32h
711 0001B266 # writes(", final Acc = ");
712 0001B266 .data 1
713 00000884 * L309:
714 00000884 * 2C202066696E616C204163632 .ascii ", final Acc = \0"
03D2000
715 00000894 * .text
716 0001B266 dd 8f00000884 pushl $L309
717 0001B26C fe 08 effffff9c5 callf $8,_writes
718 0001B273 # write32h( dbl_st_acc.m );
719 0001B273 dd effffff9bf pushl _dbl_st_acc
720 0001B279 fe 08 effffff9b8 callf $8,_write32h
721 0001B280 # writec(' ');
722 0001B280 dd 20 pushl $32
723 0001B282 fe 08 effffff9af callf $8,_writec
724 0001B289 # write32h( dbl_st_acc.l );
725 0001B289 dd effffff9ad pushl _dbl_st_acc+4
726 0001B28F fe 08 effffff9a2 callf $8,_write32h
727 0001B296 # }
728 0001B296 40 ret#2
729 0001B297 .set L304,0x0
730 0001B297 L306:
731 0001B297 11 9d jbr L307
732 0001B299 .data
733 00000720 * .text
734 0001B299 00 .align 1
735 0001B29A .globl _tstd_er_halt
736 0001B29A _tstd_er_halt:
737 0001B29A 0000 .word L310
738 0001B29C #
739 0001B29C #
740 0001B29C #
741 0001B29C # /**************************************************************************
742 0001B29C # *
743 0001B29C # * HALT ON ERROR ROUTINE
744 0001B29C # *
745 0001B29C # **************************************************************************/
746 0001B29C # tstd_er_halt( halt_code )
747 0001B29C # int halt_code;
748 0001B29C # {
749 0001B29C 13 00b6 jbr L312
750 0001B29F L313:
751 0001B29F # sgl_dummy1 = halt_code; /* get the error type */
752 0001B29F 0d ad04 effffff991 movl 4(fp),_sgl_dummy1
753 0001B2A7 # asm("movl _test_no,r0"); /* r0 = test number */
754 0001B2A7 0d effffff98b 50 movl _test_no,r0
755 0001B2AE # asm("movl _subtest,r1"); /* r1 = subtest number */
756 0001B2AE 0d effffff984 51 movl _subtest,r1
757 0001B2B5 # asm("movl _sgl_dummy1,r2"); /* r2 = error code */
758 0001B2B5 0d effffff97d 52 movl _sgl_dummy1,r2
759 0001B2BC # asm("movl _cycle,r3"); /* r3 = cycle count */
760 0001B2BC 0d effffff976 53 movl _cycle,r3
761 0001B2C3 # asm("movl _dbl_ld_acc,r4"); /* r4 = MS of init Acc */
762 0001B2C3 0d effffff96f 54 movl _dbl_ld_acc,r4
763 0001B2CA # asm("movl _dbl_ld_acc+4,r5"); /* r5 = LS of init Acc */
764 0001B2CA 0d effffff96c 55 movl _dbl_ld_acc+4,r5
765 0001B2D1 # asm("movl _psl_val,r6"); /* r6 = final PSL */
766 0001B2D1 0d effffff961 56 movl _psl_val,r6
767 0001B2D8 # if( halt_code == BAD_ACC_HLT ) {
768 0001B2D8 1d ad04 01 cmpl 4(fp),$1
769 0001B2DC 21 1e jneq L314
770 0001B2DE # asm("movl _dbl_st_acc,r7"); /* r7 = MS of final Acc */
771 0001B2DE 0d effffff954 57 movl _dbl_st_acc,r7
772 0001B2E5 # asm("movl _dbl_st_acc+4,r8"); /* r8 = LS of final Acc */
773 0001B2E5 0d effffff951 58 movl _dbl_st_acc+4,r8
774 0001B2EC # asm("movl _dbl_expected,r9"); /* r9 = MS of expected */
775 0001B2EC 0d effffff946 59 movl _dbl_expected,r9
776 0001B2F3 # asm("movl _dbl_expected+4,r10"); /* r10 = LS of expected */
777 0001B2F3 0d effffff943 5a movl _dbl_expected+4,r10
778 0001B2FA # } else
779 0001B2FA 11 57 jbr L315
780 0001B2FC L314:
781 0001B2FC # if( halt_code == BAD_REG_HLT ) {
782 0001B2FC 1d ad04 02 cmpl 4(fp),$2
783 0001B300 21 3d jneq L316
784 0001B302 # sgl_dummy1 = load_regs[index2];
785 0001B302 0d effffff930 50 movl _index2,r0
786 0001B309 0d 40effffff928 movl _load_regs[r0],_sgl_dummy1
effffff923
787 0001B315 # sgl_dummy2 = store_regs[index2];
788 0001B315 0d effffff91d 50 movl _index2,r0
789 0001B31C 0d 40effffff915 movl _store_regs[r0],_sgl_dummy2
effffff910
790 0001B328 # asm("movl _index2,r7"); /* r7 = bad register # */
791 0001B328 0d effffff90a 57 movl _index2,r7
792 0001B32F # asm("movl _sgl_dummy2,r8"); /* r8 = actual value */
793 0001B32F 0d effffff903 58 movl _sgl_dummy2,r8
794 0001B336 # asm("movl _sgl_dummy1,r9"); /* r9 = expected value */
795 0001B336 0d effffff8fc 59 movl _sgl_dummy1,r9
796 0001B33D # } else
797 0001B33D 11 14 jbr L317
798 0001B33F L316:
799 0001B33F # if( halt_code == BAD_PSL_HLT ) {
800 0001B33F 1d ad04 03 cmpl 4(fp),$3
801 0001B343 21 0e jneq L318
802 0001B345 # asm("movl _exp_psl,r7"); /* r7 = expected PSL */
803 0001B345 0d effffff8ed 57 movl _exp_psl,r7
804 0001B34C # asm("movl _index,r8"); /* r8 = data index */
805 0001B34C 0d effffff8e6 58 movl _index,r8
806 0001B353 # };
807 0001B353 L318:
808 0001B353 L317:
809 0001B353 L315:
810 0001B353 # asm("halt"); /* HALT ... */
811 0001B353 00 halt
812 0001B354 # }
813 0001B354 40 ret#2
814 0001B355 .set L310,0x0
815 0001B355 L312:
816 0001B355 13 ff47 jbr L313
817 00000720 * .data
817 00000720 * .data
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