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Power 6/32 Unix version 1.21
#include "fpp_defs.h"
/*****************************************************************************
*
* TSTF - SINGLE PRECISION FLOATING POINT TEST ACC. TEST
*
*****************************************************************************/
tstf()
{
asm(".globl _tstf_t");
asm("_tstf_t:"); /* entry address */
if( ( cycle == 1 ) && ( prt_hdrs ) ) /* print headers on 1st pass */
writes(" TSTF");
tstf_1(); /* PSL flags test */
tstf_2(); /* register stability */
tstf_3(); /* accumulator stability */
if( !no_fpp_wcs ) {
tstf_4(); /* pipelined entry test */
tstf_5(); /* pipelined exit test */
};
asm("jmp *return"); /* return to the test monitor */
}
/************************************************************************
*
* SUBTEST 1 - Check for PSL corruption
*
************************************************************************/
tstf_1()
{
force_loop = FALSE; /* clear force_loop flg */
subtest = 1;
for( index = 0; index < max_tstf_1_index; index++ ) {
sgl_ld_acc = tstf_1_data[index].ld; /* get value to load */
sgl_expected = tstf_1_data[index].exp; /* get expected flags*/
for( status_index = 0; status_index < 3; status_index++ ) {
sgl_dummy1 = status_array[status_index]; /* status = +,-,0 */
/*
* If LOOP ON ERROR is set, this is the loop for this subtest.
* The force loop flag is set after the first error.
*/
asm("ldf _sgl_ld_acc"); /* load the initial value */
asm("_tstf_1_lp1:");
asm("tstl _sgl_dummy1"); /* set the PSL status */
asm("movpsl _init_psl"); /* save the initial PSL */
asm("tstf"); /* test the accmulator */
asm("nop");
asm("movpsl _psl_val"); /* save the final PSL */
asm("stf _sgl_st_acc"); /* save the final Acc. */
if( force_loop )
asm("brb _tstf_1_lp1");; /* loop on the error */
/*
* Now compare the final PSL to the initial PSL -they should be the same
*/
exp_psl = init_psl; /* get the initial PSL */
exp_psl &= 0xfffffff3; /* clear ZERO, NEGATIVE */
if( sgl_expected == ZERO )
exp_psl |= PSL_Z; /* expect the ZERO bit set */
if( sgl_expected == NEGATIVE )
exp_psl |= PSL_N; /* expect the NEG bit set */
if( psl_val != exp_psl ) {
errcnt++; /* bump the error count */
if( prt_error ) {
writes(" \n"); /* start new print line */
writes("cycle: ");
writed( cycle );
writes(" TSTF test ");
writed( test_no );
writes(
", subtest 1 - BAD FINAL PSL\n");
print_tstf_data(); /* print the operands */
writes("initial PSL = ");
write32h( init_psl );
writes(", final PSL = ");
write32h( psl_val );
writes(", expected PSL = ");
write32h( exp_psl );
writes("\n");
}
if( halt_flg )
tstf_er_halt( BAD_PSL_HLT ); /* halt on error */
if( loop_on_err ) {
force_loop = TRUE; /* set force loop flag */
asm("brw _tstf_1_lp1"); /* loop on the error */
} /* end of loop on error */
} /* end of PSL corruption error */
} /* end of initial status WHILE loop */
} /* end of data pattern WHILE loop */
} /* end of subtest 1 */
/************************************************************************
*
* SUBTEST 2 - Check for register corruption
*
************************************************************************/
tstf_2()
{
force_loop = FALSE; /* clear force_loop flg */
subtest = 2;
fill_reg_buf( load_regs ); /* get patterns for regs */
for( index = 0; index < max_tstf_1_index; index++ ) {
sgl_ld_acc = tstf_1_data[index].ld; /* get value to load */
sgl_expected = tstf_1_data[index].exp; /* get expected flags*/
for( status_index = 0; status_index < 3; status_index++ ) {
sgl_dummy1 = status_array[status_index]; /* status = +,-,0 */
/*
* If LOOP ON ERROR is set, this is the loop for this subtest.
* The force loop flag is set after the first error.
*/
asm("_tstf_2_lp1:");
asm("loadr $0x1fff,_load_regs"); /* load regs 0 - 12 */
asm("ldf _sgl_ld_acc"); /* load the Acc. */
asm("nop");
asm("tstf"); /* test the acc. */
asm("nop");
asm("storer $0x1fff,_store_regs"); /* store regs 0 - 12 */
asm("stf _sgl_st_acc"); /* save the acc. */
if( force_loop )
asm("brb _tstf_2_lp1");; /* loop on the error */
/*
* Now compare the stored register values to those that were loaded
*/
index2 = 0;
while( (load_regs[index2] == store_regs[index2]) &&
(index2 < 13) )
index2++; /* check reg values */
if( index2 < 13 ) { /* error if index2 < 13 */
errcnt++; /* bump the error count */
if( prt_error ) {
writes(" \n"); /* start a new print line */
writes("cycle: ");
writed( cycle );
writes(" TSTF test ");
writed( test_no );
writes(", subtest 2 - A REGISTER WAS MODIFIED\n");
print_tstf_data(); /* print the operands */
writes("register "); /* print the information */
writed( index2 ); /* about the corrupted */
writes(" = "); /* register */
write32h( store_regs[index2] );
writes(", should be = ");
write32h( load_regs[index2] );
writes("\n");
}
if( halt_flg )
tstf_er_halt( BAD_REG_HLT ); /* halt on error */
if( loop_on_err ) {
force_loop = TRUE; /* set force loop flag */
asm("brw _tstf_2_lp1"); /* loop on the error */
} /* end of loop on error */
} /* end of register corruption error */
} /* end of initial PSL WHILE loop */
} /* end of tstf data WHILE loop */
} /* end of subtest 2 */
/************************************************************************
*
* SUBTEST 3 - Check for accumulator corruption
*
************************************************************************/
tstf_3()
{
force_loop = FALSE; /* clear force_loop flg */
subtest = 3;
for( index = 0; index < max_tstf_1_index; index++ ) {
sgl_ld_acc = tstf_1_data[index].ld; /* get value to load */
if( sgl_ld_acc & 0x7f800000 )
sgl_expected = sgl_ld_acc; /* the Acc should not change */
else
sgl_expected = 0; /* expect a '0' final Acc */
/*
* If LOOP ON ERROR is set, this is the loop for this subtest.
* The force loop flag is set after the first error.
*/
asm("_tstf_3_lp1:");
asm("ldf _sgl_ld_acc");
asm("nop");
asm("tstf"); /* test the accumulator */
asm("nop");
asm("stf _sgl_st_acc"); /* save the accumulator */
if( force_loop )
asm("brb _tstf_3_lp1");; /* loop on the error */
/*
* Now compare the stored accumulator to the value that was loaded
*/
if( sgl_st_acc != sgl_expected ) { /* Acc corrupted? */
errcnt++; /* bump error count */
if( prt_error ) {
writes(" \n"); /* start a new line */
writes("cycle: ");
writed( cycle );
writes(" TSTF test ");
writed( test_no );
writes(", subtest 3 (Cache Data) - THE ACC WAS MODIFIED\n");
print_tstf_data(); /* print the operands */
writes(" expected Acc = ");
write32h( sgl_expected );
writes("\n");
}
if( halt_flg )
tstf_er_halt( BAD_ACC_HLT ); /* halt on error */
if( loop_on_err ) {
force_loop = TRUE; /* set force loop flag */
asm("brw _tstf_3_lp1"); /* loop on the error */
} /* end of loop on error */
} /* end of register corruption error */
} /* end of tstf data WHILE loop */
} /* end of subtest 3 */
/************************************************************************
*
* SUBTEST 4 - pipelined entry test
*
************************************************************************/
tstf_4()
{
force_loop = FALSE;
subtest = 4;
for( index = 0; index < max_tstf_1_index; index++ ) {
sgl_ld_acc = tstf_1_data[index].ld; /* get value to negate */
sgl_expected = tstf_1_data[index].exp; /* get expected result */
for( status_index = 0; status_index < 3; status_index++ ) {
sgl_dummy1 = status_array[status_index]; /* status = +,-,0 */
/*
* If LOOP ON ERROR is set, this is the loop for this subtest.
* The force loop flag is set after the first error.
*/
asm("_tstf_4_lp1:");
asm("ldf $0"); /* load Acc. with 0.0 */
asm("tstl _sgl_dummy1"); /* set the PSL status */
asm("movpsl _init_psl"); /* save initial PSL */
asm("addf _sgl_ld_acc"); /* add the value */
asm("tstf"); /* test accumulator */
asm("movpsl _psl_val"); /* save final PSL */
asm("stf _sgl_st_acc"); /* store the result */
if( force_loop )
asm("brb _tstf_4_lp1");; /* loop on the error */
/*
* end error loop - test the results
*/
exp_psl = init_psl; /* get initial PSL */
exp_psl &= 0xfffffff3; /* clear ZERO, NEGATIVE */
if( sgl_expected == ZERO )
exp_psl |= PSL_Z; /* expect ZERO bit set */
if( sgl_expected == NEGATIVE )
exp_psl |= PSL_N; /* expect NEG bit set */
if( psl_val != exp_psl ) {
errcnt++; /* bump the error count */
if( prt_error ) {
writes(" \n"); /* start new print line */
writes("cycle: ");
writed( cycle );
writes(" TSTF test ");
writed( test_no );
writes(
", subtest 4 (Piped Entry) -BAD FINAL PSL\n");
print_tstf_data(); /* print operands */
writes("initial PSL = ");
write32h( init_psl );
writes(", final PSL = ");
write32h( psl_val );
writes(", expected PSL = ");
write32h( exp_psl );
writes("\n");
}
if( halt_flg )
tstf_er_halt( BAD_PSL_HLT ); /* halt on error */
if( loop_on_err ) {
force_loop = TRUE; /* set loop flag */
asm("brw _tstf_4_lp1"); /* loop on error */
} /* end of loop on error */
} /* end of PSL corruption error */
} /* end of status WHILE loop */
} /* end of data WHILE loop */
} /* end of subtest 4 */
/************************************************************************
*
* SUBTEST 5 - pipelined exit test
*
************************************************************************/
tstf_5()
{
force_loop = FALSE;
subtest = 5;
for( index = 0; index < max_tstf_1_index; index++ ) {
sgl_ld_acc = tstf_1_data[index].ld; /* get value to test */
if( sgl_ld_acc & 0x7f800000 )
sgl_expected = sgl_ld_acc; /* the Acc should not change */
else
sgl_expected = 0; /* expect a '0' final Acc */
/*
* If LOOP ON ERROR is set, this is the loop for this subtest.
* The force loop flag is set after the first error.
*/
asm("_tstf_5_lp1:");
asm("movl $0,r0"); /* clear r0 */
asm("ldf _sgl_ld_acc"); /* load the value */
asm("tstf"); /* test the accumulator */
asm("addf r0"); /* add a zero */
asm("stf _sgl_st_acc"); /* store the result */
if( force_loop )
asm("brb _tstf_5_lp1");; /* loop on the error */
/*
* end error loop - test the results
*/
if( sgl_st_acc != sgl_expected ) { /* COMPARE the values */
errcnt++; /* bump the error count */
if( prt_error ) {
writes(" \n"); /* start a new print line */
writes("cycle: ");
writed( cycle );
writes(" TSTF test ");
writed( test_no );
writes(
", subtest 5 (Piped Exit) - BAD FINAL ACC\n");
print_tstf_data();
writes(" expected Acc = ");
write32h( sgl_expected );
writec('\n');
}
if( halt_flg )
tstf_er_halt( BAD_ACC_HLT ); /* halt on the error */
if( loop_on_err ) {
force_loop = TRUE; /* set the force loop flag */
asm("brw _tstf_5_lp1"); /* and loop on the error */
} /* end of loop on error */
} /* end of compare error */
} /* end of WHILE loop */
} /* end of subtest 5 */
/**************************************************************************
*
* PRINT THE DATA AND STORE RESULTS
*
* initial Acc = xxxxxxxx, final Acc = xxxxxxxx, data index = xx
**************************************************************************/
print_tstf_data()
{
writes("initial Acc = ");
write32h( sgl_ld_acc );
writes(", final Acc = ");
write32h( sgl_st_acc );
writes(", data index = ");
writed( index );
writec('\n');
}
/**************************************************************************
*
* HALT ON ERROR ROUTINE
*
**************************************************************************/
tstf_er_halt( halt_code )
int halt_code;
{
sgl_dummy1 = halt_code; /* get the error type */
asm("movl _test_no,r0"); /* r0 = test number */
asm("movl _subtest,r1"); /* r1 = subtest number */
asm("movl _sgl_dummy1,r2"); /* r2 = error code */
asm("movl _cycle,r3"); /* r3 = cycle count */
asm("movl _sgl_ld_acc,r4"); /* r4 = initial data */
asm("movl _psl_val,r5"); /* r5 = final PSL */
if( halt_code == BAD_ACC_HLT ) {
asm("movl _sgl_st_acc,r6"); /* r6 = actual value */
asm("movl _sgl_expected,r7"); /* r7 = expected value */
} else
if( halt_code == BAD_REG_HLT ) {
sgl_dummy1 = load_regs[index2];
sgl_dummy2 = store_regs[index2];
asm("movl _index2,r6"); /* r6 = bad register # */
asm("movl _sgl_dummy2,r7"); /* r7 = actual value */
asm("movl _sgl_dummy1,r8"); /* r8 = expected value */
} else
if( halt_code == BAD_PSL_HLT ) {
asm("movl _exp_psl,r6"); /* r6 = expected PSL */
asm("movl _index,r7"); /* r7 = data index */
};
asm("halt"); /* HALT ... */
}
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